Angel Pons | f23ae0b | 2020-04-02 23:48:12 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 2 | |
| 3 | #ifndef _CPU_INTEL_HASWELL_H |
| 4 | #define _CPU_INTEL_HASWELL_H |
| 5 | |
Elyes HAOUAS | 88f5c71 | 2019-10-16 12:45:47 +0200 | [diff] [blame] | 6 | #include <stdint.h> |
Aaron Durbin | 39ecc65 | 2013-05-02 09:42:13 -0500 | [diff] [blame] | 7 | |
Duncan Laurie | 118d105 | 2013-07-09 15:34:25 -0700 | [diff] [blame] | 8 | /* Haswell CPU types */ |
| 9 | #define HASWELL_FAMILY_MOBILE 0x306c0 |
| 10 | #define HASWELL_FAMILY_ULT 0x40650 |
| 11 | |
| 12 | /* Haswell CPU steppings */ |
| 13 | #define HASWELL_STEPPING_MOBILE_A0 1 |
| 14 | #define HASWELL_STEPPING_MOBILE_B0 2 |
| 15 | #define HASWELL_STEPPING_MOBILE_C0 3 |
| 16 | #define HASWELL_STEPPING_MOBILE_D0 4 |
| 17 | #define HASWELL_STEPPING_ULT_B0 0 |
| 18 | #define HASWELL_STEPPING_ULT_C0 1 |
| 19 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 20 | /* Haswell bus clock is fixed at 100MHz */ |
Duncan Laurie | 118d105 | 2013-07-09 15:34:25 -0700 | [diff] [blame] | 21 | #define HASWELL_BCLK 100 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 22 | |
Elyes HAOUAS | a6a396d | 2019-05-26 13:25:30 +0200 | [diff] [blame] | 23 | #define MSR_CORE_THREAD_COUNT 0x35 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 24 | #define MSR_FEATURE_CONFIG 0x13c |
| 25 | #define MSR_FLEX_RATIO 0x194 |
| 26 | #define FLEX_RATIO_LOCK (1 << 20) |
| 27 | #define FLEX_RATIO_EN (1 << 16) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 28 | #define MSR_TEMPERATURE_TARGET 0x1a2 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 29 | #define MSR_LT_LOCK_MEMORY 0x2e7 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 30 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 31 | #define MSR_PLATFORM_INFO 0xce |
| 32 | #define PLATFORM_INFO_SET_TDP (1 << 29) |
Elyes HAOUAS | 4e6b790 | 2018-10-02 08:44:47 +0200 | [diff] [blame] | 33 | #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 34 | #define MSR_PMG_IO_CAPTURE_BASE 0xe4 |
| 35 | |
| 36 | #define MSR_MISC_PWR_MGMT 0x1aa |
| 37 | #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) |
| 38 | #define MSR_TURBO_RATIO_LIMIT 0x1ad |
| 39 | #define MSR_POWER_CTL 0x1fc |
| 40 | |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 41 | #define MSR_C_STATE_LATENCY_CONTROL_0 0x60a |
| 42 | #define MSR_C_STATE_LATENCY_CONTROL_1 0x60b |
| 43 | #define MSR_C_STATE_LATENCY_CONTROL_2 0x60c |
| 44 | #define MSR_C_STATE_LATENCY_CONTROL_3 0x633 |
| 45 | #define MSR_C_STATE_LATENCY_CONTROL_4 0x634 |
| 46 | #define MSR_C_STATE_LATENCY_CONTROL_5 0x635 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 47 | #define IRTL_VALID (1 << 15) |
| 48 | #define IRTL_1_NS (0 << 10) |
| 49 | #define IRTL_32_NS (1 << 10) |
| 50 | #define IRTL_1024_NS (2 << 10) |
| 51 | #define IRTL_32768_NS (3 << 10) |
| 52 | #define IRTL_1048576_NS (4 << 10) |
| 53 | #define IRTL_33554432_NS (5 << 10) |
| 54 | #define IRTL_RESPONSE_MASK (0x3ff) |
| 55 | |
| 56 | /* long duration in low dword, short duration in high dword */ |
| 57 | #define MSR_PKG_POWER_LIMIT 0x610 |
| 58 | #define PKG_POWER_LIMIT_MASK 0x7fff |
| 59 | #define PKG_POWER_LIMIT_EN (1 << 15) |
| 60 | #define PKG_POWER_LIMIT_CLAMP (1 << 16) |
| 61 | #define PKG_POWER_LIMIT_TIME_SHIFT 17 |
| 62 | #define PKG_POWER_LIMIT_TIME_MASK 0x7f |
| 63 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 64 | #define MSR_VR_CURRENT_CONFIG 0x601 |
Aaron Durbin | 16cbf89 | 2013-07-03 16:21:28 -0500 | [diff] [blame] | 65 | #define MSR_VR_MISC_CONFIG 0x603 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 66 | #define MSR_PKG_POWER_SKU_UNIT 0x606 |
| 67 | #define MSR_PKG_POWER_SKU 0x614 |
Duncan Laurie | c70353f | 2013-06-28 14:40:38 -0700 | [diff] [blame] | 68 | #define MSR_DDR_RAPL_LIMIT 0x618 |
Aaron Durbin | 16cbf89 | 2013-07-03 16:21:28 -0500 | [diff] [blame] | 69 | #define MSR_VR_MISC_CONFIG2 0x636 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 70 | #define MSR_PP0_POWER_LIMIT 0x638 |
| 71 | #define MSR_PP1_POWER_LIMIT 0x640 |
| 72 | |
| 73 | #define MSR_CONFIG_TDP_NOMINAL 0x648 |
| 74 | #define MSR_CONFIG_TDP_LEVEL1 0x649 |
| 75 | #define MSR_CONFIG_TDP_LEVEL2 0x64a |
| 76 | #define MSR_CONFIG_TDP_CONTROL 0x64b |
| 77 | #define MSR_TURBO_ACTIVATION_RATIO 0x64c |
| 78 | |
| 79 | /* P-state configuration */ |
| 80 | #define PSS_MAX_ENTRIES 8 |
| 81 | #define PSS_RATIO_STEP 2 |
| 82 | #define PSS_LATENCY_TRANSITION 10 |
| 83 | #define PSS_LATENCY_BUSMASTER 10 |
| 84 | |
Aaron Durbin | f24262d | 2013-04-10 14:59:21 -0500 | [diff] [blame] | 85 | /* PCODE MMIO communications live in the MCHBAR. */ |
| 86 | #define BIOS_MAILBOX_INTERFACE 0x5da4 |
Angel Pons | f5dd7b6 | 2020-10-24 12:24:19 +0200 | [diff] [blame^] | 87 | #define MAILBOX_RUN_BUSY (1 << 31) |
Aaron Durbin | f24262d | 2013-04-10 14:59:21 -0500 | [diff] [blame] | 88 | #define MAILBOX_BIOS_CMD_READ_PCS 1 |
| 89 | #define MAILBOX_BIOS_CMD_WRITE_PCS 2 |
| 90 | #define MAILBOX_BIOS_CMD_READ_CALIBRATION 0x509 |
| 91 | #define MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL 0x909 |
Duncan Laurie | e1e87e0 | 2013-04-26 10:35:19 -0700 | [diff] [blame] | 92 | #define MAILBOX_BIOS_CMD_READ_PCH_POWER 0xa |
| 93 | #define MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT 0xb |
Aaron Durbin | f24262d | 2013-04-10 14:59:21 -0500 | [diff] [blame] | 94 | /* Errors are returned back in bits 7:0. */ |
| 95 | #define MAILBOX_BIOS_ERROR_NONE 0 |
| 96 | #define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1 |
| 97 | #define MAILBOX_BIOS_ERROR_TIMEOUT 2 |
| 98 | #define MAILBOX_BIOS_ERROR_ILLEGAL_DATA 3 |
| 99 | #define MAILBOX_BIOS_ERROR_RESERVED 4 |
| 100 | #define MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID 5 |
| 101 | #define MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED 6 |
| 102 | #define MAILBOX_BIOS_ERROR_VR_ERROR 7 |
| 103 | /* Data is passed through bits 31:0 of the data register. */ |
| 104 | #define BIOS_MAILBOX_DATA 0x5da0 |
| 105 | |
Aaron Durbin | 8ce667e | 2013-02-15 21:45:06 -0600 | [diff] [blame] | 106 | /* Sanity check config options. */ |
Kyösti Mälkki | 825646e | 2019-08-02 06:14:50 +0300 | [diff] [blame] | 107 | #if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)) |
| 108 | # error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)" |
Aaron Durbin | 8ce667e | 2013-02-15 21:45:06 -0600 | [diff] [blame] | 109 | #endif |
| 110 | #if (CONFIG_SMM_TSEG_SIZE < 0x800000) |
| 111 | # error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB" |
| 112 | #endif |
| 113 | #if ((CONFIG_SMM_TSEG_SIZE & (CONFIG_SMM_TSEG_SIZE - 1)) != 0) |
| 114 | # error "CONFIG_SMM_TSEG_SIZE is not a power of 2" |
| 115 | #endif |
| 116 | #if ((CONFIG_IED_REGION_SIZE & (CONFIG_IED_REGION_SIZE - 1)) != 0) |
| 117 | # error "CONFIG_IED_REGION_SIZE is not a power of 2" |
| 118 | #endif |
| 119 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 120 | /* Lock MSRs */ |
| 121 | void intel_cpu_haswell_finalize_smm(void); |
Kyösti Mälkki | 80f963c | 2019-09-12 15:41:32 +0300 | [diff] [blame] | 122 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 123 | /* Configure power limits for turbo mode */ |
| 124 | void set_power_limits(u8 power_limit_1_time); |
| 125 | int cpu_config_tdp_levels(void); |
Aaron Durbin | f7cdfe5 | 2013-02-16 00:05:52 -0600 | [diff] [blame] | 126 | |
Duncan Laurie | 118d105 | 2013-07-09 15:34:25 -0700 | [diff] [blame] | 127 | /* CPU identification */ |
| 128 | int haswell_family_model(void); |
| 129 | int haswell_stepping(void); |
| 130 | int haswell_is_ult(void); |
| 131 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 132 | #endif |