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review.coreboot.org / coreboot / f5c463f5e6458ea45b9f3461f94800f9c87feea1 / . / src / vendorcode / amd / agesa / f15tn / AMD.h
blob: 31d38db5563e014af7bdcf7fafbe175adb6ae52e [file] [log] [blame]
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]1/* $NoKeywords:$ */
2/**
3 * @file
4 *
5 * Agesa structures and definitions
6 *
7 * Contains AMD AGESA core interface
8 *
9 * @xrefitem bom "File Content Label" "Release Content"
10 * @e project: AGESA
11 * @e sub-project: Include
12 * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
13 */
14/*****************************************************************************
15 *
Siyuan Wang641f00c2013-06-08 11:50:55 +0800[diff] [blame]16 * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
17 * All rights reserved.
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]18 *
Siyuan Wang641f00c2013-06-08 11:50:55 +0800[diff] [blame]19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are met:
21 * * Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer.
23 * * Redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution.
26 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
27 * its contributors may be used to endorse or promote products derived
28 * from this software without specific prior written permission.
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]29 *
Siyuan Wang641f00c2013-06-08 11:50:55 +0800[diff] [blame]30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
32 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
34 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
35 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
36 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
37 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
39 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]40 *
41 ***************************************************************************/
42
43
44#ifndef _AMD_H_
45#define _AMD_H_
46
47#define AGESA_REVISION "Arch2008"
48#define AGESA_ID "AGESA"
49
50#define Int16FromChar(a,b) ((a) << 0 | (b) << 8)
51#define Int32FromChar(a,b,c,d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24)
52//
53//
54// AGESA Types and Definitions
55//
56//
57#define LAST_ENTRY 0xFFFFFFFF
58#define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D')
59#define IOCF8 0xCF8
60#define IOCFC 0xCFC
61
62/// The return status for all AGESA public services.
63///
64/// Services return the most severe status of any logged event. Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
65/// will have log entries with more detail.
66///
67typedef enum {
68 AGESA_SUCCESS = 0, ///< The service completed normally. Info may be logged.
69 AGESA_UNSUPPORTED, ///< The dispatcher or create struct had an unimplemented function requested.
70 ///< Not logged.
71 AGESA_BOUNDS_CHK, ///< A dynamic parameter was out of range and the service was not provided.
72 ///< Example, memory address not installed, heap buffer handle not found.
73 ///< Not Logged.
74 // AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
75 AGESA_ALERT, ///< An observed condition, but no loss of function.
76 ///< See log. Example, HT CRC.
77 AGESA_WARNING, ///< Possible or minor loss of function. See Log.
78 AGESA_ERROR, ///< Significant loss of function, boot may be possible. See Log.
79 AGESA_CRITICAL, ///< Continue boot only to notify user. See Log.
80 AGESA_FATAL, ///< Halt booting. See Log, however Fatal errors pertaining to heap problems
81 ///< may not be able to reliably produce log events.
82 AgesaStatusMax ///< Not a status, for limit checking.
83} AGESA_STATUS;
84
85/// For checking whether a status is at or above the mandatory log level.
86#define AGESA_STATUS_LOG_LEVEL AGESA_ALERT
87
88/**
89 * Callout method to the host environment.
90 *
91 * Callout using a dispatch with appropriate thunk layer, which is determined by the host environment.
92 *
93 * @param[in] Function The specific callout function being invoked.
94 * @param[in] FcnData Function specific data item.
95 * @param[in,out] ConfigPtr Reference to Callout params.
96 */
97typedef AGESA_STATUS (*CALLOUT_ENTRY) (
98 IN UINT32 Function,
99 IN UINTN FcnData,
100 IN OUT VOID *ConfigPtr
101 );
102
103typedef AGESA_STATUS (*IMAGE_ENTRY) (VOID *ConfigPtr);
104typedef AGESA_STATUS (*MODULE_ENTRY) (VOID *ConfigPtr);
105
106///This allocation type is used by the AmdCreateStruct entry point
107typedef enum {
108 PreMemHeap = 0, ///< Create heap in cache.
109 PostMemDram, ///< Create heap in memory.
110 ByHost ///< Create heap by Host.
111} ALLOCATION_METHOD;
112
113/// These width descriptors are used by the library function, and others, to specify the data size
114typedef enum ACCESS_WIDTH {
115 AccessWidth8 = 1, ///< Access width is 8 bits.
116 AccessWidth16, ///< Access width is 16 bits.
117 AccessWidth32, ///< Access width is 32 bits.
118 AccessWidth64, ///< Access width is 64 bits.
119
120 AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data.
121 AccessS3SaveWidth16, ///< Save 16 bits data.
122 AccessS3SaveWidth32, ///< Save 32 bits data.
123 AccessS3SaveWidth64, ///< Save 64 bits data.
124} ACCESS_WIDTH;
125
126/// AGESA struct name
127typedef enum {
128 // AGESA BASIC FUNCTIONS
129 AMD_INIT_RECOVERY = 0x00020000, ///< AmdInitRecovery entry point handle
130 AMD_CREATE_STRUCT, ///< AmdCreateStruct handle
131 AMD_INIT_EARLY, ///< AmdInitEarly entry point handle
132 AMD_INIT_ENV, ///< AmdInitEnv entry point handle
133 AMD_INIT_LATE, ///< AmdInitLate entry point handle
134 AMD_INIT_MID, ///< AmdInitMid entry point handle
135 AMD_INIT_POST, ///< AmdInitPost entry point handle
136 AMD_INIT_RESET, ///< AmdInitReset entry point handle
137 AMD_INIT_RESUME, ///< AmdInitResume entry point handle
138 AMD_RELEASE_STRUCT, ///< AmdReleaseStruct handle
139 AMD_S3LATE_RESTORE, ///< AmdS3LateRestore entry point handle
140 AMD_S3_SAVE, ///< AmdS3Save entry point handle
141 AMD_GET_APIC_ID, ///< AmdGetApicId entry point handle
142 AMD_GET_PCI_ADDRESS, ///< AmdGetPciAddress entry point handle
143 AMD_IDENTIFY_CORE, ///< AmdIdentifyCore general service handle
144 AMD_READ_EVENT_LOG, ///< AmdReadEventLog general service handle
145 AMD_GET_EXECACHE_SIZE, ///< AmdGetAvailableExeCacheSize general service handle
146 AMD_LATE_RUN_AP_TASK, ///< AmdLateRunApTask entry point handle
147 AMD_IDENTIFY_DIMMS ///< AmdIdentifyDimm general service handle
148} AGESA_STRUCT_NAME;
149
150 /* ResetType constant values */
151#define WARM_RESET_WHENEVER 1
152#define COLD_RESET_WHENEVER 2
153#define WARM_RESET_IMMEDIATELY 3
154#define COLD_RESET_IMMEDIATELY 4
155
156
157// AGESA Structures
158
159/// The standard header for all AGESA services.
160/// For internal AGESA naming conventions, see @ref amdconfigparamname .
161typedef struct {
162 IN UINT32 ImageBasePtr; ///< The AGESA Image base address.
163 IN UINT32 Func; ///< The service desired
164 IN UINT32 AltImageBasePtr; ///< Alternate Image location
165 IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA
166 IN UINT8 HeapStatus; ///< For heap status from boot time slide.
167 IN UINT64 HeapBasePtr; ///< Location of the heap
168 IN OUT UINT8 Reserved[7]; ///< This space is reserved for future use.
169} AMD_CONFIG_PARAMS;
170
171
172/// Create Struct Interface.
173typedef struct {
174 IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
175 IN AGESA_STRUCT_NAME AgesaFunctionName; ///< The service to init
176 IN ALLOCATION_METHOD AllocationMethod; ///< How to handle buffer allocation
177 IN OUT UINT32 NewStructSize; ///< The size of the allocated data, in for ByHost, else out only.
178 IN OUT VOID *NewStructPtr; ///< The struct for the service.
179 ///< The struct to init for ByHost allocation,
180 ///< the initialized struct on return.
181} AMD_INTERFACE_PARAMS;
182
183#define FUNC_0 0 // bit-placed for PCI address creation
184#define FUNC_1 1
185#define FUNC_2 2
186#define FUNC_3 3
187#define FUNC_4 4
188#define FUNC_5 5
189#define FUNC_6 6
190#define FUNC_7 7
191
192/// AGESA Binary module header structure
193typedef struct {
194 IN UINT32 Signature; ///< Binary Signature
195 IN CHAR8 CreatorID[8]; ///< 8 characters ID
196 IN CHAR8 Version[12]; ///< 12 characters version
197 IN UINT32 ModuleInfoOffset; ///< Offset of module
198 IN UINT32 EntryPointAddress; ///< Entry address
199 IN UINT32 ImageBase; ///< Image base
200 IN UINT32 RelocTableOffset; ///< Relocate Table offset
201 IN UINT32 ImageSize; ///< Size
202 IN UINT16 Checksum; ///< Checksum
203 IN UINT8 ImageType; ///< Type
204 IN UINT8 V_Reserved; ///< Reserved
205} AMD_IMAGE_HEADER;
206/// AGESA Binary module header structure
207typedef struct _AMD_MODULE_HEADER {
208 IN UINT32 ModuleHeaderSignature; ///< Module signature
209 IN CHAR8 ModuleIdentifier[8]; ///< 8 characters ID
210 IN CHAR8 ModuleVersion[12]; ///< 12 characters version
211 IN VOID *ModuleDispatcher; ///< A pointer point to dispatcher
212 IN struct _AMD_MODULE_HEADER *NextBlock; ///< Next module header link
213} AMD_MODULE_HEADER;
214
215// AMD_CODE_HEADER Signatures.
216#define AGESA_CODE_SIGNATURE {'!', '!', 'A', 'G', 'E', 'S', 'A', ' '}
217#define CIMXNB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'}
218#define CIMXSB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'}
219
220/// AGESA_CODE_SIGNATURE
221typedef struct {
222 IN CHAR8 Signature[8]; ///< code header Signature
223 IN CHAR8 ComponentName[8]; ///< 8 character name of the code module
224 IN CHAR8 Version[12]; ///< 12 character version string
225 IN CHAR8 TerminatorNull; ///< null terminated string
226 IN CHAR8 VerReserved[7]; ///< reserved space
227} AMD_CODE_HEADER;
228
229/// Extended PCI address format
230typedef struct {
231 IN OUT UINT32 Register:12; ///< Register offset
232 IN OUT UINT32 Function:3; ///< Function number
233 IN OUT UINT32 Device:5; ///< Device number
234 IN OUT UINT32 Bus:8; ///< Bus number
235 IN OUT UINT32 Segment:4; ///< Segment
236} EXT_PCI_ADDR;
237
238/// Union type for PCI address
239typedef union _PCI_ADDR {
240 IN UINT32 AddressValue; ///< Formal address
241 IN EXT_PCI_ADDR Address; ///< Extended address
242} PCI_ADDR;
243
244// SBDFO - Segment Bus Device Function Offset
245// 31:28 Segment (4-bits)
246// 27:20 Bus (8-bits)
247// 19:15 Device (5-bits)
248// 14:12 Function(3-bits)
249// 11:00 Offset (12-bits)
250
251#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \
252 (((UINT32)(Dev)) << 15) | (((UINT32)(Fun)) << 12) | ((UINT32)(Off)))
253#define ILLEGAL_SBDFO 0xFFFFFFFF
254
255/// CPUID data received registers format
256typedef struct {
257 OUT UINT32 EAX_Reg; ///< CPUID instruction result in EAX
258 OUT UINT32 EBX_Reg; ///< CPUID instruction result in EBX
259 OUT UINT32 ECX_Reg; ///< CPUID instruction result in ECX
260 OUT UINT32 EDX_Reg; ///< CPUID instruction result in EDX
261} CPUID_DATA;
262
263/// HT frequency for external callbacks
264typedef enum {
265 HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks
266 HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks
267 HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks
268 HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks
269 HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks
270 HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks
271 HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks
272 HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks
273 HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks
274 HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks
275 HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks
276 HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks
277 HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks
278 HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks
279 HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks
280 HT_FREQUENCY_3200M = 19, ///< HT speed 3200 for external callbacks
281 HT_FREQUENCY_MAX ///< Limit check.
282} HT_FREQUENCIES;
283// The minimum HT3 frequency
284#define HT3_FREQUENCY_MIN HT_FREQUENCY_1200M
285
286#ifndef BIT0
287 #define BIT0 0x0000000000000001ull
288#endif
289#ifndef BIT1
290 #define BIT1 0x0000000000000002ull
291#endif
292#ifndef BIT2
293 #define BIT2 0x0000000000000004ull
294#endif
295#ifndef BIT3
296 #define BIT3 0x0000000000000008ull
297#endif
298#ifndef BIT4
299 #define BIT4 0x0000000000000010ull
300#endif
301#ifndef BIT5
302 #define BIT5 0x0000000000000020ull
303#endif
304#ifndef BIT6
305 #define BIT6 0x0000000000000040ull
306#endif
307#ifndef BIT7
308 #define BIT7 0x0000000000000080ull
309#endif
310#ifndef BIT8
311 #define BIT8 0x0000000000000100ull
312#endif
313#ifndef BIT9
314 #define BIT9 0x0000000000000200ull
315#endif
316#ifndef BIT10
317 #define BIT10 0x0000000000000400ull
318#endif
319#ifndef BIT11
320 #define BIT11 0x0000000000000800ull
321#endif
322#ifndef BIT12
323 #define BIT12 0x0000000000001000ull
324#endif
325#ifndef BIT13
326 #define BIT13 0x0000000000002000ull
327#endif
328#ifndef BIT14
329 #define BIT14 0x0000000000004000ull
330#endif
331#ifndef BIT15
332 #define BIT15 0x0000000000008000ull
333#endif
334#ifndef BIT16
335 #define BIT16 0x0000000000010000ull
336#endif
337#ifndef BIT17
338 #define BIT17 0x0000000000020000ull
339#endif
340#ifndef BIT18
341 #define BIT18 0x0000000000040000ull
342#endif
343#ifndef BIT19
344 #define BIT19 0x0000000000080000ull
345#endif
346#ifndef BIT20
347 #define BIT20 0x0000000000100000ull
348#endif
349#ifndef BIT21
350 #define BIT21 0x0000000000200000ull
351#endif
352#ifndef BIT22
353 #define BIT22 0x0000000000400000ull
354#endif
355#ifndef BIT23
356 #define BIT23 0x0000000000800000ull
357#endif
358#ifndef BIT24
359 #define BIT24 0x0000000001000000ull
360#endif
361#ifndef BIT25
362 #define BIT25 0x0000000002000000ull
363#endif
364#ifndef BIT26
365 #define BIT26 0x0000000004000000ull
366#endif
367#ifndef BIT27
368 #define BIT27 0x0000000008000000ull
369#endif
370#ifndef BIT28
371 #define BIT28 0x0000000010000000ull
372#endif
373#ifndef BIT29
374 #define BIT29 0x0000000020000000ull
375#endif
376#ifndef BIT30
377 #define BIT30 0x0000000040000000ull
378#endif
379#ifndef BIT31
380 #define BIT31 0x0000000080000000ull
381#endif
382#ifndef BIT32
383 #define BIT32 0x0000000100000000ull
384#endif
385#ifndef BIT33
386 #define BIT33 0x0000000200000000ull
387#endif
388#ifndef BIT34
389 #define BIT34 0x0000000400000000ull
390#endif
391#ifndef BIT35
392 #define BIT35 0x0000000800000000ull
393#endif
394#ifndef BIT36
395 #define BIT36 0x0000001000000000ull
396#endif
397#ifndef BIT37
398 #define BIT37 0x0000002000000000ull
399#endif
400#ifndef BIT38
401 #define BIT38 0x0000004000000000ull
402#endif
403#ifndef BIT39
404 #define BIT39 0x0000008000000000ull
405#endif
406#ifndef BIT40
407 #define BIT40 0x0000010000000000ull
408#endif
409#ifndef BIT41
410 #define BIT41 0x0000020000000000ull
411#endif
412#ifndef BIT42
413 #define BIT42 0x0000040000000000ull
414#endif
415#ifndef BIT43
416 #define BIT43 0x0000080000000000ull
417#endif
418#ifndef BIT44
419 #define BIT44 0x0000100000000000ull
420#endif
421#ifndef BIT45
422 #define BIT45 0x0000200000000000ull
423#endif
424#ifndef BIT46
425 #define BIT46 0x0000400000000000ull
426#endif
427#ifndef BIT47
428 #define BIT47 0x0000800000000000ull
429#endif
430#ifndef BIT48
431 #define BIT48 0x0001000000000000ull
432#endif
433#ifndef BIT49
434 #define BIT49 0x0002000000000000ull
435#endif
436#ifndef BIT50
437 #define BIT50 0x0004000000000000ull
438#endif
439#ifndef BIT51
440 #define BIT51 0x0008000000000000ull
441#endif
442#ifndef BIT52
443 #define BIT52 0x0010000000000000ull
444#endif
445#ifndef BIT53
446 #define BIT53 0x0020000000000000ull
447#endif
448#ifndef BIT54
449 #define BIT54 0x0040000000000000ull
450#endif
451#ifndef BIT55
452 #define BIT55 0x0080000000000000ull
453#endif
454#ifndef BIT56
455 #define BIT56 0x0100000000000000ull
456#endif
457#ifndef BIT57
458 #define BIT57 0x0200000000000000ull
459#endif
460#ifndef BIT58
461 #define BIT58 0x0400000000000000ull
462#endif
463#ifndef BIT59
464 #define BIT59 0x0800000000000000ull
465#endif
466#ifndef BIT60
467 #define BIT60 0x1000000000000000ull
468#endif
469#ifndef BIT61
470 #define BIT61 0x2000000000000000ull
471#endif
472#ifndef BIT62
473 #define BIT62 0x4000000000000000ull
474#endif
475#ifndef BIT63
476 #define BIT63 0x8000000000000000ull
477#endif
478
479#endif // _AMD_H_