zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * Agesa structures and definitions |
| 6 | * |
| 7 | * Contains AMD AGESA core interface |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: Include |
| 12 | * @e \$Revision: 64574 $ @e \$Date: 2012-01-25 01:01:51 -0600 (Wed, 25 Jan 2012) $ |
| 13 | */ |
| 14 | /***************************************************************************** |
| 15 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 16 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 17 | * All rights reserved. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 18 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 19 | * Redistribution and use in source and binary forms, with or without |
| 20 | * modification, are permitted provided that the following conditions are met: |
| 21 | * * Redistributions of source code must retain the above copyright |
| 22 | * notice, this list of conditions and the following disclaimer. |
| 23 | * * Redistributions in binary form must reproduce the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer in the |
| 25 | * documentation and/or other materials provided with the distribution. |
| 26 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 27 | * its contributors may be used to endorse or promote products derived |
| 28 | * from this software without specific prior written permission. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 29 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 30 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 31 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 32 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 33 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 34 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 35 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 36 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 37 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 38 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 39 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 40 | * |
| 41 | ***************************************************************************/ |
| 42 | |
| 43 | |
| 44 | #ifndef _AGESA_H_ |
| 45 | #define _AGESA_H_ |
| 46 | |
| 47 | #include "Porting.h" |
| 48 | #include "AMD.h" |
| 49 | |
| 50 | // |
| 51 | // |
| 52 | // AGESA Types and Definitions |
| 53 | // |
| 54 | // |
| 55 | |
| 56 | // AGESA BASIC CALLOUTS |
| 57 | #define AGESA_MEM_RELEASE 0x00028000ul |
| 58 | |
| 59 | // AGESA ADVANCED CALLOUTS, Processor |
| 60 | #define AGESA_CHECK_UMA 0x00028100ul |
| 61 | #define AGESA_DO_RESET 0x00028101ul |
| 62 | #define AGESA_ALLOCATE_BUFFER 0x00028102ul |
| 63 | #define AGESA_DEALLOCATE_BUFFER 0x00028103ul |
| 64 | #define AGESA_LOCATE_BUFFER 0x00028104ul |
| 65 | #define AGESA_RUNFUNC_ONAP 0x00028105ul |
| 66 | |
| 67 | // AGESA ADVANCED CALLOUTS, HyperTransport |
| 68 | |
| 69 | // AGESA ADVANCED CALLOUTS, Memory |
| 70 | #define AGESA_READ_SPD 0x00028140ul |
| 71 | #define AGESA_HOOKBEFORE_DRAM_INIT 0x00028141ul |
| 72 | #define AGESA_HOOKBEFORE_DQS_TRAINING 0x00028142ul |
| 73 | #define AGESA_READ_SPD_RECOVERY 0x00028143ul |
| 74 | #define AGESA_HOOKBEFORE_EXIT_SELF_REF 0x00028144ul |
| 75 | #define AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY 0x00028145ul |
| 76 | |
| 77 | // AGESA IDS CALLOUTS |
| 78 | #define AGESA_GET_IDS_INIT_DATA 0x00028200ul |
| 79 | |
| 80 | // AGESA GNB CALLOUTS |
| 81 | #define AGESA_GNB_PCIE_SLOT_RESET 0x00028301ul |
| 82 | #define AGESA_GNB_GFX_GET_VBIOS_IMAGE 0x00028302ul |
| 83 | |
| 84 | // AGESA FCH CALLOUTS |
| 85 | #define AGESA_FCH_OEM_CALLOUT 0x00028401ul |
| 86 | |
| 87 | //------------------------------------------------------------------------ |
| 88 | // |
| 89 | // HyperTransport Interface |
| 90 | |
| 91 | |
| 92 | |
| 93 | //----------------------------------------------------------------------------- |
| 94 | // HT DEFINITIONS AND MACROS |
| 95 | // |
| 96 | //----------------------------------------------------------------------------- |
| 97 | |
| 98 | |
| 99 | // Width equates for call backs |
| 100 | #define HT_WIDTH_8_BITS 8 ///< Specifies 8 bit, or up to 8 bit widths. |
| 101 | #define HT_WIDTH_16_BITS 16 ///< Specifies 16 bit, or up to 16 bit widths. |
| 102 | #define HT_WIDTH_4_BITS 4 |
| 103 | #define HT_WIDTH_2_BITS 2 |
| 104 | #define HT_WIDTH_NO_LIMIT HT_WIDTH_16_BITS |
| 105 | |
| 106 | // Frequency Limit equates for call backs which take a frequency supported mask. |
| 107 | #define HT_FREQUENCY_LIMIT_200M 1 ///< Specifies a limit of no more than 200 MHz HT frequency. |
| 108 | #define HT_FREQUENCY_LIMIT_400M 7 ///< Specifies a limit of no more than 400 MHz HT frequency. |
| 109 | #define HT_FREQUENCY_LIMIT_600M 0x1F ///< Specifies a limit of no more than 600 MHz HT frequency. |
| 110 | #define HT_FREQUENCY_LIMIT_800M 0x3F ///< Specifies a limit of no more than 800 MHz HT frequency. |
| 111 | #define HT_FREQUENCY_LIMIT_1000M 0x7F ///< Specifies a limit of no more than 1000 MHz HT frequency. |
| 112 | #define HT_FREQUENCY_LIMIT_HT1_ONLY 0x7F ///< Specifies a limit of no more than 1000 MHz HT frequency. |
| 113 | #define HT_FREQUENCY_LIMIT_1200M 0xFF ///< Specifies a limit of no more than 1200 MHz HT frequency. |
| 114 | #define HT_FREQUENCY_LIMIT_1400M 0x1FF ///< Specifies a limit of no more than 1400 MHz HT frequency. |
| 115 | #define HT_FREQUENCY_LIMIT_1600M 0x3FF ///< Specifies a limit of no more than 1600 MHz HT frequency. |
| 116 | #define HT_FREQUENCY_LIMIT_1800M 0x7FF ///< Specifies a limit of no more than 1800 MHz HT frequency. |
| 117 | #define HT_FREQUENCY_LIMIT_2000M 0xFFF ///< Specifies a limit of no more than 2000 MHz HT frequency. |
| 118 | #define HT_FREQUENCY_LIMIT_2200M 0x1FFF ///< Specifies a limit of no more than 2200 MHz HT frequency. |
| 119 | #define HT_FREQUENCY_LIMIT_2400M 0x3FFF ///< Specifies a limit of no more than 2400 MHz HT frequency. |
| 120 | #define HT_FREQUENCY_LIMIT_2600M 0x7FFF ///< Specifies a limit of no more than 2600 MHz HT frequency. |
| 121 | #define HT_FREQUENCY_LIMIT_2800M 0x27FFFul ///< Specifies a limit of no more than 2800 MHz HT frequency. |
| 122 | #define HT_FREQUENCY_LIMIT_3000M 0x67FFFul ///< Specifies a limit of no more than 3000 MHz HT frequency. |
| 123 | #define HT_FREQUENCY_LIMIT_3200M 0xE7FFFul ///< Specifies a limit of no more than 3200 MHz HT frequency. |
| 124 | #define HT_FREQUENCY_LIMIT_3600M 0x1E7FFFul |
| 125 | #define HT_FREQUENCY_LIMIT_MAX HT_FREQUENCY_LIMIT_3600M |
| 126 | #define HT_FREQUENCY_NO_LIMIT 0xFFFFFFFFul ///< Specifies a no limit of HT frequency. |
| 127 | |
| 128 | // Unit ID Clumping special values |
| 129 | #define HT_CLUMPING_DISABLE 0x00000000ul |
| 130 | #define HT_CLUMPING_NO_LIMIT 0xFFFFFFFFul |
| 131 | |
| 132 | #define HT_LIST_TERMINAL 0xFF ///< End of list. |
| 133 | #define HT_LIST_MATCH_ANY 0xFE ///< Match Any value, used for Sockets, Links, IO Chain Depth. |
| 134 | #define HT_LIST_MATCH_INTERNAL_LINK 0xFD ///< Match all of the internal links. |
| 135 | |
| 136 | // Event Notify definitions |
| 137 | |
| 138 | // Event definitions. |
| 139 | |
| 140 | // Coherent subfunction events |
| 141 | #define HT_EVENT_COH_EVENTS 0x10001000ul |
| 142 | #define HT_EVENT_COH_NO_TOPOLOGY 0x10011000ul ///< See ::HT_EVENT_DATA_COH_NO_TOPOLOGY. |
| 143 | #define HT_EVENT_COH_OBSOLETE000 0x10021000ul // No longer used. |
| 144 | #define HT_EVENT_COH_PROCESSOR_TYPE_MIX 0x10031000ul ///< See ::HT_EVENT_DATA_COH_PROCESSOR_TYPE_MIX. |
| 145 | #define HT_EVENT_COH_NODE_DISCOVERED 0x10041000ul ///< See ::HT_EVENT_COH_NODE_DISCOVERED. |
| 146 | #define HT_EVENT_COH_MPCAP_MISMATCH 0x10051000ul ///< See ::HT_EVENT_COH_MPCAP_MISMATCH. |
| 147 | |
| 148 | // Non-coherent subfunction events |
| 149 | #define HT_EVENT_NCOH_EVENTS 0x10002000ul |
| 150 | #define HT_EVENT_NCOH_BUID_EXCEED 0x10012000ul ///< See ::HT_EVENT_DATA_NCOH_BUID_EXCEED |
| 151 | #define HT_EVENT_NCOH_OBSOLETE000 0x10022000ul // No longer used. |
| 152 | #define HT_EVENT_NCOH_BUS_MAX_EXCEED 0x10032000ul ///< See ::HT_EVENT_DATA_NCOH_BUS_MAX_EXCEED. |
| 153 | #define HT_EVENT_NCOH_CFG_MAP_EXCEED 0x10042000ul ///< See ::HT_EVENT_DATA_NCOH_CFG_MAP_EXCEED. |
| 154 | #define HT_EVENT_NCOH_DEVICE_FAILED 0x10052000ul ///< See ::HT_EVENT_DATA_NCOH_DEVICE_FAILED |
| 155 | #define HT_EVENT_NCOH_AUTO_DEPTH 0x10062000ul ///< See ::HT_EVENT_NCOH_AUTO_DEPTH |
| 156 | |
| 157 | // Optimization subfunction events |
| 158 | #define HT_EVENT_OPT_EVENTS 0x10003000ul |
| 159 | #define HT_EVENT_OPT_REQUIRED_CAP_RETRY 0x10013000ul ///< See ::HT_EVENT_DATA_OPT_REQUIRED_CAP. |
| 160 | #define HT_EVENT_OPT_REQUIRED_CAP_GEN3 0x10023000ul ///< See ::HT_EVENT_DATA_OPT_REQUIRED_CAP. |
| 161 | #define HT_EVENT_OPT_UNUSED_LINKS 0x10033000ul ///< See ::HT_EVENT_DATA_OPT_UNUSED_LINKS. |
| 162 | #define HT_EVENT_OPT_LINK_PAIR_EXCEED 0x10043000ul ///< See ::HT_EVENT_DATA_OPT_LINK_PAIR_EXCEED. |
| 163 | |
| 164 | // HW Fault events |
| 165 | #define HT_EVENT_HW_EVENTS 0x10004000ul |
| 166 | #define HT_EVENT_HW_SYNCFLOOD 0x10014000ul ///< See ::HT_EVENT_DATA_HW_SYNCFLOOD. |
| 167 | #define HT_EVENT_HW_HTCRC 0x10024000ul ///< See ::HT_EVENT_DATA_HW_HT_CRC. |
| 168 | |
| 169 | // The Recovery HT component uses 0x10005000 for events. |
| 170 | // For consistency, we avoid that range here. |
| 171 | |
| 172 | #define HT_MAX_NC_BUIDS 32 |
| 173 | //---------------------------------------------------------------------------- |
| 174 | // HT TYPEDEFS, STRUCTURES, ENUMS |
| 175 | // |
| 176 | //---------------------------------------------------------------------------- |
| 177 | |
| 178 | /// Specify the state redundant links are to be left in after match. |
| 179 | /// |
| 180 | /// After matching a link for IGNORE_LINK or SKIP_REGANG, the link may be left alone, |
| 181 | /// or powered off. |
| 182 | |
| 183 | typedef enum { |
| 184 | MATCHED, ///< The link matches the requested customization. |
| 185 | ///< When used with IGNORE_LINK, |
| 186 | ///< this will generally require other software to initialize the link. |
| 187 | ///< When used with SKIP_REGANG, |
| 188 | ///< the two unganged links will be available for distribution. |
| 189 | |
| 190 | POWERED_OFF, ///< Power the link off. Support may vary based on processor model. |
| 191 | ///< Power Off is only supported for coherent links. |
| 192 | ///< Link power off may occur at a warm reset rather than immediately. |
| 193 | ///< When used with SKIP_REGANG, the paired sublink is powered off, not the matching link. |
| 194 | |
| 195 | UNMATCHED, ///< The link should be processed according to normal defaults. |
| 196 | ///< Effectively, the link does not match the requested customization. |
| 197 | ///< This can be used to exclude links from a following match any. |
| 198 | |
| 199 | MaxFinalLinkState ///< Not a final link state, use for limit checking. |
| 200 | } FINAL_LINK_STATE; |
| 201 | |
| 202 | /// Swap a device from its current id to a new one. |
| 203 | |
| 204 | typedef struct { |
| 205 | IN UINT8 FromId; ///< The device responding to FromId, |
| 206 | IN UINT8 ToId; ///< will be moved to ToId. |
| 207 | } BUID_SWAP_ITEM; |
| 208 | |
| 209 | |
| 210 | /// Each Non-coherent chain may have a list of device swaps. After performing the swaps, |
| 211 | /// the final in order list of device ids is provided. (There can be more swaps than devices.) |
| 212 | /// The unused entries in both are filled with 0xFF. |
| 213 | |
| 214 | typedef struct { |
| 215 | IN BUID_SWAP_ITEM Swaps[HT_MAX_NC_BUIDS]; ///< The BUID Swaps to perform |
| 216 | IN UINT8 FinalIds[HT_MAX_NC_BUIDS]; ///< The ordered final BUIDs, resulting from the swaps |
| 217 | } BUID_SWAP_LIST; |
| 218 | |
| 219 | |
| 220 | /// Control Manual Initialization of Non-Coherent Chains |
| 221 | /// |
| 222 | /// This interface is checked every time a non-coherent chain is |
| 223 | /// processed. BUID assignment may be controlled explicitly on a |
| 224 | /// non-coherent chain. Provide a swap list. Swaps controls the |
| 225 | /// BUID assignment and FinalIds provides the device to device |
| 226 | /// Linking. Device orientation can be detected automatically, or |
| 227 | /// explicitly. See interface documentation for more details. |
| 228 | /// |
| 229 | /// If a manual swap list is not supplied, |
| 230 | /// automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially |
| 231 | /// based on each device's unit count. |
| 232 | |
| 233 | typedef struct { |
| 234 | // Match fields |
| 235 | IN UINT8 Socket; ///< The Socket on which this chain is located |
| 236 | IN UINT8 Link; ///< The Link on the host for this chain |
| 237 | // Override fields |
| 238 | IN BUID_SWAP_LIST SwapList; ///< The swap list |
| 239 | } MANUAL_BUID_SWAP_LIST; |
| 240 | |
| 241 | |
| 242 | /// Override options for DEVICE_CAP_OVERRIDE. |
| 243 | /// |
| 244 | /// Specify which override actions should be performed. For Checks, 1 means to check the item |
| 245 | /// and 0 means to skip the check. For the override options, 1 means to apply the override and |
| 246 | /// 0 means to ignore the override. |
| 247 | |
| 248 | typedef struct { |
| 249 | IN UINT32 IsCheckDevVenId:1; ///< Check Match on Device/Vendor id |
| 250 | IN UINT32 IsCheckRevision:1; ///< Check Match on device Revision |
| 251 | IN UINT32 IsOverrideWidthIn:1; ///< Override Width In |
| 252 | IN UINT32 IsOverrideWidthOut:1; ///< Override Width Out |
| 253 | IN UINT32 IsOverrideFreq:1; ///< Override Frequency |
| 254 | IN UINT32 IsOverrideClumping:1; ///< Override Clumping |
| 255 | IN UINT32 IsDoCallout:1; ///< Make the optional callout |
| 256 | } DEVICE_CAP_OVERRIDE_OPTIONS; |
| 257 | |
| 258 | /// Override capabilities of a device. |
| 259 | /// |
| 260 | /// This interface is checked once for every Link on every IO device. |
| 261 | /// Provide the width and frequency capability if needed for this device. |
| 262 | /// This is used along with device capabilities, the limit interfaces, and northbridge |
| 263 | /// limits to compute the default settings. The components of the device's PCI config |
| 264 | /// address are provided, so its settings can be consulted if need be. |
| 265 | /// The optional callout is a catch all. |
| 266 | |
| 267 | typedef struct { |
| 268 | // Match fields |
| 269 | IN UINT8 HostSocket; ///< The Socket on which this chain is located. |
| 270 | IN UINT8 HostLink; ///< The Link on the host for this chain. |
| 271 | IN UINT8 Depth; ///< The Depth in the I/O chain from the Host. |
| 272 | IN UINT32 DevVenId; ///< The Device's PCI Vendor + Device ID (offset 0x00). |
| 273 | IN UINT8 Revision; ///< The Device's PCI Revision field (offset 0x08). |
| 274 | IN UINT8 Link; ///< The Device's Link number (0 or 1). |
| 275 | IN DEVICE_CAP_OVERRIDE_OPTIONS Options; ///< The options for this device override. |
| 276 | // Override fields |
| 277 | IN UINT8 LinkWidthIn; ///< modify to change the Link Width In. |
| 278 | IN UINT8 LinkWidthOut; ///< modify to change the Link Width Out. |
| 279 | IN UINT32 FreqCap; ///< modify to change the Link's frequency capability. |
| 280 | IN UINT32 Clumping; ///< modify to change Unit ID clumping support. |
| 281 | IN CALLOUT_ENTRY Callout; ///< optional call for really complex cases, or NULL. |
| 282 | } DEVICE_CAP_OVERRIDE; |
| 283 | |
| 284 | /// Callout param struct for override capabilities of a device. |
| 285 | /// |
| 286 | /// If the optional callout is implemented this param struct is passed to it. |
| 287 | |
| 288 | typedef struct { |
| 289 | IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header |
| 290 | // Match fields |
| 291 | IN UINT8 HostSocket; ///< The Socket on which this chain is located. |
| 292 | IN UINT8 HostLink; ///< The Link on the host for this chain. |
| 293 | IN UINT8 Depth; ///< The Depth in the I/O chain from the Host. |
| 294 | IN UINT32 DevVenId; ///< The Device's PCI Vendor + Device ID (offset 0x00). |
| 295 | IN UINT8 Revision; ///< The Device's PCI Revision field (offset 0x08). |
| 296 | IN UINT8 Link; ///< The Device's Link number (0 or 1). |
| 297 | IN PCI_ADDR PciAddress; ///< The Device's PCI Address. |
| 298 | // Override fields |
| 299 | OUT UINT8 *LinkWidthIn; ///< modify to change the Link Width In. |
| 300 | OUT UINT8 *LinkWidthOut; ///< modify to change the Link Width Out. |
| 301 | OUT UINT32 *FreqCap; ///< modify to change the Link's frequency capability. |
| 302 | OUT UINT32 *Clumping; ///< modify to change Unit ID clumping support. |
| 303 | } DEVICE_CAP_CALLOUT_PARAMS; |
| 304 | |
| 305 | /// Limits for CPU to CPU Links. |
| 306 | /// |
| 307 | /// For each coherent connection this interface is checked once. |
| 308 | /// Provide the frequency and width if needed for this Link (usually based on board |
| 309 | /// restriction). This is used with CPU device capabilities and northbridge limits |
| 310 | /// to compute the default settings. |
| 311 | |
| 312 | typedef struct { |
| 313 | // Match fields |
| 314 | IN UINT8 SocketA; ///< One Socket on which this Link is located |
| 315 | IN UINT8 LinkA; ///< The Link on this Node |
| 316 | IN UINT8 SocketB; ///< The other Socket on which this Link is located |
| 317 | IN UINT8 LinkB; ///< The Link on that Node |
| 318 | // Limit fields |
| 319 | IN UINT8 ABLinkWidthLimit; ///< modify to change the Link Width A->B |
| 320 | IN UINT8 BALinkWidthLimit; ///< modify to change the Link Width B-<A |
| 321 | IN UINT32 PcbFreqCap; ///< modify to change the Link's frequency capability |
| 322 | } CPU_TO_CPU_PCB_LIMITS; |
| 323 | |
| 324 | /// Get limits for non-coherent Links. |
| 325 | /// |
| 326 | /// For each non-coherent connection this interface is checked once. |
| 327 | /// Provide the frequency and width if needed for this Link (usually based on board |
| 328 | /// restriction). This is used with device capabilities, device overrides, and northbridge limits |
| 329 | /// to compute the default settings. |
| 330 | /// |
| 331 | typedef struct { |
| 332 | // Match fields |
| 333 | IN UINT8 HostSocket; ///< The Socket on which this Link is located |
| 334 | IN UINT8 HostLink; ///< The Link about to be initialized |
| 335 | IN UINT8 Depth; ///< The Depth in the I/O chain from the Host |
| 336 | // Limit fields |
| 337 | IN UINT8 DownstreamLinkWidthLimit; ///< modify to change the Link Width going away from processor |
| 338 | IN UINT8 UpstreamLinkWidthLimit; ///< modify to change the Link Width moving toward processor |
| 339 | IN UINT32 PcbFreqCap; ///< modify to change the Link's frequency capability |
| 340 | } IO_PCB_LIMITS; |
| 341 | |
| 342 | /// Manually control bus number assignment. |
| 343 | /// |
| 344 | /// This interface is checked every time a non-coherent chain is processed. |
| 345 | /// If a system can not use the auto Bus numbering feature for non-coherent chain bus |
| 346 | /// assignments, this interface can provide explicit control. For each chain, provide |
| 347 | /// the bus number range to use. |
| 348 | |
| 349 | typedef struct { |
| 350 | // Match fields |
| 351 | IN UINT8 Socket; ///< The Socket on which this chain is located |
| 352 | IN UINT8 Link; ///< The Link on the host for this chain |
| 353 | // Override fields |
| 354 | IN UINT8 SecBus; ///< Secondary Bus number for this non-coherent chain |
| 355 | IN UINT8 SubBus; ///< Subordinate Bus number |
| 356 | } OVERRIDE_BUS_NUMBERS; |
| 357 | |
| 358 | |
| 359 | /// Ignore a Link. |
| 360 | /// |
| 361 | /// This interface is checked every time a coherent Link is found and then every |
| 362 | /// time a non-coherent Link from a CPU is found. |
| 363 | /// Any coherent or non-coherent Link from a CPU can be ignored and not used |
| 364 | /// for discovery or initialization. Useful for connection based systems. |
| 365 | /// (Note: not checked for IO device to IO Device Links.) |
| 366 | /// (Note: not usable for internal links (MCM processors).) |
| 367 | |
| 368 | typedef struct { |
| 369 | // Match fields |
| 370 | IN UINT8 Socket; ///< The Socket on which this Link is located |
| 371 | IN UINT8 Link; ///< The Link about to be initialized |
| 372 | // Customization fields |
| 373 | IN FINAL_LINK_STATE LinkState; ///< The link may be left unitialized, or powered off. |
| 374 | } IGNORE_LINK; |
| 375 | |
| 376 | |
| 377 | /// Skip reganging of subLinks. |
| 378 | /// |
| 379 | /// This interface is checked whenever two subLinks are both connected to the same CPUs. |
| 380 | /// Normally, unganged sublinks between the same two CPUs are reganged. |
| 381 | /// Provide a matching structure to leave the Links unganged. |
| 382 | |
| 383 | typedef struct { |
| 384 | // Match fields |
| 385 | IN UINT8 SocketA; ///< One Socket on which this Link is located |
| 386 | IN UINT8 LinkA; ///< The Link on this Node |
| 387 | IN UINT8 SocketB; ///< The other Socket on which this Link is located |
| 388 | IN UINT8 LinkB; ///< The Link on that Node |
| 389 | // Customization fields |
| 390 | IN FINAL_LINK_STATE LinkState; ///< The paired sublink may be active, or powered off. |
| 391 | } SKIP_REGANG; |
| 392 | |
| 393 | /// The System Socket layout, which sockets are physically connected. |
| 394 | /// |
| 395 | /// The hardware method for Socket naming is preferred. Use this software method only |
| 396 | /// if required. |
| 397 | |
| 398 | typedef struct { |
| 399 | IN UINT8 CurrentSocket; ///< The socket from which this connection originates. |
| 400 | IN UINT8 CurrentLink; ///< The Link from the source socket connects to another socket. |
| 401 | IN UINT8 TargetSocket; ///< The target socket which is connected on that link. |
| 402 | } SYSTEM_PHYSICAL_SOCKET_MAP; |
| 403 | |
| 404 | //---------------------------------------------------------------------------- |
| 405 | /// |
| 406 | /// This is the input structure for AmdHtInitialize. |
| 407 | /// |
| 408 | typedef struct { |
| 409 | // Basic level customization |
| 410 | IN UINT8 AutoBusStart; ///< For automatic bus number assignment, starting bus number - usually zero. |
| 411 | ///< @BldCfgItem{BLDCFG_STARTING_BUSNUM} |
| 412 | IN UINT8 AutoBusMax; ///< For automatic bus number assignment, do not assign above max. |
| 413 | ///< @BldCfgItem{BLDCFG_MAXIMUM_BUSNUM} |
| 414 | IN UINT8 AutoBusIncrement; ///< For automatic bus number assignment, each chain gets this many busses. |
| 415 | ///< @BldCfgItem{BLDCFG_ALLOCATED_BUSNUM} |
| 416 | |
| 417 | // Advanced Level Customization |
| 418 | IN MANUAL_BUID_SWAP_LIST *ManualBuidSwapList; ///< Provide Manual Swap List, if any. |
| 419 | ///< @BldCfgItem{BLDCFG_BUID_SWAP_LIST} |
| 420 | IN DEVICE_CAP_OVERRIDE *DeviceCapOverrideList; ///< Provide Device Overrides, if any. |
| 421 | ///< @BldCfgItem{BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST} |
| 422 | IN CPU_TO_CPU_PCB_LIMITS *CpuToCpuPcbLimitsList; ///< Provide CPU PCB Limits, if any. |
| 423 | ///< @BldCfgItem{BLDCFG_HTFABRIC_LIMITS_LIST}. |
| 424 | ///< @n @e Examples: See @ref FrequencyLimitExamples "Frequency Limit Examples". |
| 425 | IN IO_PCB_LIMITS *IoPcbLimitsList; ///< Provide IO PCB Limits, if any. |
| 426 | ///< @BldCfgItem{BLDCFG_HTCHAIN_LIMITS_LIST}. |
| 427 | ///< @n @e Examples: See @ref FrequencyLimitExamples "Frequency Limit Examples". |
| 428 | IN OVERRIDE_BUS_NUMBERS *OverrideBusNumbersList; ///< Provide manual Bus Number assignment, if any. |
| 429 | ///< Use either auto bus numbering or override bus |
| 430 | ///< numbers, not both. |
| 431 | ///< @BldCfgItem{BLDCFG_BUS_NUMBERS_LIST} |
| 432 | |
| 433 | IN IGNORE_LINK *IgnoreLinkList; ///< Provide links to ignore, if any. |
| 434 | ///< @BldCfgItem{BLDCFG_IGNORE_LINK_LIST} |
| 435 | IN SKIP_REGANG *SkipRegangList; ///< Provide links to remain unganged, if any. |
| 436 | ///< @BldCfgItem{BLDCFG_LINK_SKIP_REGANG_LIST} |
| 437 | ///< @n @e Examples: See @ref PerfPerWattHt "Performance-per-watt Optimization". |
| 438 | |
| 439 | // Expert Level Customization |
| 440 | IN UINT8 **Topolist; ///< Use this topology list in addition to the built in, if not NULL. |
| 441 | ///< @BldCfgItem{BLDCFG_ADDITIONAL_TOPOLOGIES_LIST} |
| 442 | IN SYSTEM_PHYSICAL_SOCKET_MAP *SystemPhysicalSocketMap; |
| 443 | ///< The hardware socket naming method is preferred, |
| 444 | ///< If it can't be used, this provides a software method. |
| 445 | ///< @BldCfgItem{BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP} |
| 446 | } AMD_HT_INTERFACE; |
| 447 | |
| 448 | //----------------------------------------------------------------------------- |
| 449 | // |
| 450 | // HT Recovery Interface |
| 451 | // |
| 452 | |
| 453 | |
| 454 | /*----------------------------------------------------------------------------- |
| 455 | * HT Recovery DEFINITIONS AND MACROS |
| 456 | * |
| 457 | *----------------------------------------------------------------------------- |
| 458 | */ |
| 459 | |
| 460 | // BBHT subfunction events |
| 461 | #define HT_EVENT_BB_EVENTS 0x10005000ul |
| 462 | #define HT_EVENT_BB_BUID_EXCEED 0x10015000ul |
| 463 | #define HT_EVENT_BB_DEVICE_FAILED 0x10055000ul |
| 464 | #define HT_EVENT_BB_AUTO_DEPTH 0x10065000ul |
| 465 | |
| 466 | /*---------------------------------------------------------------------------- |
| 467 | * HT Recovery TYPEDEFS, STRUCTURES, ENUMS |
| 468 | * |
| 469 | *---------------------------------------------------------------------------- |
| 470 | */ |
| 471 | |
| 472 | |
| 473 | /// The Interface structure to Recovery HT. |
| 474 | |
| 475 | typedef struct { |
| 476 | IN MANUAL_BUID_SWAP_LIST *ManualBuidSwapList; ///< Option to manually control SB link init |
| 477 | ///< @BldCfgItem{BLDCFG_BUID_SWAP_LIST} |
| 478 | OUT UINT32 Depth; ///< If auto init was used this is set to the depth of the chain, |
| 479 | ///< else, for manual init unmodified. |
| 480 | } AMD_HT_RESET_INTERFACE; |
| 481 | |
| 482 | |
| 483 | //----------------------------------------------------------------------------- |
| 484 | // FCH DEFINITIONS AND MACROS |
| 485 | // |
| 486 | //----------------------------------------------------------------------------- |
| 487 | |
| 488 | /// Configuration values for SdConfig |
| 489 | typedef enum { |
| 490 | SdDisable = 0, ///< Disabled |
| 491 | SdAmda, ///< AMDA, set 24,18,16, default |
| 492 | SdDma, ///< DMA clear 24, 16, set 18 |
| 493 | SdPio ///< PIO clear 24,18,16 |
| 494 | } SD_MODE; |
| 495 | |
| 496 | /// Configuration values for SdClockControl |
| 497 | typedef enum { |
| 498 | Sd50MhzTraceCableLengthWithinSixInches = 4, ///< 50Mhz, default |
| 499 | Sd40MhzTraceCableLengthSix2ElevenInches = 6, ///< 40Mhz |
| 500 | Sd25MhzTraceCableLengthEleven2TwentyfourInches = 7, ///< 25Mhz |
| 501 | } SD_CLOCK_CONTROL; |
| 502 | |
| 503 | /// Configuration values for AzaliaController |
| 504 | typedef enum { |
zbao | 7598bea | 2012-08-09 15:08:20 +0800 | [diff] [blame] | 505 | AzAuto = 0, ///< Auto - Detect Azalia controller automatically |
| 506 | AzDisable, ///< Diable - Disable Azalia controller |
| 507 | AzEnable ///< Enable - Enable Azalia controller |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 508 | } HDA_CONFIG; |
| 509 | |
| 510 | /// Configuration values for IrConfig |
| 511 | typedef enum { |
| 512 | IrDisable = 0, ///< Disable |
| 513 | IrRxTx0 = 1, ///< Rx and Tx0 |
| 514 | IrRxTx1 = 2, ///< Rx and Tx1 |
| 515 | IrRxTx0Tx1 = 3 ///< Rx and both Tx0,Tx1 |
| 516 | } IR_CONFIG; |
| 517 | |
| 518 | /// Configuration values for SataClass |
| 519 | typedef enum { |
| 520 | SataNativeIde = 0, ///< Native IDE mode |
| 521 | SataRaid, ///< RAID mode |
| 522 | SataAhci, ///< AHCI mode |
| 523 | SataLegacyIde, ///< Legacy IDE mode |
| 524 | SataIde2Ahci, ///< IDE->AHCI mode |
| 525 | SataAhci7804, ///< AHCI mode as 7804 ID (AMD driver) |
| 526 | SataIde2Ahci7804 ///< IDE->AHCI mode as 7804 ID (AMD driver) |
| 527 | } SATA_CLASS; |
| 528 | |
| 529 | /// Configuration values for BLDCFG_FCH_GPP_LINK_CONFIG |
| 530 | typedef enum { |
| 531 | PortA4 = 0, ///< 4:0:0:0 |
| 532 | PortA2B2 = 2, ///< 2:2:0:0 |
| 533 | PortA2B1C1 = 3, ///< 2:1:1:0 |
| 534 | PortA1B1C1D1 = 4 ///< 1:1:1:1 |
| 535 | } GPP_LINKMODE; |
| 536 | |
| 537 | /// Configuration values for FchPowerFail |
| 538 | typedef enum { |
| 539 | AlwaysOff = 0, ///< Always power off after power resumes |
| 540 | AlwaysOn = 1, ///< Always power on after power resumes |
| 541 | UsePrevious = 3, ///< Resume to same setting when power fails |
| 542 | } POWER_FAIL; |
| 543 | |
| 544 | |
| 545 | /// Configuration values for SATA Link Speed |
| 546 | typedef enum { |
| 547 | Gen1 = 1, ///< SATA port GEN1 speed |
| 548 | Gen2 = 2, ///< SATA port GEN2 speed |
| 549 | Gen3 = 3, ///< SATA port GEN3 speed |
| 550 | } SATA_SPEED; |
| 551 | |
| 552 | |
| 553 | /// Configuration values for GPIO function |
| 554 | typedef enum { |
| 555 | Function0 = 0, ///< GPIO Function 1 |
| 556 | Function1 = 1, ///< GPIO Function 1 |
| 557 | Function2 = 2, ///< GPIO Function 2 |
| 558 | Function3 = 3, ///< GPIO Function 3 |
| 559 | } GPIO_FUN; |
| 560 | |
| 561 | |
| 562 | /// Configuration values for GPIO_CFG |
| 563 | typedef enum { |
| 564 | OwnedByEc = 1 << 0, ///< This bit can only be written by EC |
| 565 | OwnedByHost = 1 << 1, ///< This bit can only be written by host (BIOS) |
| 566 | Sticky = 1 << 2, ///< If set, [6:3] are sticky |
| 567 | PullUpB = 1 << 3, ///< 0: Pullup enable; 1: Pullup disabled |
| 568 | PullDown = 1 << 4, ///< 0: Pulldown disabled; 1: Pulldown enable |
| 569 | GpioOutEnB = 1 << 5, ///< 0: Output enable; 1: Output disable |
| 570 | GpioOut = 1 << 6, ///< Output state when GpioOutEnB is 0 |
| 571 | GpioIn = 1 << 7, ///< This bit is read only - current pin state |
| 572 | } CFG_BYTE; |
| 573 | |
| 574 | /// FCH GPIO CONTROL |
| 575 | typedef struct { |
| 576 | IN UINT8 GpioPin; ///< Gpio Pin, valid range: 0-67, 128-150, 160-228 |
| 577 | IN GPIO_FUN PinFunction; ///< Multi-function selection |
| 578 | IN CFG_BYTE CfgByte; ///< GPIO Register value |
| 579 | } GPIO_CONTROL; |
| 580 | |
| 581 | /// |
| 582 | /// FCH SCI MAP CONTROL |
| 583 | /// |
| 584 | typedef struct { |
| 585 | IN UINT8 InputPin; ///< Input Pin, valid range 0-63 |
| 586 | IN UINT8 GpeMap; ///< Gpe Map, valid range 0-31 |
| 587 | } SCI_MAP_CONTROL; |
| 588 | |
| 589 | /// |
| 590 | /// FCH SATA PHY CONTROL |
| 591 | /// |
| 592 | typedef struct { |
| 593 | IN BOOLEAN CommonPhy; ///< Common PHY or not |
| 594 | ///< @li <b>FALSE</b> - Only applied to specified port |
| 595 | ///< @li <b>TRUE</b> - Apply to all SATA ports |
| 596 | IN SATA_SPEED Gen; ///< SATA speed |
| 597 | IN UINT8 Port; ///< Port number, valid range: 0-7 |
| 598 | IN UINT32 PhyData; ///< SATA PHY data, valid range: 0-0xFFFFFFFF |
| 599 | } SATA_PHY_CONTROL; |
| 600 | |
| 601 | /// |
| 602 | /// FCH Component Data Structure in InitReset stage |
| 603 | /// |
| 604 | typedef struct { |
| 605 | IN BOOLEAN UmiGen2; ///< Enable Gen2 data rate of UMI |
| 606 | ///< @li <b>FALSE</b> - Disable Gen2 |
| 607 | ///< @li <b>TRUE</b> - Enable Gen2 |
| 608 | |
| 609 | IN BOOLEAN SataEnable; ///< SATA controller function |
| 610 | ///< @li <b>FALSE</b> - SATA controller is disabled |
| 611 | ///< @li <b>TRUE</b> - SATA controller is enabled |
| 612 | |
| 613 | IN BOOLEAN IdeEnable; ///< SATA IDE controller mode enabled/disabled |
| 614 | ///< @li <b>FALSE</b> - IDE controller is disabled |
| 615 | ///< @li <b>TRUE</b> - IDE controller is enabled |
| 616 | |
| 617 | IN BOOLEAN GppEnable; ///< Master switch of GPP function |
| 618 | ///< @li <b>FALSE</b> - GPP disabled |
| 619 | ///< @li <b>TRUE</b> - GPP enabled |
| 620 | |
| 621 | IN BOOLEAN Xhci0Enable; ///< XHCI0 controller function |
| 622 | ///< @li <b>FALSE</b> - XHCI0 controller disabled |
| 623 | ///< @li <b>TRUE</b> - XHCI0 controller enabled |
| 624 | |
| 625 | IN BOOLEAN Xhci1Enable; ///< XHCI1 controller function |
| 626 | ///< @li <b>FALSE</b> - XHCI1 controller disabled |
| 627 | ///< @li <b>TRUE</b> - XHCI1 controller enabled |
| 628 | } FCH_RESET_INTERFACE; |
| 629 | |
| 630 | |
| 631 | /// |
| 632 | /// FCH Component Data Structure from InitEnv stage |
| 633 | /// |
| 634 | typedef struct { |
| 635 | IN SD_MODE SdConfig; ///< Secure Digital (SD) controller mode |
| 636 | IN HDA_CONFIG AzaliaController; ///< Azalia HD Audio Controller |
| 637 | |
| 638 | IN IR_CONFIG IrConfig; ///< Infrared (IR) Configuration |
| 639 | IN BOOLEAN UmiGen2; ///< Enable Gen2 data rate of UMI |
| 640 | ///< @li <b>FALSE</b> - Disable Gen2 |
| 641 | ///< @li <b>TRUE</b> - Enable Gen2 |
| 642 | |
| 643 | IN SATA_CLASS SataClass; ///< SATA controller mode |
| 644 | IN BOOLEAN SataEnable; ///< SATA controller function |
| 645 | ///< @li <b>FALSE</b> - SATA controller is disabled |
| 646 | ///< @li <b>TRUE</b> - SATA controller is enabled |
| 647 | |
| 648 | IN BOOLEAN IdeEnable; ///< SATA IDE controller mode enabled/disabled |
| 649 | ///< @li <b>FALSE</b> - IDE controller is disabled |
| 650 | ///< @li <b>TRUE</b> - IDE controller is enabled |
| 651 | |
| 652 | IN BOOLEAN SataIdeMode; ///< Native mode of SATA IDE controller |
| 653 | ///< @li <b>FALSE</b> - Legacy IDE mode |
| 654 | ///< @li <b>TRUE</b> - Native IDE mode |
| 655 | |
| 656 | IN BOOLEAN Ohci1Enable; ///< OHCI controller #1 Function |
| 657 | ///< @li <b>FALSE</b> - OHCI1 is disabled |
| 658 | ///< @li <b>TRUE</b> - OHCI1 is enabled |
| 659 | |
| 660 | IN BOOLEAN Ohci2Enable; ///< OHCI controller #2 Function |
| 661 | ///< @li <b>FALSE</b> - OHCI2 is disabled |
| 662 | ///< @li <b>TRUE</b> - OHCI2 is enabled |
| 663 | |
| 664 | IN BOOLEAN Ohci3Enable; ///< OHCI controller #3 Function |
| 665 | ///< @li <b>FALSE</b> - OHCI3 is disabled |
| 666 | ///< @li <b>TRUE</b> - OHCI3 is enabled |
| 667 | |
| 668 | IN BOOLEAN Ohci4Enable; ///< OHCI controller #4 Function |
| 669 | ///< @li <b>FALSE</b> - OHCI4 is disabled |
| 670 | ///< @li <b>TRUE</b> - OHCI4 is enabled |
| 671 | |
| 672 | IN BOOLEAN XhciSwitch; ///< XHCI controller Function |
| 673 | ///< @li <b>FALSE</b> - XHCI is disabled |
| 674 | ///< @li <b>TRUE</b> - XHCI is enabled |
| 675 | |
| 676 | IN BOOLEAN GppEnable; ///< Master switch of GPP function |
| 677 | ///< @li <b>FALSE</b> - GPP disabled |
| 678 | ///< @li <b>TRUE</b> - GPP enabled |
| 679 | |
| 680 | IN POWER_FAIL FchPowerFail; ///< FCH power failure option |
| 681 | } FCH_INTERFACE; |
| 682 | |
| 683 | |
| 684 | /*---------------------------------------------------------------------------- |
| 685 | * CPU Feature related info |
| 686 | *---------------------------------------------------------------------------- |
| 687 | */ |
| 688 | |
| 689 | /// Build Configuration values for BLDCFG_PLATFORM_C1E_MODE |
| 690 | typedef enum { |
| 691 | C1eModeDisabled = 0, ///< Disabled |
| 692 | C1eModeAuto = 1, ///< Auto mode enables the best C1e method for the |
| 693 | ///< currently installed processor |
| 694 | C1eModeHardware = 2, ///< Hardware method |
| 695 | C1eModeMsgBased = 3, ///< Message-based method |
| 696 | C1eModeSoftwareDeprecated = 4, ///< Deprecated software SMI method. |
| 697 | ///< Refer to "Addendum\Examples\C1eSMMHandler.asm" for |
| 698 | ///< example host BIOS SMM Handler implementation |
| 699 | C1eModeHardwareSoftwareDeprecated = 5, ///< Hardware or deprecated software SMI method |
| 700 | MaxC1eMode = 6 ///< Not a valid value, used for verifying input |
| 701 | } PLATFORM_C1E_MODES; |
| 702 | |
| 703 | /// Build Configuration values for BLDCFG_PLATFORM_CSTATE_MODE |
| 704 | typedef enum { |
| 705 | CStateModeDisabled = 0, ///< Disabled |
| 706 | CStateModeC6 = 1, ///< C6 State |
| 707 | MaxCStateMode = 2 ///< Not a valid value, used for verifying input |
| 708 | } PLATFORM_CSTATE_MODES; |
| 709 | |
| 710 | /// Build Configuration values for BLDCFG_PLATFORM_CPB_MODE |
| 711 | typedef enum { |
| 712 | CpbModeAuto = 0, ///< Auto |
| 713 | CpbModeDisabled = 1, ///< Disabled |
| 714 | MaxCpbMode = 2 ///< Not a valid value, used for verifying input |
| 715 | } PLATFORM_CPB_MODES; |
| 716 | |
| 717 | /// Build Configuration values for BLDCFG_LOW_POWER_PSTATE_FOR_PROCHOT_MODE |
| 718 | typedef enum { |
| 719 | LOW_POWER_PSTATE_FOR_PROCHOT_AUTO = 0, ///< Auto |
| 720 | LOW_POWER_PSTATE_FOR_PROCHOT_DISABLE = 1, ///< Disabled |
| 721 | MAX_LOW_POWER_PSTATE_FOR_PROCHOT_MODE = 2 ///< Not a valid value, used for verifying input |
| 722 | } PLATFORM_LOW_POWER_PSTATE_MODES; |
| 723 | |
| 724 | /*---------------------------------------------------------------------------- |
| 725 | * GNB PCIe configuration info |
| 726 | *---------------------------------------------------------------------------- |
| 727 | */ |
| 728 | |
| 729 | // Event definitions |
| 730 | |
| 731 | #define GNB_EVENT_INVALID_CONFIGURATION 0x20010000ul // User configuration invalid |
| 732 | #define GNB_EVENT_INVALID_PCIE_TOPOLOGY_CONFIGURATION 0x20010001ul // Requested lane allocation for PCIe port can not be supported |
| 733 | #define GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION 0x20010002ul // Requested incorrect PCIe port device address |
| 734 | #define GNB_EVENT_INVALID_DDI_LINK_CONFIGURATION 0x20010003ul // Incorrect parameter in DDI link configuration |
| 735 | #define GNB_EVENT_INVALID_LINK_WIDTH_CONFIGURATION 0x20010004ul // Invalid with for PCIe port or DDI link |
| 736 | #define GNB_EVENT_INVALID_LANES_CONFIGURATION 0x20010005ul // Lane double subscribe lanes |
| 737 | #define GNB_EVENT_INVALID_DDI_TOPOLOGY_CONFIGURATION 0x20010006ul // Requested lane allocation for DDI link(s) can not be supported |
| 738 | #define GNB_EVENT_LINK_TRAINING_FAIL 0x20020000ul // PCIe Link training fail |
| 739 | #define GNB_EVENT_BROKEN_LANE_RECOVERY 0x20030000ul // Broken lane workaround applied to recover link training |
| 740 | #define GNB_EVENT_GEN2_SUPPORT_RECOVERY 0x20040000ul // Scale back to GEN1 to recover link training |
| 741 | |
| 742 | |
| 743 | #define DESCRIPTOR_TERMINATE_LIST 0x80000000ull |
| 744 | #define DESCRIPTOR_IGNORE 0x40000000ull |
| 745 | |
| 746 | /// PCIe link initialization |
| 747 | typedef enum { |
| 748 | EndpointDetect = 0, ///< Detect endpoint presence |
| 749 | EndpointNotPresent ///< Endpoint not present (or connected). Used in case there is alternative way to determine |
| 750 | ///< if device present on board or in slot. For example GPIO can be used to determine device presence. |
| 751 | } PCIE_ENDPOINT_STATUS; |
| 752 | |
| 753 | |
| 754 | /// PCIe port misc extended controls |
| 755 | typedef struct { |
| 756 | IN UINT8 LinkComplianceMode :1; ///< Force port into compliance mode (device will not be trained, port output compliance pattern) |
| 757 | IN UINT8 LinkSafeMode :2; /**< Safe mode PCIe capability. (Parameter may limit PCIe speed requested through PCIe_PORT_DATA::LinkSpeedCapability) |
| 758 | * @li @b 0 - port can advertize muximum supported capability |
| 759 | * @li @b 1 - port limit advertized capability and speed to PCIe Gen1 |
| 760 | */ |
| 761 | IN UINT8 SbLink :1; /**< PCIe link type |
| 762 | * @li @b 0 - General purpose port |
| 763 | * @li @b 1 - Port connected to SB |
| 764 | */ |
| 765 | IN UINT8 ClkPmSupport :1; /**< Clock Power Management Support |
| 766 | * @li @b 0 - Clock Power Management not configured |
| 767 | * @li @b 1 - Clock Power Management configured according to PCIe device capability |
| 768 | */ |
| 769 | } PCIe_PORT_MISC_CONTROL; |
| 770 | |
| 771 | /// The IO APIC Interrupt Mapping Info |
| 772 | typedef struct { |
| 773 | IN UINT8 GroupMap; /**< Group mapping for slot or endpoint device (connected to PCIE port) interrupts . |
| 774 | * @li <b>0</b> - IGNORE THIS STRUCTURE AND USE RECOMMENDED SETTINGS |
| 775 | * @li <b>1</b> - mapped to Grp 0 (Interrupts 0..3 of IO APIC redirection table) |
| 776 | * @li <b>2</b> - mapped to Grp 1 (Interrupts 4..7 of IO APIC redirection table) |
| 777 | * @li ... |
| 778 | * @li <b>8</b> - mapped to Grp 7 (Interrupts 28..31 of IO APIC redirection table) |
| 779 | */ |
| 780 | IN UINT8 Swizzle; /**< Swizzle interrupt in the Group. |
| 781 | * @li <b>0</b> - ABCD |
| 782 | * @li <b>1</b> - BCDA |
| 783 | * @li <b>2</b> - CDAB |
| 784 | * @li <b>3</b> - DABC |
| 785 | */ |
| 786 | IN UINT8 BridgeInt; /**< IOAPIC redirection table entry for PCIE bridge interrupt |
| 787 | * @li <b>0</b> - Entry 0 of IO APIC redirection table |
| 788 | * @li <b>1</b> - Entry 1 of IO APIC redirection table |
| 789 | * @li ... |
| 790 | * @li <b>31</b> - Entry 31 of IO APIC redirection table |
| 791 | */ |
| 792 | } APIC_DEVICE_INFO; |
| 793 | |
| 794 | /// PCIe port configuration data |
| 795 | typedef struct { |
| 796 | IN UINT8 PortPresent; ///< Enable PCIe port for initialization. |
| 797 | IN UINT8 ChannelType; /**< Channel type. |
| 798 | * @li @b 0 - "lowLoss", |
| 799 | * @li @b 1 - "highLoss", |
| 800 | * @li @b 2 - "mob0db", |
| 801 | * @li @b 3 - "mob3db", |
| 802 | * @li @b 4 - "extnd6db" |
| 803 | * @li @b 5 - "extnd8db" |
| 804 | */ |
| 805 | IN UINT8 DeviceNumber; /**< PCI Device number for port. |
| 806 | * @li @b 0 - Native port device number |
| 807 | * @li @b N - Port device number (See available configurations @ref F12LaneConfigurations "Family 0x12", @ref F14ONLaneConfigurations "Family 0x14(ON)") |
| 808 | */ |
| 809 | IN UINT8 FunctionNumber; ///< Reserved for future use |
| 810 | IN UINT8 LinkSpeedCapability; /**< PCIe link speed/ |
| 811 | * @li @b 0 - Maximum supported by silicon |
| 812 | * @li @b 1 - Gen1 |
| 813 | * @li @b 2 - Gen2 |
| 814 | * @li @b 3 - Gen3 |
| 815 | */ |
| 816 | IN UINT8 LinkAspm; /**< ASPM control. (see AgesaPcieLinkAspm for additional option to control ASPM) |
| 817 | * @li @b 0 - Disabled |
| 818 | * @li @b 1 - L0s only |
| 819 | * @li @b 2 - L1 only |
| 820 | * @li @b 3 - L0s and L1 |
| 821 | */ |
| 822 | IN UINT8 LinkHotplug; /**< Hotplug control. |
| 823 | * @li @b 0 - Disabled |
| 824 | * @li @b 1 - Basic |
| 825 | * @li @b 2 - Server |
| 826 | * @li @b 3 - Enhanced |
| 827 | */ |
| 828 | IN UINT8 ResetId; /**< Arbitrary number greater than 0 assigned by platform firmware for GPIO |
| 829 | * identification which control reset for given port. |
| 830 | * Each port with unique GPIO should have unique ResetId assigned. |
| 831 | * All ports use same GPIO to control reset should have same ResetId assigned. |
| 832 | * see AgesaPcieSlotResetContol. |
| 833 | */ |
| 834 | IN PCIe_PORT_MISC_CONTROL MiscControls; ///< Misc extended controls |
| 835 | IN APIC_DEVICE_INFO ApicDeviceInfo; ///< IOAPIC device programming info |
| 836 | IN PCIE_ENDPOINT_STATUS EndpointStatus; ///< PCIe endpoint (device connected to PCIe port) status |
| 837 | } PCIe_PORT_DATA; |
| 838 | |
| 839 | /// DDI channel lane mapping |
| 840 | typedef struct { ///< Structure that discribe lane mapping |
| 841 | IN UINT8 Lane0 :2; /**< Lane 0 mapping |
| 842 | * @li @b 0 - Map to lane 0 |
| 843 | * @li @b 1 - Map to lane 1 |
| 844 | * @li @b 2 - Map to lane 2 |
| 845 | * @li @b 2 - Map to lane 3 |
| 846 | */ |
| 847 | IN UINT8 Lane1 :2; ///< Lane 1 mapping (see "Lane 0 mapping") |
| 848 | IN UINT8 Lane2 :2; ///< Lane 2 mapping (see "Lane 0 mapping") |
| 849 | IN UINT8 Lane3 :2; ///< Lane 3 mapping (see "Lane 0 mapping") |
| 850 | } CHANNEL_MAPPING; ///< Lane mapping |
| 851 | |
| 852 | /// Common Channel Mapping |
| 853 | typedef union { |
| 854 | IN UINT8 ChannelMappingValue; ///< Raw lane mapping |
| 855 | IN CHANNEL_MAPPING ChannelMapping; ///< Channel mapping |
| 856 | } CONN_CHANNEL_MAPPING; |
| 857 | |
| 858 | /// DDI Configuration data |
| 859 | typedef struct { |
| 860 | IN UINT8 ConnectorType; /**< Display Connector Type |
| 861 | * @li @b 0 - DP |
| 862 | * @li @b 1 - eDP |
| 863 | * @li @b 2 - Single Link DVI-D |
| 864 | * @li @b 3 - Dual Link DVI-D (see @ref F12DualLinkDviDescription "Family 0x12 Dual Link DVI connector description") |
| 865 | * @li @b 4 - HDMI |
| 866 | * @li @b 5 - Travis DP-to-VGA |
| 867 | * @li @b 6 - Travis DP-to-LVDS |
| 868 | * @li @b 7 - Hudson-2 NutMeg DP-to-VGA |
| 869 | * @li @b 8 - Single Link DVI-I |
| 870 | * @li @b 9 - Native CRT (Family 0x14) |
| 871 | * @li @b 10 - Native LVDS (Family 0x14) |
| 872 | * @li @b 11 - Auto detect LCD panel connector type. VBIOS is able to auto detect the LVDS connector type: native LVDS, eDP or Travis-LVDS |
| 873 | * The auto detection method only support panel with EDID. |
| 874 | */ |
| 875 | IN UINT8 AuxIndex; /**< Indicates which AUX or DDC Line is used |
| 876 | * @li @b 0 - AUX1 |
| 877 | * @li @b 1 - AUX2 |
| 878 | * @li @b 2 - AUX3 |
| 879 | * @li @b 3 - AUX4 |
| 880 | * @li @b 4 - AUX5 |
| 881 | * @li @b 5 - AUX6 |
| 882 | */ |
| 883 | IN UINT8 HdpIndex; /**< Indicates which HDP pin is used |
| 884 | * @li @b 0 - HDP1 |
| 885 | * @li @b 1 - HDP2 |
| 886 | * @li @b 2 - HDP3 |
| 887 | * @li @b 3 - HDP4 |
| 888 | * @li @b 4 - HDP5 |
| 889 | * @li @b 5 - HDP6 |
| 890 | */ |
| 891 | IN CONN_CHANNEL_MAPPING Mapping[2]; /**< Set specific mapping of lanes to connector pins |
| 892 | * @li Mapping[0] define mapping for group of 4 lanes starting at PCIe_ENGINE_DATA.StartLane |
| 893 | * @li Mapping[1] define mapping for group of 4 lanes ending at PCIe_ENGINE_DATA.EndLane (only applicable for Dual DDI link) |
| 894 | * if Mapping[x] set to 0 than default mapping assumed |
| 895 | */ |
| 896 | IN UINT8 LanePnInversionMask; /**< Specifies whether to invert the state of P and N for each lane. Each bit represents a PCIe lane on the DDI port. |
| 897 | * @li 0 - Do not invert (default) |
| 898 | * @li 1 - Invert P and N on this lane |
| 899 | */ |
| 900 | IN UINT8 Flags; /**< Capabilities flags |
| 901 | * @li Flags bit[0] DDI_DATA_FLAGS_DP1_1_ONLY Selects downgrade PHY link to DP1.1 |
| 902 | * @li Flags bit[7:1] Reserved |
| 903 | */ |
| 904 | } PCIe_DDI_DATA; |
| 905 | |
| 906 | /// Engine Configuration |
| 907 | typedef struct { |
| 908 | IN UINT8 EngineType; /**< Engine type |
| 909 | * @li @b 0 - Ignore engine configuration |
| 910 | * @li @b 1 - PCIe port |
| 911 | * @li @b 2 - DDI |
| 912 | */ |
| 913 | IN UINT16 StartLane; /**< Start Lane ID (in reversed configuration StartLane > EndLane) |
| 914 | * See lane description for @ref F12PcieLaneDescription "Family 0x12" |
| 915 | * @ref F14ONPcieLaneDescription "Family 0x14(ON)". |
| 916 | * See lane configurations for @ref F12LaneConfigurations "Family 0x12" |
| 917 | * @ref F14ONLaneConfigurations "Family 0x14(ON)". |
| 918 | */ |
| 919 | IN UINT16 EndLane; /**< End lane ID (in reversed configuration StartLane > EndLane) |
| 920 | * See lane description for @ref F12PcieLaneDescription "Family 0x12", |
| 921 | * @ref F14ONPcieLaneDescription "Family 0x14(ON)". |
| 922 | * See lane configurations for @ref F12LaneConfigurations "Family 0x12" |
| 923 | * @ref F14ONLaneConfigurations "Family 0x14(ON)". |
| 924 | */ |
| 925 | |
| 926 | } PCIe_ENGINE_DATA; |
| 927 | |
| 928 | /// PCIe port descriptor |
| 929 | typedef struct { |
| 930 | IN UINT32 Flags; /**< Descriptor flags |
| 931 | * @li @b Bit31 - last descriptor in complex |
| 932 | */ |
| 933 | IN PCIe_ENGINE_DATA EngineData; ///< Engine data |
| 934 | IN PCIe_PORT_DATA Port; ///< PCIe port specific configuration info |
| 935 | } PCIe_PORT_DESCRIPTOR; |
| 936 | |
| 937 | /// DDI descriptor |
| 938 | typedef struct { |
| 939 | IN UINT32 Flags; /**< Descriptor flags |
| 940 | * @li @b Bit31 - last descriptor in complex |
| 941 | */ |
| 942 | IN PCIe_ENGINE_DATA EngineData; ///< Engine data |
| 943 | IN PCIe_DDI_DATA Ddi; ///< DDI port specific configuration info |
| 944 | } PCIe_DDI_DESCRIPTOR; |
| 945 | |
| 946 | /// PCIe Complex descriptor |
| 947 | typedef struct { |
| 948 | IN UINT32 Flags; /**< Descriptor flags |
| 949 | * @li @b Bit31 - last descriptor in topology |
| 950 | */ |
| 951 | IN UINT32 SocketId; ///< Socket Id |
Bruce Griffith | 283ba78 | 2013-06-04 14:16:24 -0600 | [diff] [blame] | 952 | IN CONST PCIe_PORT_DESCRIPTOR *PciePortList; ///< Pointer to array of PCIe port descriptors or NULL (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST). |
| 953 | IN CONST PCIe_DDI_DESCRIPTOR *DdiLinkList; ///< Pointer to array DDI link descriptors (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST). |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 954 | IN VOID *Reserved; ///< Reserved for future use |
| 955 | } PCIe_COMPLEX_DESCRIPTOR; |
| 956 | |
| 957 | /// Action to control PCIe slot reset |
| 958 | typedef enum { |
| 959 | AssertSlotReset, ///< Assert slot reset |
| 960 | DeassertSlotReset ///< Deassert slot reset |
| 961 | } PCIE_RESET_CONTROL; |
| 962 | |
| 963 | ///Slot Reset Info |
| 964 | typedef struct { |
| 965 | IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header |
| 966 | IN UINT8 ResetId; ///< Slot reset ID as specified in PCIe_PORT_DESCRIPTOR |
| 967 | IN UINT8 ResetControl; ///< Reset control as in PCIE_RESET_CONTROL |
| 968 | } PCIe_SLOT_RESET_INFO; |
| 969 | |
| 970 | #define GFX_VBIOS_IMAGE_FLAG_SPECIAL_POST 0x1 |
| 971 | |
| 972 | ///VBIOS image info |
| 973 | typedef struct { |
| 974 | IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header |
| 975 | OUT VOID *ImagePtr; ///< Pointer to VBIOS image |
| 976 | IN PCI_ADDR GfxPciAddress; ///< PCI address of integrated graphics controller |
| 977 | IN UINT32 Flags; ///< BIT[0] - special repost requred |
| 978 | } GFX_VBIOS_IMAGE_INFO; |
| 979 | |
| 980 | /// Engine descriptor type |
| 981 | typedef enum { |
| 982 | PcieUnusedEngine = 0, ///< Unused descriptor |
| 983 | PciePortEngine = 1, ///< PCIe port |
| 984 | PcieDdiEngine = 2, ///< DDI |
| 985 | MaxPcieEngine ///< Max engine type for boundary check. |
| 986 | } PCIE_ENGINE_TYPE; |
| 987 | |
| 988 | /// PCIe link capability/speed |
| 989 | typedef enum { |
| 990 | PcieGenMaxSupported, ///< Maximum supported |
| 991 | PcieGen1 = 1, ///< Gen1 |
| 992 | PcieGen2, ///< Gen2 |
| 993 | PcieGen3, ///< Gen3 |
| 994 | MaxPcieGen ///< Max Gen for boundary check |
| 995 | } PCIE_LINK_SPEED_CAP; |
| 996 | |
| 997 | /// PCIe PSPP Power policy |
| 998 | typedef enum { |
| 999 | PsppDisabled, ///< PSPP disabled |
| 1000 | PsppPerformance = 1, ///< Performance |
| 1001 | PsppBalanceHigh, ///< Balance-High |
| 1002 | PsppBalanceLow, ///< Balance-Low |
| 1003 | PsppPowerSaving, ///< Power Saving |
| 1004 | MaxPspp ///< Max Pspp for boundary check |
| 1005 | } PCIE_PSPP_POLICY; |
| 1006 | |
| 1007 | /// DDI display connector type |
| 1008 | typedef enum { |
| 1009 | ConnectorTypeDP, ///< DP |
| 1010 | ConnectorTypeEDP, ///< eDP |
| 1011 | ConnectorTypeSingleLinkDVI, ///< Single Link DVI-D |
| 1012 | ConnectorTypeDualLinkDVI, ///< Dual Link DVI-D |
| 1013 | ConnectorTypeHDMI, ///< HDMI |
| 1014 | ConnectorTypeTravisDpToVga, ///< Travis DP-to-VGA |
| 1015 | ConnectorTypeTravisDpToLvds, ///< Travis DP-to-LVDS |
| 1016 | ConnectorTypeNutmegDpToVga, ///< Hudson-2 NutMeg DP-to-VGA |
| 1017 | ConnectorTypeSingleLinkDviI, ///< Single Link DVI-I |
| 1018 | ConnectorTypeCrt, ///< CRT (VGA) |
| 1019 | ConnectorTypeLvds, ///< LVDS |
| 1020 | ConnectorTypeEDPToLvds, ///< 3rd party common eDP-to-LVDS translator chip without AMD SW init |
| 1021 | ConnectorTypeEDPToRealtecLvds, ///< Realtek eDP-to-LVDS tansaltor which require AMD SW init |
| 1022 | ConnectorTypeAutoDetect, ///< VBIOS auto detect connector type (native LVDS, eDP or Travis-LVDS) |
| 1023 | MaxConnectorType ///< Not valid value, used to verify input |
| 1024 | } PCIE_CONNECTOR_TYPE; |
| 1025 | |
| 1026 | /// PCIe link channel type |
| 1027 | typedef enum { |
| 1028 | ChannelTypeLowLoss, ///< Low Loss |
| 1029 | ChannelTypeHighLoss, ///< High Loss |
| 1030 | ChannelTypeMob0db, ///< Mobile 0dB |
| 1031 | ChannelTypeMob3db, ///< Mobile 3dB |
| 1032 | ChannelTypeExt6db, ///< Extended 6dB |
| 1033 | ChannelTypeExt8db, ///< Extended 8dB |
| 1034 | MaxChannelType ///< Not valid value, used to verify input |
| 1035 | } PCIE_CHANNEL_TYPE; |
| 1036 | |
| 1037 | /// PCIe link ASPM |
| 1038 | typedef enum { |
| 1039 | AspmDisabled, ///< Disabled |
| 1040 | AspmL0s, ///< PCIe L0s link state |
| 1041 | AspmL1, ///< PCIe L1 link state |
| 1042 | AspmL0sL1, ///< PCIe L0s & L1 link state |
| 1043 | MaxAspm ///< Not valid value, used to verify input |
| 1044 | } PCIE_ASPM_TYPE; |
| 1045 | |
| 1046 | /// PCIe link hotplug support |
| 1047 | typedef enum { |
| 1048 | HotplugDisabled, ///< Hotplug disable |
| 1049 | HotplugBasic, ///< Basic Hotplug |
| 1050 | HotplugServer, ///< Server Hotplug |
| 1051 | HotplugEnhanced, ///< Enhanced |
| 1052 | HotplugInboard, ///< Inboard |
| 1053 | MaxHotplug ///< Not valid value, used to verify input |
| 1054 | } PCIE_HOTPLUG_TYPE; |
| 1055 | |
| 1056 | /// PCIe link initialization |
| 1057 | typedef enum { |
| 1058 | PortDisabled, ///< Disable |
| 1059 | PortEnabled ///< Enable |
| 1060 | } PCIE_PORT_ENABLE; |
| 1061 | |
| 1062 | /// DDI Aux channel |
| 1063 | typedef enum { |
| 1064 | Aux1, ///< Aux1 |
| 1065 | Aux2, ///< Aux2 |
| 1066 | Aux3, ///< Aux3 |
| 1067 | Aux4, ///< Aux4 |
| 1068 | Aux5, ///< Aux5 |
| 1069 | Aux6, ///< Aux6 |
| 1070 | MaxAux ///< Not valid value, used to verify input |
| 1071 | } PCIE_AUX_TYPE; |
| 1072 | |
| 1073 | /// DDI Hdp Index |
| 1074 | typedef enum { |
| 1075 | Hdp1, ///< Hdp1 |
| 1076 | Hdp2, ///< Hdp2 |
| 1077 | Hdp3, ///< Hdp3 |
| 1078 | Hdp4, ///< Hdp4 |
| 1079 | Hdp5, ///< Hdp5 |
| 1080 | Hdp6, ///< Hdp6 |
| 1081 | MaxHdp ///< Not valid value, used to verify input |
| 1082 | } PCIE_HDP_TYPE; |
| 1083 | |
| 1084 | /// PCIe_DDI_DATA.Flags definitions |
| 1085 | #define DDI_DATA_FLAGS_DP1_1_ONLY 0x01 ///< BIT[0] Selects downgrade PHY link to DP1.1 |
| 1086 | |
| 1087 | |
| 1088 | // Macro for statically initialization of various structures |
| 1089 | #define PCIE_ENGINE_DATA_INITIALIZER(mType, mStartLane, mEndLane) {mType, mStartLane, mEndLane} |
| 1090 | #define PCIE_PORT_DATA_INITIALIZER(mPortPresent, mChannelType, mDevAddress, mHotplug, mMaxLinkSpeed, mMaxLinkCap, mAspm, mResetId) \ |
| 1091 | {mPortPresent, mChannelType, mDevAddress, 0, mMaxLinkSpeed, mAspm, mHotplug, mResetId, {0, mMaxLinkCap, 0, 0}, {0, 0, 0}, EndpointDetect} |
| 1092 | #define PCIE_DDI_DATA_INITIALIZER(mConnectorType, mAuxIndex, mHpdIndex ) \ |
| 1093 | {mConnectorType, mAuxIndex, mHpdIndex, {{0}, {0}}, 0, 0} |
| 1094 | #define PCIE_DDI_DATA_INITIALIZER_V1(mConnectorType, mAuxIndex, mHpdIndex, mMapping0, mMapping1, mPNInversion) \ |
| 1095 | {mConnectorType, mAuxIndex, mHpdIndex, {mMapping0, mMapping1}, mPNInversion, 0} |
| 1096 | #define PCIE_DDI_DATA_INITIALIZER_V2(mConnectorType, mAuxIndex, mHpdIndex, mMapping0, mMapping1, mPNInversion, mFlags) \ |
| 1097 | {mConnectorType, mAuxIndex, mHpdIndex, {mMapping0, mMapping1}, mPNInversion, mFlags} |
| 1098 | |
| 1099 | ///IOMMU requestor ID |
| 1100 | typedef struct { |
| 1101 | IN UINT16 Bus :8; ///< Bus |
| 1102 | IN UINT16 Device :5; ///< Device |
| 1103 | IN UINT16 Function :3; ///< Function |
| 1104 | } IOMMU_REQUESTOR_ID; |
| 1105 | |
| 1106 | /// IVMD exclusion range descriptor |
| 1107 | typedef struct { |
| 1108 | IN UINT32 Flags; /**< Descriptor flags |
| 1109 | * @li @b Flags[31] - Terminate descriptor array. |
| 1110 | * @li @b Flags[30] - Ignore descriptor. |
| 1111 | */ |
| 1112 | IN IOMMU_REQUESTOR_ID RequestorIdStart; ///< Requestor ID start |
| 1113 | IN IOMMU_REQUESTOR_ID RequestorIdEnd; ///< Requestor ID end (use same as start for single ID) |
| 1114 | IN UINT64 RangeBaseAddress; ///< Phisical base address of exclusion range |
| 1115 | IN UINT64 RangeLength; ///< Length of exclusion range in bytes |
| 1116 | } IOMMU_EXCLUSION_RANGE_DESCRIPTOR; |
| 1117 | |
| 1118 | /*---------------------------------------------------------------------------- |
| 1119 | * GNB configuration info |
| 1120 | *---------------------------------------------------------------------------- |
| 1121 | */ |
| 1122 | |
| 1123 | /// LVDS Misc Control Field |
| 1124 | typedef struct { |
| 1125 | IN UINT8 FpdiMode:1; ///< This item configures LVDS 888bit panel mode |
| 1126 | ///< @li FALSE = LVDS 888 panel in LDI mode |
| 1127 | ///< @li TRUE = LVDS 888 panel in FPDI mode |
| 1128 | ///< @BldCfgItem{BLDCFG_LVDS_MISC_888_FPDI_MODE} |
| 1129 | IN UINT8 DlChSwap:1; ///< This item configures LVDS panel lower and upper link mapping |
| 1130 | ///< @li FALSE = Lower link and upper link not swap |
| 1131 | ///< @li TRUE = Lower link and upper link are swapped |
| 1132 | ///< @BldCfgItem{BLDCFG_LVDS_MISC_DL_CH_SWAP} |
| 1133 | IN UINT8 VsyncActiveLow:1; ///< This item configures polarity of frame pulse encoded in lvds data stream |
| 1134 | ///< @li FALSE = Active high Frame Pulse/Vsync |
| 1135 | ///< @li TRUE = Active low Frame Pulse/Vsync |
| 1136 | ///< @BldCfgItem{BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW} |
| 1137 | IN UINT8 HsyncActiveLow:1; ///< This item configures polarity of line pulse encoded in lvds data |
| 1138 | ///< @li FALSE = Active high Line Pulse |
| 1139 | ///< @li TRUE = Active low Line Pulse / Hsync |
| 1140 | ///< @BldCfgItem{BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW} |
| 1141 | IN UINT8 BLONActiveLow:1; ///< This item configures polarity of signal sent to digital BLON output pin |
| 1142 | ///< @li FALSE = Not inverted(active high) |
| 1143 | ///< @li TRUE = Inverted (active low) |
| 1144 | ///< @BldCfgItem{BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW} |
| 1145 | IN UINT8 TravisLvdsVoltOverwriteEn:1; ///< This item configures polarity of Travis LVDS output voltage overwrite |
| 1146 | ///< @li FALSE = Travis LVDS output voltage overwrite disable, use VBIOS default setting. |
| 1147 | ///< @li TRUE = Use ucTravisLVDSVolAdjust value to program Travis register LVDS_CTRL_4 |
| 1148 | ///< @BldCfgItem{BLDCFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE} |
| 1149 | IN UINT8 Reserved:2; ///< Reserved |
| 1150 | } LVDS_MISC_CONTROL_FIELD; |
| 1151 | |
| 1152 | /// LVDS Misc Control |
| 1153 | typedef union _LVDS_MISC_CONTROL { |
| 1154 | IN LVDS_MISC_CONTROL_FIELD Field; ///< LVDS_MISC_CONTROL_FIELD |
| 1155 | IN UINT8 Value; ///< LVDS Misc Control Value |
| 1156 | } LVDS_MISC_CONTROL; |
| 1157 | |
| 1158 | /// Display Misc Control Field |
| 1159 | typedef struct { |
| 1160 | IN UINT8 Reserved1:3; ///< Reserved |
| 1161 | IN UINT8 VbiosFastBootEn:1; ///< This item configures VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open. |
| 1162 | ///< @li FALSE = VBIOS fast boot is disable. |
| 1163 | ///< @li TRUE = VBIOS fast boot is enable. |
| 1164 | ///< @BldCfgItem{BLDCFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE} |
| 1165 | IN UINT8 Reserved2:4; ///< Reserved |
| 1166 | } DISPLAY_MISC_CONTROL_FIELD; |
| 1167 | |
| 1168 | /// LVDS Misc Control |
| 1169 | typedef union _DISPLAY_MISC_CONTROL { |
| 1170 | IN DISPLAY_MISC_CONTROL_FIELD Field; ///< DISPLAY_MISC_CONTROL_FIELD |
| 1171 | IN UINT8 Value; ///< Display Misc Control Value |
| 1172 | } DISPLAY_MISC_CONTROL; |
| 1173 | |
| 1174 | /// POST Configuration settings for GNB. |
| 1175 | typedef struct { |
| 1176 | IN UINT8 IgpuEnableDisablePolicy; ///< This item defines the iGPU Enable/Disable policy |
| 1177 | ///< @li 0 = Auto - use existing default - |
| 1178 | ///< @li 1 = Disable iGPU if any PCIe/PCI graphics card present |
| 1179 | ///< @BldCfgItem{BLDCFG_IGPU_ENABLE_DISABLE_POLICY} |
| 1180 | } GNB_POST_CONFIGURATION; |
| 1181 | |
| 1182 | /// iGPU Enable/Disable Policy values |
| 1183 | #define IGPU_DISABLE_AUTO 0 ///< Auto setting - disable iGPU if ANY PCI graphics or non-AMD PCIe graphics |
| 1184 | #define IGPU_DISABLE_ANY_PCIE 1 ///< Disable iGPU if any PCI or PCIE graphics card is present |
| 1185 | |
| 1186 | /// ENV Configuration settings for GNB. |
| 1187 | typedef struct { |
| 1188 | IN UINT8 Gnb3dStereoPinIndex; ///< 3D Stereo Pin ID. |
| 1189 | ///< @li 0 = Stereo 3D is disabled (default). |
| 1190 | ///< @li 1 = Use processor pin HPD1. |
| 1191 | ///< @li 2 = Use processor pin HPD2 |
| 1192 | ///< @li 3 = Use processor pin HPD3 |
| 1193 | ///< @li 4 = Use processor pin HPD4 |
| 1194 | ///< @li 5 = Use processor pin HPD5 |
| 1195 | ///< @li 6 = Use processor pin HPD6 |
| 1196 | ///< @BldCfgItem{BLDCFG_STEREO_3D_PINOUT} |
| 1197 | IN BOOLEAN IommuSupport; ///< IOMMU support. |
| 1198 | ///< @li FALSE = Disabled. Disable and hide IOMMU device. |
| 1199 | ///< @li TRUE = Initialize IOMMU subsystem. Generate ACPI IVRS table. |
| 1200 | ///< BldCfgItem{BLDCFG_IOMMU_SUPPORT} |
| 1201 | IN UINT16 LvdsSpreadSpectrum; ///< Spread spectrum value in 0.01 % |
| 1202 | ///< BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM} |
| 1203 | IN UINT16 LvdsSpreadSpectrumRate; ///< Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz |
| 1204 | ///< BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE} |
| 1205 | IN UINT8 LvdsPowerOnSeqDigonToDe; ///< This item configures panel initialization timing. |
| 1206 | ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE} |
| 1207 | IN UINT8 LvdsPowerOnSeqDeToVaryBl; ///< This item configures panel initialization timing. |
| 1208 | ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL} |
| 1209 | IN UINT8 LvdsPowerOnSeqDeToDigon; ///< This item configures panel initialization timing. |
| 1210 | ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON} |
| 1211 | IN UINT8 LvdsPowerOnSeqVaryBlToDe; ///< This item configures panel initialization timing. |
| 1212 | ///< @BldCfgItem{BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE} |
| 1213 | IN UINT8 LvdsPowerOnSeqOnToOffDelay; ///< This item configures panel initialization timing. |
| 1214 | ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY} |
| 1215 | IN UINT8 LvdsPowerOnSeqVaryBlToBlon; ///< This item configures panel initialization timing. |
| 1216 | ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON} |
| 1217 | IN UINT8 LvdsPowerOnSeqBlonToVaryBl; ///< This item configures panel initialization timing. |
| 1218 | ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL} |
| 1219 | IN UINT16 LvdsMaxPixelClockFreq; ///< This item configures the maximum pixel clock frequency supported. |
| 1220 | ///< @BldCfgItem{BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ} |
| 1221 | IN UINT32 LcdBitDepthControlValue; ///< This item configures the LCD bit depth control settings. |
| 1222 | ///< @BldCfgItem{BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE} |
| 1223 | IN UINT8 Lvds24bbpPanelMode; ///< This item configures the LVDS 24 BBP mode. |
| 1224 | ///< @BldCfgItem{BLDCFG_LVDS_24BBP_PANEL_MODE} |
| 1225 | IN LVDS_MISC_CONTROL LvdsMiscControl;///< This item configures LVDS swap/Hsync/Vsync/BLON |
| 1226 | IN UINT16 PcieRefClkSpreadSpectrum; ///< Spread spectrum value in 0.01 % |
| 1227 | ///< @BldCfgItem{BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM} |
| 1228 | IN BOOLEAN GnbRemoteDisplaySupport; ///< This item enables Wireless Display Support |
| 1229 | ///< @li TRUE = Enable Wireless Display Support |
| 1230 | ///< @li FALSE = Disable Wireless Display Support |
| 1231 | ///< @BldCfgItem{BLDCFG_REMOTE_DISPLAY_SUPPORT} |
| 1232 | IN UINT8 LvdsMiscVoltAdjustment; ///< Travis register LVDS_CTRL_4 to adjust LVDS output voltage |
| 1233 | ///< @BldCfgItem{BLDCFG_LVDS_MISC_VOL_ADJUSTMENT} |
| 1234 | IN DISPLAY_MISC_CONTROL DisplayMiscControl;///< This item configures display misc control |
| 1235 | } GNB_ENV_CONFIGURATION; |
| 1236 | |
| 1237 | /// Configuration settings for GNB. |
| 1238 | typedef struct { |
| 1239 | IN UINT8 iGpuVgaMode; ///< VGA resourses decoding configuration for iGPU |
| 1240 | ///< @li 0 = iGPU decode all VGA resourses (must be promary VGA adapter) |
| 1241 | ///< @li 1 = iGPU will not decode any VGA resourses (must be secondary graphics adapter) |
| 1242 | } GNB_MID_CONFIGURATION; |
| 1243 | |
| 1244 | /// GNB configuration info |
| 1245 | typedef struct { |
| 1246 | IN PCIe_COMPLEX_DESCRIPTOR *PcieComplexList; /**< Pointer to array of structures describe PCIe topology on each processor package or NULL. |
| 1247 | * Last element of array must ne terminated with DESCRIPTOR_TERMINATE_LIST |
| 1248 | * Example of topology definition for single socket system: |
| 1249 | * @code |
| 1250 | * PCIe_PORT_DESCRIPTOR PortList [] = { |
| 1251 | * // Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...) |
| 1252 | * { |
| 1253 | * 0, //Descriptor flags |
| 1254 | * PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15), |
| 1255 | * PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) |
| 1256 | * }, |
| 1257 | * // Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...) |
| 1258 | * { |
| 1259 | * 0, //Descriptor flags |
| 1260 | * PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 16, 19), |
| 1261 | * PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) |
| 1262 | * }, |
| 1263 | * // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) |
| 1264 | * { |
| 1265 | * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array |
| 1266 | * PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), |
| 1267 | * PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) |
| 1268 | * } |
| 1269 | * }; |
| 1270 | * PCIe_PORT_DESCRIPTOR DdiList [] = { |
| 1271 | * // Initialize Ddi descriptor (DDI interface Lanes 24:27, Display Port Connector, ...) |
| 1272 | * { |
| 1273 | * 0, //Descriptor flags |
| 1274 | * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), |
Paul Menzel | 07e0f1b | 2013-04-13 15:58:03 +0200 | [diff] [blame] | 1275 | * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1276 | * }, |
| 1277 | * // Initialize Ddi descriptor (DDI interface Lanes 28:31, HDMI, ...) |
| 1278 | * { |
| 1279 | * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array |
| 1280 | * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31), |
Paul Menzel | 07e0f1b | 2013-04-13 15:58:03 +0200 | [diff] [blame] | 1281 | * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2) |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1282 | * } |
| 1283 | * }; |
| 1284 | * PCIe_COMPLEX_DESCRIPTOR PlatformTopology = { |
| 1285 | * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate complexes list |
| 1286 | * 0, //Socket ID |
| 1287 | * &PortList[0], |
| 1288 | * &DdiList[0], |
| 1289 | * } |
| 1290 | * @endcode |
| 1291 | */ |
| 1292 | IN UINT8 PsppPolicy; /**< PSPP (PCIe Speed Power Policy) |
| 1293 | * @li @b 0 - Disabled |
| 1294 | * @li @b 1 - Performance |
| 1295 | * @li @b 2 - Balance-High |
| 1296 | * @li @b 3 - Balance-Low |
| 1297 | * @li @b 4 - Power Saving |
| 1298 | */ |
| 1299 | |
| 1300 | } GNB_CONFIGURATION; |
| 1301 | // |
| 1302 | // MEMORY-SPECIFIC DATA STRUCTURES |
| 1303 | // |
| 1304 | // |
| 1305 | // |
| 1306 | // |
| 1307 | // AGESA MAXIMIUM VALUES |
| 1308 | // |
| 1309 | // These Max values are used to define array sizes and associated loop |
| 1310 | // counts in the code. They reflect the maximum values that AGESA |
| 1311 | // currently supports and does not necessarily reflect the hardware |
| 1312 | // capabilities of configuration. |
| 1313 | // |
| 1314 | |
| 1315 | #define MAX_SOCKETS_SUPPORTED 8 ///< Max number of sockets in system |
| 1316 | #define MAX_CHANNELS_PER_SOCKET 4 ///< Max Channels per sockets |
| 1317 | #define MAX_DIMMS_PER_CHANNEL 4 ///< Max DIMMs on a memory channel (independent of platform) |
| 1318 | #define NUMBER_OF_DELAY_TABLES 9 ///< Number of tables defined in CH_DEF_STRUCT. |
| 1319 | ///< Eg: UINT16 *RcvEnDlys; |
| 1320 | ///< UINT8 *WrDqsDlys; |
| 1321 | ///< UINT8 *RdDqsDlys; |
| 1322 | ///< UINT8 *WrDatDlys; |
| 1323 | ///< UINT8 *RdDqsMinDlys; |
| 1324 | ///< UINT8 *RdDqsMaxDlys; |
| 1325 | ///< UINT8 *WrDatMinDlys; |
| 1326 | ///< UINT8 *WrDatMaxDlys; |
| 1327 | #define NUMBER_OF_FAILURE_MASK_TABLES 1 ///< Number of failure mask tables |
| 1328 | |
| 1329 | #define MAX_PLATFORM_TYPES 16 ///< Platform types per system |
| 1330 | |
| 1331 | #define MCT_TRNG_KEEPOUT_START 0x00004000ul ///< base [39:8] |
| 1332 | #define MCT_TRNG_KEEPOUT_END 0x00007FFFul ///< base [39:8] |
| 1333 | |
| 1334 | #define UMA_ATTRIBUTE_INTERLEAVE 0x80000000ul ///< Uma Region is interleaved |
| 1335 | #define UMA_ATTRIBUTE_ON_DCT0 0x40000000ul ///< UMA resides on memory that belongs to DCT0 |
| 1336 | #define UMA_ATTRIBUTE_ON_DCT1 0x20000000ul ///< UMA resides on memory that belongs to DCT1 |
| 1337 | |
| 1338 | typedef UINT8 PSO_TABLE; ///< Platform Configuration Table |
| 1339 | |
| 1340 | // AGESA DEFINITIONS |
| 1341 | // |
| 1342 | // Many of these are derived from the platform and hardware specific definitions |
| 1343 | |
| 1344 | /// EccSymbolSize override value |
| 1345 | #define ECCSYMBOLSIZE_USE_BKDG 0 ///< Use BKDG Recommended Value |
| 1346 | #define ECCSYMBOLSIZE_FORCE_X4 4 ///< Force to x4 |
| 1347 | #define ECCSYMBOLSIZE_FORCE_X8 8 ///< Force to x8 |
| 1348 | /// CPU Package Type |
| 1349 | #define PT_L1 0 ///< L1 Package type |
| 1350 | #define PT_M2 1 ///< AM Package type |
| 1351 | #define PT_S1 2 ///< S1 Package type |
| 1352 | |
| 1353 | /// Structures use to pass system Logical CPU-ID |
| 1354 | typedef struct { |
| 1355 | IN OUT UINT64 Family; ///< Indicates logical ID Family |
| 1356 | IN OUT UINT64 Revision; ///< Indicates logical ID Family |
| 1357 | } CPU_LOGICAL_ID; |
| 1358 | |
| 1359 | /// Build Configuration values for BLDCFG_AMD_PLATFORM_TYPE |
| 1360 | typedef enum { |
| 1361 | AMD_PLATFORM_SERVER = 0x8000, ///< Server |
| 1362 | AMD_PLATFORM_DESKTOP = 0x10000, ///< Desktop |
| 1363 | AMD_PLATFORM_MOBILE = 0x20000, ///< Mobile |
| 1364 | } AMD_PLATFORM_TYPE; |
| 1365 | |
| 1366 | /// Dram technology type |
| 1367 | typedef enum { |
| 1368 | DDR2_TECHNOLOGY, ///< DDR2 technology |
| 1369 | DDR3_TECHNOLOGY ///< DDR3 technology |
| 1370 | } TECHNOLOGY_TYPE; |
| 1371 | |
| 1372 | /// Build Configuration values for BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT & BLDCFG_MEMORY_CLOCK_SELECT |
| 1373 | typedef enum { |
| 1374 | DDR400_FREQUENCY = 200, ///< DDR 400 |
| 1375 | DDR533_FREQUENCY = 266, ///< DDR 533 |
| 1376 | DDR667_FREQUENCY = 333, ///< DDR 667 |
| 1377 | DDR800_FREQUENCY = 400, ///< DDR 800 |
| 1378 | DDR1066_FREQUENCY = 533, ///< DDR 1066 |
| 1379 | DDR1333_FREQUENCY = 667, ///< DDR 1333 |
| 1380 | DDR1600_FREQUENCY = 800, ///< DDR 1600 |
| 1381 | DDR1866_FREQUENCY = 933, ///< DDR 1866 |
| 1382 | DDR2100_FREQUENCY = 1050, ///< DDR 2100 |
| 1383 | DDR2133_FREQUENCY = 1066, ///< DDR 2133 |
| 1384 | DDR2400_FREQUENCY = 1200, ///< DDR 2400 |
| 1385 | UNSUPPORTED_DDR_FREQUENCY ///< Highest limit of DDR frequency |
| 1386 | } MEMORY_BUS_SPEED; |
| 1387 | |
| 1388 | /// Build Configuration values for BLDCFG_MEMORY_QUADRANK_TYPE |
| 1389 | typedef enum { |
| 1390 | QUADRANK_REGISTERED, ///< Quadrank registered DIMM |
| 1391 | QUADRANK_UNBUFFERED ///< Quadrank unbuffered DIMM |
| 1392 | } QUANDRANK_TYPE; |
| 1393 | |
| 1394 | /// Build Configuration values for BLDCFG_TIMING_MODE_SELECT |
| 1395 | typedef enum { |
| 1396 | TIMING_MODE_AUTO, ///< Use best rate possible |
| 1397 | TIMING_MODE_LIMITED, ///< Set user top limit |
| 1398 | TIMING_MODE_SPECIFIC ///< Set user specified speed |
| 1399 | } USER_MEMORY_TIMING_MODE; |
| 1400 | |
| 1401 | /// Build Configuration values for BLDCFG_POWER_DOWN_MODE |
| 1402 | typedef enum { |
| 1403 | POWER_DOWN_BY_CHANNEL, ///< Channel power down mode |
| 1404 | POWER_DOWN_BY_CHIP_SELECT, ///< Chip select power down mode |
| 1405 | POWER_DOWN_MODE_AUTO ///< AGESA to select power down mode |
| 1406 | } POWER_DOWN_MODE; |
| 1407 | |
| 1408 | /// Low voltage support |
| 1409 | typedef enum { |
| 1410 | VOLT_INITIAL, ///< Initial value for VDDIO |
| 1411 | VOLT1_5, ///< 1.5 Volt |
| 1412 | VOLT1_35, ///< 1.35 Volt |
| 1413 | VOLT1_25, ///< 1.25 Volt |
| 1414 | VOLT_UNSUPPORTED = 0xFF ///< No common voltage found |
| 1415 | } DIMM_VOLTAGE; |
| 1416 | |
| 1417 | /// UMA Mode |
| 1418 | typedef enum { |
| 1419 | UMA_NONE = 0, ///< UMA None |
| 1420 | UMA_SPECIFIED = 1, ///< UMA Specified |
| 1421 | UMA_AUTO = 2 ///< UMA Auto |
| 1422 | } UMA_MODE; |
| 1423 | |
| 1424 | /// Force Training Mode |
| 1425 | typedef enum { |
| 1426 | FORCE_TRAIN_1D = 0, ///< 1D Training only |
| 1427 | FORCE_ENUM1 = 1, |
| 1428 | FORCE_TRAIN_AUTO = 2 |
| 1429 | } FORCE_TRAIN_MODE; |
| 1430 | |
| 1431 | /// The possible DRAM prefetch mode settings. |
| 1432 | typedef enum { |
| 1433 | DRAM_PREFETCHER_AUTO, ///< Use the recommended setting for the processor. In most cases, the recommended setting is enabled. |
| 1434 | DISABLE_DRAM_PREFETCH_FOR_IO, ///< Disable DRAM prefetching for I/O requests only. |
| 1435 | DISABLE_DRAM_PREFETCH_FOR_CPU, ///< Disable DRAM prefetching for requests from processor cores only. |
| 1436 | DISABLE_DRAM_PREFETCHER, ///< Disable DRAM prefetching. |
| 1437 | MAX_DRAM_FREFETCH_MODE ///< Not a DRAM prefetch mode, use for limit checking. |
| 1438 | } DRAM_PREFETCH_MODE; |
| 1439 | |
| 1440 | /// Build Configuration values for BLDCFG_UMA_ALIGNMENT |
| 1441 | typedef enum { |
| 1442 | NO_UMA_ALIGNED = 0x00FFFFFF, ///< NO UMA aligned |
| 1443 | UMA_4MB_ALIGNED = 0x00FFFFC0, ///< UMA 4MB aligned |
| 1444 | UMA_128MB_ALIGNED = 0x00FFF800, ///< UMA 128MB aligned |
| 1445 | UMA_256MB_ALIGNED = 0x00FFF000, ///< UMA 256MB aligned |
| 1446 | UMA_512MB_ALIGNED = 0x00FFE000, ///< UMA 512MB aligned |
| 1447 | } UMA_ALIGNMENT; |
| 1448 | |
| 1449 | /// |
| 1450 | /// Global MCT Configuration Status Word (GStatus) |
| 1451 | /// |
| 1452 | typedef enum { |
| 1453 | GsbMTRRshort, ///< Ran out of MTRRs while mapping memory |
| 1454 | GsbAllECCDimms, ///< All banks of all Nodes are ECC capable |
| 1455 | GsbDramECCDis, ///< Dram ECC requested but not enabled. |
| 1456 | GsbSoftHole, ///< A Node Base gap was created |
| 1457 | GsbHWHole, ///< A HW dram remap was created |
| 1458 | GsbNodeIntlv, ///< Node Memory interleaving was enabled |
| 1459 | GsbSpIntRemapHole, ///< Special condition for Node Interleave and HW remapping |
| 1460 | GsbEnDIMMSpareNW, ///< Indicates that DIMM Spare can be used without a warm reset |
| 1461 | |
| 1462 | GsbEOL ///< End of list |
| 1463 | } GLOBAL_STATUS_FIELD; |
| 1464 | |
| 1465 | /// |
| 1466 | /// Local Error Status (DIE_STRUCT.ErrStatus[31:0]) |
| 1467 | /// |
| 1468 | typedef enum { |
| 1469 | EsbNoDimms, ///< No DIMMs |
| 1470 | EsbSpdChkSum, ///< SPD Checksum fail |
| 1471 | EsbDimmMismatchM, ///< dimm module type(buffer) mismatch |
| 1472 | EsbDimmMismatchT, ///< dimm CL/T mismatch |
| 1473 | EsbDimmMismatchO, ///< dimm organization mismatch (128-bit) |
| 1474 | EsbNoTrcTrfc, ///< SPD missing Trc or Trfc info |
| 1475 | EsbNoCycTime, ///< SPD missing byte 23 or 25 |
| 1476 | EsbBkIntDis, ///< Bank interleave requested but not enabled |
| 1477 | EsbDramECCDis, ///< Dram ECC requested but not enabled |
| 1478 | EsbSpareDis, ///< Online spare requested but not enabled |
| 1479 | EsbMinimumMode, ///< Running in Minimum Mode |
| 1480 | EsbNoRcvrEn, ///< No DQS Receiver Enable pass window found |
| 1481 | EsbSmallRcvr, ///< DQS Rcvr En pass window too small (far right of dynamic range) |
| 1482 | EsbNoDqsPos, ///< No DQS-DQ passing positions |
| 1483 | EsbSmallDqs, ///< DQS-DQ passing window too small |
| 1484 | EsbDCBKScrubDis, ///< DCache scrub requested but not enabled |
| 1485 | |
| 1486 | EsbEMPNotSupported, ///< Processor is not capable for EMP. |
| 1487 | EsbEMPConflict, ///< EMP requested but cannot be enabled since |
| 1488 | ///< channel interleaving, bank interleaving, or bank swizzle is enabled. |
| 1489 | EsbEMPDis, ///< EMP requested but cannot be enabled since |
| 1490 | ///< memory size of each DCT is not a power of two. |
| 1491 | |
| 1492 | EsbEOL ///< End of list |
| 1493 | } ERROR_STATUS_FIELD; |
| 1494 | |
| 1495 | /// |
| 1496 | /// Local Configuration Status (DIE_STRUCT.Status[31:0]) |
| 1497 | /// |
| 1498 | typedef enum { |
| 1499 | SbRegistered, ///< All DIMMs are Registered |
| 1500 | SbEccDimms, ///< All banks ECC capable |
| 1501 | SbParDimms, ///< All banks Addr/CMD Parity capable |
| 1502 | SbDiagClks, ///< Jedec ALL slots clock enable diag mode |
| 1503 | Sb128bitmode, ///< DCT in 128-bit mode operation |
| 1504 | Sb64MuxedMode, ///< DCT in 64-bit mux'ed mode. |
| 1505 | Sb2TMode, ///< 2T CMD timing mode is enabled. |
| 1506 | SbSWNodeHole, ///< Remapping of Node Base on this Node to create a gap. |
| 1507 | SbHWHole, ///< Memory Hole created on this Node using HW remapping. |
| 1508 | SbOver400Mhz, ///< DCT freq greater than or equal to 400MHz flag |
| 1509 | SbDQSPosPass2, ///< Used for TrainDQSPos DIMM0/1, when freq greater than or equal to 400MHz |
| 1510 | SbDQSRcvLimit, ///< Used for DQSRcvEnTrain to know we have reached the upper bound. |
| 1511 | SbExtConfig, ///< Indicate the default setting for extended PCI configuration support |
| 1512 | SbLrdimms, ///< All DIMMs are LRDIMMs |
| 1513 | |
| 1514 | SbEOL ///< End of list |
| 1515 | } LOCAL_STATUS_FIELD; |
| 1516 | |
| 1517 | |
| 1518 | ///< CPU MSR Register definitions ------------------------------------------ |
| 1519 | #define SYS_CFG 0xC0010010ul |
| 1520 | #define TOP_MEM 0xC001001Aul |
| 1521 | #define TOP_MEM2 0xC001001Dul |
| 1522 | #define HWCR 0xC0010015ul |
| 1523 | #define NB_CFG 0xC001001Ful |
| 1524 | |
| 1525 | #define FS_BASE 0xC0000100ul |
| 1526 | #define IORR0_BASE 0xC0010016ul |
| 1527 | #define IORR0_MASK 0xC0010017ul |
| 1528 | #define BU_CFG 0xC0011023ul |
| 1529 | #define BU_CFG2 0xC001102Aul |
| 1530 | #define COFVID_STAT 0xC0010071ul |
| 1531 | #define TSC 0x10 |
| 1532 | |
| 1533 | //----------------------------------------------------------------------------- |
| 1534 | /// |
| 1535 | /// SPD Data for each DIMM. |
| 1536 | /// |
| 1537 | typedef struct _SPD_DEF_STRUCT { |
| 1538 | IN BOOLEAN DimmPresent; ///< Indicates that the DIMM is present and Data is valid |
| 1539 | IN UINT8 Data[256]; ///< Buffer for 256 Bytes of SPD data from DIMM |
| 1540 | } SPD_DEF_STRUCT; |
| 1541 | |
| 1542 | /// |
| 1543 | /// Channel Definition Structure. |
| 1544 | /// This data structure defines entries that are specific to the channel initialization |
| 1545 | /// |
| 1546 | typedef struct _CH_DEF_STRUCT { |
| 1547 | OUT UINT8 ChannelID; ///< Physical channel ID of a socket(0 = CH A, 1 = CH B, 2 = CH C, 3 = CH D) |
| 1548 | OUT TECHNOLOGY_TYPE TechType; ///< Technology type of this channel |
| 1549 | OUT UINT8 ChDimmPresent; ///< For each bit n 0..7, 1 = DIMM n is present. |
| 1550 | ///< DIMM# Select Signal |
| 1551 | ///< 0 MA0_CS_L[0, 1] |
| 1552 | ///< 1 MB0_CS_L[0, 1] |
| 1553 | ///< 2 MA1_CS_L[0, 1] |
| 1554 | ///< 3 MB1_CS_L[0, 1] |
| 1555 | ///< 4 MA2_CS_L[0, 1] |
| 1556 | ///< 5 MB2_CS_L[0, 1] |
| 1557 | ///< 6 MA3_CS_L[0, 1] |
| 1558 | ///< 7 MB3_CS_L[0, 1] |
| 1559 | |
| 1560 | OUT struct _DCT_STRUCT *DCTPtr; ///< Pointer to the DCT data of this channel. |
| 1561 | OUT struct _DIE_STRUCT *MCTPtr; ///< Pointer to the node data of this channel. |
| 1562 | OUT SPD_DEF_STRUCT *SpdPtr; ///< Pointer to the SPD data for this channel. (Setup by NB Constructor) |
| 1563 | OUT SPD_DEF_STRUCT *DimmSpdPtr[MAX_DIMMS_PER_CHANNEL]; ///< Array of pointers to |
| 1564 | ///< SPD Data for each Dimm. (Setup by Tech Block Constructor) |
| 1565 | OUT UINT8 ChDimmValid; ///< For each bit n 0..3, 1 = DIMM n is valid and is/will be configured where 4..7 are reserved. |
| 1566 | ///< |
| 1567 | OUT UINT8 RegDimmPresent; ///< For each bit n 0..3, 1 = DIMM n is a registered DIMM where 4..7 are reserved. |
| 1568 | OUT UINT8 LrDimmPresent; ///< For each bit n 0..3, 1 = DIMM n is Load Reduced DIMM where 4..7 are reserved. |
| 1569 | OUT UINT8 SODimmPresent; ///< For each bit n 0..3, 1 = DIMM n is a SO-DIMM, where 4..7 are reserved. |
| 1570 | OUT UINT8 Loads; ///< Number of devices loading bus |
| 1571 | OUT UINT8 Dimms; ///< Number of DIMMs loading Channel |
| 1572 | OUT UINT8 Ranks; ///< Number of ranks loading Channel DATA |
| 1573 | OUT BOOLEAN SlowMode; ///< 1T or 2T CMD mode (slow access mode) |
| 1574 | ///< FALSE = 1T |
| 1575 | ///< TRUE = 2T |
| 1576 | ///< The following pointers will be pointed to dynamically allocated buffers. |
| 1577 | ///< Each buffer is two dimensional (RowCount x ColumnCount) and is lay-outed as in below. |
| 1578 | ///< Example: If DIMM and Byte based training, then |
| 1579 | ///< XX is a value in Hex |
| 1580 | ///< BYTE 0, BYTE 1, BYTE 2, BYTE 3, BYTE 4, BYTE 5, BYTE 6, BYTE 7, ECC BYTE |
| 1581 | ///< Row1 - Logical DIMM0 XX XX XX XX XX XX XX XX XX |
| 1582 | ///< Row2 - Logical DIMM1 XX XX XX XX XX XX XX XX XX |
| 1583 | OUT UINT16 *RcvEnDlys; ///< DQS Receiver Enable Delays |
| 1584 | OUT UINT8 *WrDqsDlys; ///< Write DQS delays (only valid for DDR3) |
| 1585 | OUT UINT8 *RdDqsDlys; ///< Read Dqs delays |
| 1586 | OUT UINT8 *WrDatDlys; ///< Write Data delays |
| 1587 | OUT UINT8 *RdDqs2dDlys; ///< 2d Read DQS data |
| 1588 | OUT UINT8 *RdDqsMinDlys; ///< Minimum Window for Read DQS |
| 1589 | OUT UINT8 *RdDqsMaxDlys; ///< Maximum Window for Read DQS |
| 1590 | OUT UINT8 *WrDatMinDlys; ///< Minimum Window for Write data |
| 1591 | OUT UINT8 *WrDatMaxDlys; ///< Maximum Window for Write data |
| 1592 | OUT UINT16 *RcvEnDlysMemPs1; ///< DQS Receiver Enable Delays for Mem Pstate 1 |
| 1593 | OUT UINT8 *WrDqsDlysMemPs1; ///< Write DQS delays (only valid for DDR3) for Mem Pstate 1 |
| 1594 | OUT UINT8 *RdDqsDlysMemPs1; ///< Read Dqs delays for Memory Pstate 1 |
| 1595 | OUT UINT8 *WrDatDlysMemPs1; ///< Write Data delays for Memory Pstate 1 |
| 1596 | OUT UINT8 *RdDqs2dDlysMemPs1; ///< 2d Read DQS data for Memory Pstate 1 |
| 1597 | OUT UINT8 *RdDqsMinDlysMemPs1; ///< Minimum Window for Read DQS for Memory Pstate 1 |
| 1598 | OUT UINT8 *RdDqsMaxDlysMemPs1; ///< Maximum Window for Read DQS for Memory Pstate 1 |
| 1599 | OUT UINT8 *WrDatMinDlysMemPs1; ///< Minimum Window for Write data for Memory Pstate 1 |
| 1600 | OUT UINT8 *WrDatMaxDlysMemPs1; ///< Maximum Window for Write data for Memory Pstate 1 |
| 1601 | OUT UINT8 RowCount; ///< Number of rows of the allocated buffer. |
| 1602 | OUT UINT8 ColumnCount; ///< Number of columns of the allocated buffer. |
| 1603 | OUT UINT8 *FailingBitMask; ///< Table of masks to Track Failing bits |
| 1604 | OUT UINT8 *FailingBitMaskMemPs1; ///< Table of masks to Track Failing bits for Memory Pstate 1 |
| 1605 | OUT UINT32 DctOdcCtl; ///< Output Driver Strength (see BKDG FN2:Offset 9Ch, index 00h) |
| 1606 | OUT UINT32 DctAddrTmg; ///< Address Bus Timing (see BKDG FN2:Offset 9Ch, index 04h) |
| 1607 | OUT UINT32 PhyRODTCSLow; ///< Phy Read ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 180h) |
| 1608 | OUT UINT32 PhyRODTCSHigh; ///< Phy Read ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 181h) |
| 1609 | OUT UINT32 PhyWODTCSLow; ///< Phy Write ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 182h) |
| 1610 | OUT UINT32 PhyWODTCSHigh; ///< Phy Write ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 183) |
| 1611 | OUT UINT8 PhyWLODT[4]; ///< Write Levelization ODT Pattern for Dimm 0-3 or CS 0-7(see BKDG FN2:Offset 9Ch, index 0x8[11:8]) |
| 1612 | OUT UINT16 DctEccDqsLike; ///< DCT DQS ECC UINT8 like... |
| 1613 | OUT UINT8 DctEccDqsScale; ///< DCT DQS ECC UINT8 scale |
| 1614 | OUT UINT16 PtrPatternBufA; ///< Ptr on stack to aligned DQS testing pattern |
| 1615 | OUT UINT16 PtrPatternBufB; ///< Ptr on stack to aligned DQS testing pattern |
| 1616 | OUT UINT8 ByteLane; ///< Current UINT8 Lane (0..7) |
| 1617 | OUT UINT8 Direction; ///< Current DQS-DQ training write direction (0=read, 1=write) |
| 1618 | OUT UINT8 Pattern; ///< Current pattern |
| 1619 | OUT UINT8 DqsDelay; ///< Current DQS delay value |
| 1620 | OUT UINT16 HostBiosSrvc1; ///< UINT16 sized general purpose field for use by host BIOS. Scratch space. |
| 1621 | OUT UINT32 HostBiosSrvc2; ///< UINT32 sized general purpose field for use by host BIOS. Scratch space. |
| 1622 | OUT UINT16 DctMaxRdLat[4]; ///< Max Read Latency (ns) for the DCT |
| 1623 | ///< DctMaxRdLat [i] is for NBPstate i |
| 1624 | OUT UINT8 DIMMValidCh; ///< DIMM# in CH |
| 1625 | OUT UINT8 MaxCh; ///< Max number of CH in system |
| 1626 | OUT UINT8 Dct; ///< Dct pointer |
| 1627 | OUT UINT8 WrDatGrossH; ///< Write Data Gross delay high value |
| 1628 | OUT UINT8 DqsRcvEnGrossL; ///< DQS Receive Enable Gross Delay low |
| 1629 | |
| 1630 | OUT UINT8 TrwtWB; ///< Non-SPD timing value for TrwtWB |
| 1631 | OUT UINT8 CurrRcvrDctADelay; ///< for keep current RcvrEnDly |
| 1632 | OUT UINT16 T1000; ///< get the T1000 figure (cycle time (ns) * 1K) |
| 1633 | OUT UINT8 DqsRcvEnPass; ///< for TrainRcvrEn UINT8 lane pass flag |
| 1634 | OUT UINT8 DqsRcvEnSaved; ///< for TrainRcvrEn UINT8 lane saved flag |
| 1635 | OUT UINT8 SeedPass1Remainder; ///< for Phy assisted DQS receiver enable training |
| 1636 | |
| 1637 | OUT UINT8 ClToNbFlag; ///< is used to restore ClLinesToNbDis bit after memory |
| 1638 | OUT UINT32 NodeSysBase; ///< for channel interleave usage |
| 1639 | OUT UINT8 RefRawCard[MAX_DIMMS_PER_CHANNEL]; ///< Array of rawcards detected |
| 1640 | OUT UINT8 CtrlWrd02[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 2 values per DIMM |
| 1641 | OUT UINT8 CtrlWrd03[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 3 values per DIMM |
| 1642 | OUT UINT8 CtrlWrd04[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 4 values per DIMM |
| 1643 | OUT UINT8 CtrlWrd05[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 5 values per DIMM |
| 1644 | OUT UINT8 CtrlWrd08[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 8 values per DIMM |
| 1645 | |
| 1646 | OUT UINT16 CsPresentDCT; ///< For each bit n 0..7, 1 = Chip-select n is present |
| 1647 | OUT UINT8 DimmMirrorPresent; ///< For each bit n 0..3, 1 = DIMM n is OnDimmMirror capable where 4..7 are reserved. |
| 1648 | OUT UINT8 DimmSpdCse; ///< For each bit n 0..3, 1 = DIMM n SPD checksum error where 4..7 are reserved. |
| 1649 | OUT UINT8 DimmExclude; ///< For each bit n 0..3, 1 = DIMM n gets excluded where 4..7 are reserved. |
| 1650 | OUT UINT8 DimmYr06; ///< Bitmap indicating which Dimms have a manufacturer's year code <= 2006 |
| 1651 | OUT UINT8 DimmWk2406; ///< Bitmap indicating which Dimms have a manufacturer's week code <= 24 of 2006 (June) |
| 1652 | OUT UINT8 DimmPlPresent; ///< Bitmap indicating that Planar (1) or Stacked (0) Dimms are present. |
| 1653 | OUT UINT8 DimmQrPresent; ///< QuadRank DIMM present? |
| 1654 | OUT UINT8 DimmDrPresent; ///< Bitmap indicating that Dual Rank Dimms are present |
| 1655 | OUT UINT8 DimmSRPresent; ///< Bitmap indicating that Single Rank Dimms are present |
| 1656 | OUT UINT8 Dimmx4Present; ///< For each bit n 0..3, 1 = DIMM n contains x4 data devices. where 4..7 are reserved. |
| 1657 | OUT UINT8 Dimmx8Present; ///< For each bit n 0..3, 1 = DIMM n contains x8 data devices. where 4..7 are reserved. |
| 1658 | OUT UINT8 Dimmx16Present; ///< For each bit n 0..3, 1 = DIMM n contains x16 data devices. where 4..7 are reserved. |
| 1659 | OUT UINT8 LrdimmPhysicalRanks[MAX_DIMMS_PER_CHANNEL];///< Number of Physical Ranks for LRDIMMs |
| 1660 | OUT UINT8 LrDimmLogicalRanks[MAX_DIMMS_PER_CHANNEL];///< Number of LRDIMM Logical ranks in this configuration |
| 1661 | OUT UINT8 LrDimmRankMult[MAX_DIMMS_PER_CHANNEL];///< Rank Multipication factor per dimm. |
| 1662 | OUT UINT8 DimmNibbleAccess; ///< For each bit n 0..3, 1 = DIMM n will use nibble signaling. Where 4..7 are reserved. |
| 1663 | OUT UINT8 *MemClkDisMap; ///< This pointer will be set to point to an array that describes |
| 1664 | ///< the routing of M[B,A]_CLK pins to the DIMMs' ranks. AGESA will |
| 1665 | ///< base on this array to disable unused MemClk to save power. |
| 1666 | ///< |
| 1667 | ///< The array must have 8 entries. Each entry, which associates with |
| 1668 | ///< one MemClkDis bit, is a bitmap of 8 CS that that MemClk is routed to. |
| 1669 | ///< Example: |
| 1670 | ///< BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package |
| 1671 | ///< is like below: |
| 1672 | ///< Bit AM3/S1g3 pin name |
| 1673 | ///< 0 M[B,A]_CLK_H/L[0] |
| 1674 | ///< 1 M[B,A]_CLK_H/L[1] |
| 1675 | ///< 2 M[B,A]_CLK_H/L[2] |
| 1676 | ///< 3 M[B,A]_CLK_H/L[3] |
| 1677 | ///< 4 M[B,A]_CLK_H/L[4] |
| 1678 | ///< 5 M[B,A]_CLK_H/L[5] |
| 1679 | ///< 6 M[B,A]_CLK_H/L[6] |
| 1680 | ///< 7 M[B,A]_CLK_H/L[7] |
| 1681 | ///< And platform has the following routing: |
| 1682 | ///< CS0 M[B,A]_CLK_H/L[4] |
| 1683 | ///< CS1 M[B,A]_CLK_H/L[2] |
| 1684 | ///< CS2 M[B,A]_CLK_H/L[3] |
| 1685 | ///< CS3 M[B,A]_CLK_H/L[5] |
| 1686 | ///< Then MemClkDisMap should be pointed to the following array: |
| 1687 | ///< CLK_2 CLK_3 CLK_4 CLK_5 |
| 1688 | ///< 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00 |
| 1689 | ///< Each entry of the array is the bitmask of 8 chip selects. |
| 1690 | |
| 1691 | OUT UINT8 *CKETriMap; ///< This pointer will be set to point to an array that describes |
| 1692 | ///< the routing of CKE pins to the DIMMs' ranks. |
| 1693 | ///< The array must have 2 entries. Each entry, which associates with |
| 1694 | ///< one CKE pin, is a bitmap of 8 CS that that CKE is routed to. |
| 1695 | ///< AGESA will base on this array to disable unused CKE pins to save power. |
| 1696 | |
| 1697 | OUT UINT8 *ODTTriMap; ///< This pointer will be set to point to an array that describes |
| 1698 | ///< the routing of ODT pins to the DIMMs' ranks. |
| 1699 | ///< The array must have 4 entries. Each entry, which associates with |
| 1700 | ///< one ODT pin, is a bitmap of 8 CS that that ODT is routed to. |
| 1701 | ///< AGESA will base on this array to disable unused ODT pins to save power. |
| 1702 | |
| 1703 | OUT UINT8 *ChipSelTriMap; ///< This pointer will be set to point to an array that describes |
| 1704 | ///< the routing of chip select pins to the DIMMs' ranks. |
| 1705 | ///< The array must have 8 entries. Each entry is a bitmap of 8 CS. |
| 1706 | ///< AGESA will base on this array to disable unused Chip select pins to save power. |
| 1707 | |
| 1708 | OUT BOOLEAN ExtendTmp; ///< If extended temperature is supported on all dimms on a channel. |
| 1709 | |
| 1710 | OUT UINT8 MaxVref; ///< Maximum Vref Value for channel |
| 1711 | |
| 1712 | OUT UINT8 Reserved[100]; ///< Reserved |
| 1713 | } CH_DEF_STRUCT; |
| 1714 | |
| 1715 | /// |
| 1716 | /// DCT Channel Timing Parameters. |
| 1717 | /// This data structure sets timings that are specific to the channel. |
| 1718 | /// |
| 1719 | typedef struct _CH_TIMING_STRUCT { |
| 1720 | OUT UINT16 DctDimmValid; ///< For each bit n 0..3, 1=DIMM n is valid and is/will be configured where 4..7 are reserved. |
| 1721 | OUT UINT16 DimmMirrorPresent; ///< For each bit n 0..3, 1=DIMM n is OnDimmMirror capable where 4..7 are reserved. |
| 1722 | OUT UINT16 DimmSpdCse; ///< For each bit n 0..3, 1=DIMM n SPD checksum error where 4..7 are reserved. |
| 1723 | OUT UINT16 DimmExclude; ///< For each bit n 0..3, 1 = DIMM n gets excluded where 4..7 are reserved. |
| 1724 | OUT UINT16 CsPresent; ///< For each bit n 0..7, 1=Chip-select n is present |
| 1725 | OUT UINT16 CsEnabled; ///< For each bit n 0..7, 1=Chip-select n is enabled |
| 1726 | OUT UINT16 CsTestFail; ///< For each bit n 0..7, 1=Chip-select n is present but disabled |
| 1727 | OUT UINT16 CsTrainFail; ///< Bitmap showing which chipselects failed training |
| 1728 | OUT UINT16 DIMM1KPage; ///< For each bit n 0..3, 1=DIMM n contains 1K page devices. where 4..7 are reserved |
| 1729 | OUT UINT16 DimmQrPresent; ///< QuadRank DIMM present? |
| 1730 | OUT UINT16 DimmDrPresent; ///< Bitmap indicating that Dual Rank Dimms are present , where 4..7 are reserved |
| 1731 | OUT UINT8 DimmSRPresent; ///< Bitmap indicating that Single Rank Dimms are present, where 4..7 are reserved |
| 1732 | OUT UINT16 Dimmx4Present; ///< For each bit n 0..3, 1=DIMM n contains x4 data devices. where 4..7 are reserved |
| 1733 | OUT UINT16 Dimmx8Present; ///< For each bit n 0..3, 1=DIMM n contains x8 data devices. where 4..7 are reserved |
| 1734 | OUT UINT16 Dimmx16Present; ///< For each bit n 0..3, 1=DIMM n contains x16 data devices. where 4..7 are reserved |
| 1735 | |
| 1736 | OUT UINT16 DIMMTrcd; ///< Minimax Trcd*40 (ns) of DIMMs |
| 1737 | OUT UINT16 DIMMTrp; ///< Minimax Trp*40 (ns) of DIMMs |
| 1738 | OUT UINT16 DIMMTrtp; ///< Minimax Trtp*40 (ns) of DIMMs |
| 1739 | OUT UINT16 DIMMTras; ///< Minimax Tras*40 (ns) of DIMMs |
| 1740 | OUT UINT16 DIMMTrc; ///< Minimax Trc*40 (ns) of DIMMs |
| 1741 | OUT UINT16 DIMMTwr; ///< Minimax Twr*40 (ns) of DIMMs |
| 1742 | OUT UINT16 DIMMTrrd; ///< Minimax Trrd*40 (ns) of DIMMs |
| 1743 | OUT UINT16 DIMMTwtr; ///< Minimax Twtr*40 (ns) of DIMMs |
| 1744 | OUT UINT16 DIMMTfaw; ///< Minimax Tfaw*40 (ns) of DIMMs |
| 1745 | OUT UINT16 TargetSpeed; ///< Target DRAM bus speed in MHz |
| 1746 | OUT UINT16 Speed; ///< DRAM bus speed in MHz |
| 1747 | ///< 400 (MHz) |
| 1748 | ///< 533 (MHz) |
| 1749 | ///< 667 (MHz) |
| 1750 | ///< 800 (MHz) |
| 1751 | ///< and so on... |
| 1752 | OUT UINT8 CasL; ///< CAS latency DCT setting (busclocks) |
| 1753 | OUT UINT8 Trcd; ///< DCT Trcd (busclocks) |
| 1754 | OUT UINT8 Trp; ///< DCT Trp (busclocks) |
| 1755 | OUT UINT8 Trtp; ///< DCT Trtp (busclocks) |
| 1756 | OUT UINT8 Tras; ///< DCT Tras (busclocks) |
| 1757 | OUT UINT8 Trc; ///< DCT Trc (busclocks) |
| 1758 | OUT UINT8 Twr; ///< DCT Twr (busclocks) |
| 1759 | OUT UINT8 Trrd; ///< DCT Trrd (busclocks) |
| 1760 | OUT UINT8 Twtr; ///< DCT Twtr (busclocks) |
| 1761 | OUT UINT8 Tfaw; ///< DCT Tfaw (busclocks) |
| 1762 | OUT UINT8 Trfc0; ///< DCT Logical DIMM0 Trfc |
| 1763 | ///< 0 = 75ns (for 256Mb devs) |
| 1764 | ///< 1 = 105ns (for 512Mb devs) |
| 1765 | ///< 2 = 127.5ns (for 1Gb devs) |
| 1766 | ///< 3 = 195ns (for 2Gb devs) |
| 1767 | ///< 4 = 327.5ns (for 4Gb devs) |
| 1768 | OUT UINT8 Trfc1; ///< DCT Logical DIMM1 Trfc (see Trfc0 for format) |
| 1769 | OUT UINT8 Trfc2; ///< DCT Logical DIMM2 Trfc (see Trfc0 for format) |
| 1770 | OUT UINT8 Trfc3; ///< DCT Logical DIMM3 Trfc (see Trfc0 for format) |
| 1771 | OUT UINT32 DctMemSize; ///< Base[47:16], total DRAM size controlled by this DCT. |
| 1772 | ///< |
| 1773 | OUT BOOLEAN SlowMode; ///< 1T or 2T CMD mode (slow access mode) |
| 1774 | ///< FALSE = 1T |
| 1775 | ///< TRUE = 2T |
| 1776 | OUT UINT8 TrwtTO; ///< DCT TrwtTO (busclocks) |
| 1777 | OUT UINT8 Twrrd; ///< DCT Twrrd (busclocks) |
| 1778 | OUT UINT8 Twrwr; ///< DCT Twrwr (busclocks) |
| 1779 | OUT UINT8 Trdrd; ///< DCT Trdrd (busclocks) |
| 1780 | OUT UINT8 TrwtWB; ///< DCT TrwtWB (busclocks) |
| 1781 | OUT UINT8 TrdrdSD; ///< DCT TrdrdSD (busclocks) |
| 1782 | OUT UINT8 TwrwrSD; ///< DCT TwrwrSD (busclocks) |
| 1783 | OUT UINT8 TwrrdSD; ///< DCT TwrrdSD (busclocks) |
| 1784 | OUT UINT16 MaxRdLat; ///< Max Read Latency |
| 1785 | OUT UINT8 WrDatGrossH; ///< Temporary variables must be removed |
| 1786 | OUT UINT8 DqsRcvEnGrossL; ///< Temporary variables must be removed |
| 1787 | } CH_TIMING_STRUCT; |
| 1788 | |
| 1789 | /// |
| 1790 | /// Data for each DCT. |
| 1791 | /// This data structure defines data used to configure each DRAM controller. |
| 1792 | /// |
| 1793 | typedef struct _DCT_STRUCT { |
| 1794 | OUT UINT8 Dct; ///< Current Dct |
| 1795 | OUT CH_TIMING_STRUCT Timings; ///< Channel Timing structure |
| 1796 | OUT CH_TIMING_STRUCT *TimingsMemPs1; ///< Pointed to channel timing structure for memory Pstate 1 |
| 1797 | OUT CH_DEF_STRUCT *ChData; ///< Pointed to a dynamically allocated array of Channel structures |
| 1798 | OUT UINT8 ChannelCount; ///< Number of channel per this DCT |
| 1799 | OUT BOOLEAN BkIntDis; ///< Bank interleave requested but not enabled on current DCT |
| 1800 | } DCT_STRUCT; |
| 1801 | |
| 1802 | |
| 1803 | /// |
| 1804 | /// Data Structure defining each Die. |
| 1805 | /// This data structure contains information that is used to configure each Die. |
| 1806 | /// |
| 1807 | typedef struct _DIE_STRUCT { |
| 1808 | |
| 1809 | /// Advanced: |
| 1810 | |
| 1811 | OUT UINT8 NodeId; ///< Node ID of current controller |
| 1812 | OUT UINT8 SocketId; ///< Socket ID of this Die |
| 1813 | OUT UINT8 DieId; ///< ID of this die relative to the socket |
| 1814 | OUT PCI_ADDR PciAddr; ///< Pci bus and device number of this controller. |
| 1815 | OUT AGESA_STATUS ErrCode; ///< Current error condition of Node |
| 1816 | ///< 0x0 = AGESA_SUCCESS |
| 1817 | ///< 0x1 = AGESA_UNSUPPORTED |
| 1818 | ///< 0x2 = AGESA_BOUNDS_CHK |
| 1819 | ///< 0x3 = AGESA_ALERT |
| 1820 | ///< 0x4 = AGESA_WARNING |
| 1821 | ///< 0x5 = AGESA_ERROR |
| 1822 | ///< 0x6 = AGESA_CRITICAL |
| 1823 | ///< 0x7 = AGESA_FATAL |
| 1824 | ///< |
| 1825 | OUT BOOLEAN ErrStatus[EsbEOL]; ///< Error Status bit Field |
| 1826 | ///< |
| 1827 | OUT BOOLEAN Status[SbEOL]; ///< Status bit Field |
| 1828 | ///< |
| 1829 | OUT UINT32 NodeMemSize; ///< Base[47:16], total DRAM size controlled by both DCT0 and DCT1 of this Node. |
| 1830 | ///< |
| 1831 | OUT UINT32 NodeSysBase; ///< Base[47:16] (system address) DRAM base address of this Node. |
| 1832 | ///< |
| 1833 | OUT UINT32 NodeHoleBase; ///< If not zero, Base[47:16] (system address) of dram hole for HW remapping. Dram hole exists on this Node |
| 1834 | ///< |
| 1835 | OUT UINT32 NodeSysLimit; ///< Base[47:16] (system address) DRAM limit address of this Node. |
| 1836 | ///< |
| 1837 | OUT UINT32 DimmPresent; ///< For each bit n 0..7, 1 = DIMM n is present. |
| 1838 | ///< DIMM# Select Signal |
| 1839 | ///< 0 MA0_CS_L[0, 1] |
| 1840 | ///< 1 MB0_CS_L[0, 1] |
| 1841 | ///< 2 MA1_CS_L[0, 1] |
| 1842 | ///< 3 MB1_CS_L[0, 1] |
| 1843 | ///< 4 MA2_CS_L[0, 1] |
| 1844 | ///< 5 MB2_CS_L[0, 1] |
| 1845 | ///< 6 MA3_CS_L[0, 1] |
| 1846 | ///< 7 MB3_CS_L[0, 1] |
| 1847 | ///< |
| 1848 | OUT UINT32 DimmValid; ///< For each bit n 0..7, 1 = DIMM n is valid and is / will be configured |
| 1849 | OUT UINT32 RegDimmPresent; ///< For each bit n 0..7, 1 = DIMM n is registered DIMM |
| 1850 | OUT UINT32 LrDimmPresent; ///< For each bit n 0..7, 1 = DIMM n is Load Reduced DIMM |
| 1851 | OUT UINT32 DimmEccPresent; ///< For each bit n 0..7, 1 = DIMM n is ECC capable. |
| 1852 | OUT UINT32 DimmParPresent; ///< For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable. |
| 1853 | ///< |
| 1854 | OUT UINT16 DimmTrainFail; ///< Bitmap showing which dimms failed training |
| 1855 | OUT UINT16 ChannelTrainFail; ///< Bitmap showing the channel information about failed Chip Selects |
| 1856 | ///< 0 in any bit field indicates Channel 0 |
| 1857 | ///< 1 in any bit field indicates Channel 1 |
| 1858 | OUT UINT8 Dct; ///< Need to be removed |
| 1859 | ///< DCT pointer |
| 1860 | OUT BOOLEAN GangedMode; ///< Ganged mode |
| 1861 | ///< 0 = disabled |
| 1862 | ///< 1 = enabled |
| 1863 | OUT CPU_LOGICAL_ID LogicalCpuid; ///< The logical CPUID of the node |
| 1864 | ///< |
| 1865 | OUT UINT16 HostBiosSrvc1; ///< UINT16 sized general purpose field for use by host BIOS. Scratch space. |
| 1866 | ///< |
| 1867 | OUT UINT32 HostBiosSrvc2; ///< UINT32 sized general purpose field for use by host BIOS. Scratch space. |
| 1868 | ///< |
| 1869 | OUT UINT8 MLoad; ///< Need to be removed |
| 1870 | ///< Number of devices loading MAA bus |
| 1871 | ///< |
| 1872 | OUT UINT8 MaxAsyncLat; ///< Legacy wrapper |
| 1873 | ///< |
| 1874 | OUT UINT8 ChbD3Rcvrdly; ///< Legacy wrapper |
| 1875 | ///< |
| 1876 | OUT UINT16 ChaMaxRdLat; ///< Max Read Latency (ns) for DCT 0 |
| 1877 | ///< |
| 1878 | OUT UINT8 ChbD3BcRcvrdly; ///< CHB DIMM 3 Check UINT8 Receiver Enable Delay |
| 1879 | |
| 1880 | OUT DCT_STRUCT *DctData; ///< Pointed to a dynamically allocated array of DCT_STRUCTs |
| 1881 | OUT UINT8 DctCount; ///< Number of DCTs per this Die |
| 1882 | OUT UINT8 Reserved[16]; ///< Reserved |
| 1883 | } DIE_STRUCT; |
| 1884 | |
| 1885 | /********************************************************************** |
| 1886 | * S3 Support structure |
| 1887 | **********************************************************************/ |
| 1888 | /// AmdInitResume, AmdS3LateRestore, and AmdS3Save param structure |
| 1889 | typedef struct { |
| 1890 | OUT UINT32 Signature; ///< "ASTR" for AMD Suspend-To-RAM |
| 1891 | OUT UINT16 Version; ///< S3 Params version number |
| 1892 | IN OUT UINT32 Flags; ///< Indicates operation |
| 1893 | IN OUT VOID *NvStorage; ///< Pointer to memory critical save state data |
| 1894 | IN OUT UINT32 NvStorageSize; ///< Size in bytes of the NvStorage region |
| 1895 | IN OUT VOID *VolatileStorage; ///< Pointer to remaining AMD save state data |
| 1896 | IN OUT UINT32 VolatileStorageSize; ///< Size in bytes of the VolatileStorage region |
| 1897 | } AMD_S3_PARAMS; |
| 1898 | |
| 1899 | ///=============================================================================== |
| 1900 | /// MEM_PARAMETER_STRUCT |
| 1901 | /// This data structure is used to pass wrapper parameters to the memory configuration code |
| 1902 | /// |
| 1903 | typedef struct _MEM_PARAMETER_STRUCT { |
| 1904 | |
| 1905 | // Basic (Return parameters) |
| 1906 | // (This section contains the outbound parameters from the memory init code) |
| 1907 | |
| 1908 | OUT BOOLEAN GStatus[GsbEOL]; ///< Global Status bitfield. |
| 1909 | ///< |
| 1910 | OUT UINT32 HoleBase; ///< If not zero Base[47:16] (system address) of sub 4GB dram hole for HW remapping. |
| 1911 | ///< |
| 1912 | OUT UINT32 Sub4GCacheTop; ///< If not zero, the 32-bit top of cacheable memory. |
| 1913 | ///< |
| 1914 | OUT UINT32 Sub1THoleBase; ///< If not zero Base[47:16] (system address) of sub 1TB dram hole. |
| 1915 | ///< |
| 1916 | OUT UINT32 SysLimit; ///< Limit[47:16] (system address). |
| 1917 | ///< |
| 1918 | OUT DIMM_VOLTAGE DDR3Voltage; ///< Find support voltage and send back to platform BIOS. |
| 1919 | ///< |
| 1920 | OUT UINT8 ExternalVrefValue; ///< Target reference voltage for external Vref for 2D training |
| 1921 | ///< |
| 1922 | OUT struct _MEM_DATA_STRUCT *MemData; ///< Access to global memory init data. |
| 1923 | |
| 1924 | // Advanced (Optional parameters) |
| 1925 | // Optional (all defaults values will be initialized by the |
| 1926 | // 'AmdMemInitDataStructDef' based on AMD defaults. It is up |
| 1927 | // to the IBV/OEM to change the defaults after initialization |
| 1928 | // but prior to the main entry to the memory code): |
| 1929 | |
| 1930 | // Memory Map/Mgt. |
| 1931 | |
| 1932 | IN UINT16 BottomIo; ///< Bottom of 32-bit IO space (8-bits). |
| 1933 | ///< NV_BOTTOM_IO[7:0]=Addr[31:24] |
| 1934 | ///< |
| 1935 | IN BOOLEAN MemHoleRemapping; ///< Memory Hole Remapping (1-bit). |
| 1936 | ///< FALSE = disable |
| 1937 | ///< TRUE = enable |
| 1938 | ///< |
| 1939 | IN BOOLEAN LimitMemoryToBelow1Tb;///< Limit memory address space to below 1 TB |
| 1940 | ///< FALSE = disable |
| 1941 | ///< TRUE = enable |
| 1942 | ///< |
| 1943 | ///< @BldCfgItem{BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB} |
| 1944 | |
| 1945 | |
| 1946 | // Dram Timing |
| 1947 | |
| 1948 | IN USER_MEMORY_TIMING_MODE UserTimingMode; ///< User Memclock Mode. |
| 1949 | ///< @BldCfgItem{BLDCFG_TIMING_MODE_SELECT} |
| 1950 | |
| 1951 | IN MEMORY_BUS_SPEED MemClockValue; ///< Memory Clock Value. |
| 1952 | ///< @BldCfgItem{BLDCFG_MEMORY_CLOCK_SELECT} |
| 1953 | |
| 1954 | |
| 1955 | // Dram Configuration |
| 1956 | |
| 1957 | IN BOOLEAN EnableBankIntlv; ///< Dram Bank (chip-select) Interleaving (1-bit). |
| 1958 | ///< - FALSE =disable (default) |
| 1959 | ///< - TRUE = enable |
| 1960 | ///< |
| 1961 | ///< @BldCfgItem{BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING} |
| 1962 | |
| 1963 | IN BOOLEAN EnableNodeIntlv; ///< Node Memory Interleaving (1-bit). |
| 1964 | ///< - FALSE = disable (default) |
| 1965 | ///< - TRUE = enable |
| 1966 | ///< |
| 1967 | ///< @BldCfgItem{BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING} |
| 1968 | |
| 1969 | IN BOOLEAN EnableChannelIntlv; ///< Channel Interleaving (1-bit). |
| 1970 | ///< - FALSE = disable (default) |
| 1971 | ///< - TRUE = enable |
| 1972 | ///< |
| 1973 | ///< @BldCfgItem{BLDCFG_MEMORY_CHANNEL_INTERLEAVING} |
| 1974 | // ECC |
| 1975 | |
| 1976 | IN BOOLEAN EnableEccFeature; ///< enable ECC error to go into MCE. |
| 1977 | ///< - FALSE = disable (default) |
| 1978 | ///< - TRUE = enable |
| 1979 | ///< |
| 1980 | ///< @BldCfgItem{BLDCFG_ENABLE_ECC_FEATURE} |
| 1981 | // Dram Power |
| 1982 | |
| 1983 | IN BOOLEAN EnablePowerDown; ///< CKE based power down mode (1-bit). |
| 1984 | ///< - FALSE =disable (default) |
| 1985 | ///< - TRUE =enable |
| 1986 | ///< |
| 1987 | ///< @BldCfgItem{BLDCFG_MEMORY_POWER_DOWN} |
| 1988 | |
| 1989 | // Online Spare |
| 1990 | |
| 1991 | IN BOOLEAN EnableOnLineSpareCtl; ///< Chip Select Spare Control bit 0. |
| 1992 | ///< - FALSE = disable Spare (default) |
| 1993 | ///< - TRUE = enable Spare |
| 1994 | ///< |
| 1995 | ///< @BldCfgItem{BLDCFG_ONLINE_SPARE} |
| 1996 | |
| 1997 | IN UINT8 *TableBasedAlterations; ///< Desired modifications to register settings. |
| 1998 | |
| 1999 | IN PSO_TABLE *PlatformMemoryConfiguration; |
| 2000 | ///< A table that contains platform specific settings. |
| 2001 | ///< For example, MemClk routing, the number of DIMM slots per channel, .... |
| 2002 | ///< AGESA initializes this pointer with DefaultPlatformMemoryConfiguration that |
| 2003 | ///< contains default conservative settings. Platform BIOS can either tweak |
| 2004 | ///< DefaultPlatformMemoryConfiguration or reassign this pointer to its own table. |
| 2005 | ///< |
| 2006 | IN BOOLEAN EnableParity; ///< Parity control. |
| 2007 | ///< - TRUE = enable |
| 2008 | ///< - FALSE = disable (default) |
| 2009 | ///< |
| 2010 | ///< @BldCfgItem{BLDCFG_MEMORY_PARITY_ENABLE} |
| 2011 | |
| 2012 | IN BOOLEAN EnableBankSwizzle; ///< BankSwizzle control. |
| 2013 | ///< - FALSE = disable |
| 2014 | ///< - TRUE = enable (default) |
| 2015 | ///< |
| 2016 | ///< @BldCfgItem{BLDCFG_BANK_SWIZZLE} |
| 2017 | |
| 2018 | ///< |
| 2019 | |
| 2020 | IN BOOLEAN EnableMemClr; ///< Memory Clear functionality control. |
| 2021 | ///< - FALSE = disable |
| 2022 | ///< - TRUE = enable (default) |
| 2023 | ///< |
| 2024 | |
| 2025 | // Uma Configuration |
| 2026 | |
| 2027 | IN UMA_MODE UmaMode; ///< Uma Mode |
| 2028 | ///< 0 = None |
| 2029 | ///< 1 = Specified |
| 2030 | ///< 2 = Auto |
| 2031 | IN OUT UINT32 UmaSize; ///< The size of shared graphics dram (16-bits) |
| 2032 | ///< NV_UMA_Size[31:0]=Addr[47:16] |
| 2033 | ///< |
| 2034 | OUT UINT32 UmaBase; ///< The allocated Uma base address (32-bits) |
| 2035 | ///< NV_UMA_Base[31:0]=Addr[47:16] |
| 2036 | ///< |
| 2037 | |
| 2038 | /// Memory Restore Feature |
| 2039 | |
| 2040 | IN BOOLEAN MemRestoreCtl; ///< Memory context restore control |
| 2041 | ///< FALSE = perform memory init as normal (AMD default) |
| 2042 | ///< TRUE = restore memory context and skip training. This requires |
| 2043 | ///< MemContext is valid before AmdInitPost |
| 2044 | ///< |
| 2045 | IN BOOLEAN SaveMemContextCtl; ///< Control switch to save memory context at the end of MemAuto |
| 2046 | ///< TRUE = AGESA will setup MemContext block before exit AmdInitPost |
| 2047 | ///< FALSE = AGESA will not setup MemContext block. Platform is |
| 2048 | ///< expected to call S3Save later in POST if it wants to |
| 2049 | ///< use memory context restore feature. |
| 2050 | ///< |
| 2051 | IN OUT AMD_S3_PARAMS MemContext; ///< Memory context block describes the data that platform needs to |
| 2052 | ///< save and restore for memory context restore feature to work. |
| 2053 | ///< It uses the subset of S3Save block to save/restore. Hence platform |
| 2054 | ///< may save only S3 block and uses it for both S3 resume and |
| 2055 | ///< memory context restore. |
| 2056 | ///< - If MemRestoreCtl is TRUE, platform needs to pass in MemContext |
| 2057 | ///< before AmdInitPost. |
| 2058 | ///< - If SaveMemContextCtl is TRUE, platform needs to save MemContext |
| 2059 | ///< right after AmdInitPost. |
| 2060 | ///< |
| 2061 | IN BOOLEAN ExternalVrefCtl; ///< Control the use of external Vref |
| 2062 | ///< TRUE = AGESA will use the function defined in "AGESA_EXTERNAL_VREF_CHANGE" in function list |
| 2063 | ///< to change the vref |
| 2064 | ///< FALSE = AGESA will will use the internal vref control. |
| 2065 | ///< @BldCfgItem{BLDCFG_ENABLE_EXTERNAL_VREF_FEATURE} |
| 2066 | ///< |
| 2067 | IN FORCE_TRAIN_MODE ForceTrainMode; ///< Training Mode |
| 2068 | ///< 0 = Force 1D Training for all configurations |
| 2069 | ///< 2 = Auto - AGESA will control 1D or 2D |
| 2070 | } MEM_PARAMETER_STRUCT; |
| 2071 | |
| 2072 | |
| 2073 | /// |
| 2074 | /// Function definition. |
| 2075 | /// This data structure passes function pointers to the memory configuration code. |
| 2076 | /// The wrapper can use this structure with customized versions. |
| 2077 | /// |
| 2078 | typedef struct _MEM_FUNCTION_STRUCT { |
| 2079 | |
| 2080 | // PUBLIC required Internal functions |
| 2081 | |
| 2082 | IN OUT BOOLEAN (*amdMemGetPsCfgU) ( VOID *pMemData); ///< Proc for Unbuffered DIMMs, platform specific |
| 2083 | IN OUT BOOLEAN (*amdMemGetPsCfgR) (VOID *pMemData); ///< Proc for Registered DIMMs, platform specific |
| 2084 | |
| 2085 | // PUBLIC optional functions |
| 2086 | |
| 2087 | IN OUT VOID (*amdMemEccInit) (VOID *pMemData); ///< NB proc for ECC feature |
| 2088 | IN OUT VOID (*amdMemChipSelectInterleaveInit) (VOID *pMemData); ///< NB proc for CS interleave feature |
| 2089 | IN OUT VOID (*amdMemDctInterleavingInit) (VOID *pMemData); ///< NB proc for Channel interleave feature |
| 2090 | IN OUT VOID (*amdMemMctInterleavingInit) (VOID *pMemData); ///< NB proc for Node interleave feature |
| 2091 | IN OUT VOID (*amdMemParallelTraining) (VOID *pMemData); ///< NB proc for parallel training feature |
| 2092 | IN OUT VOID (*amdMemEarlySampleSupport) (VOID *pMemData); ///< NB code for early sample support feature |
| 2093 | IN OUT VOID (*amdMemMultiPartInitSupport) (VOID *pMemData); ///< NB code for 'multi-part' |
| 2094 | IN OUT VOID (*amdMemOnlineSpareSupport) (VOID *pMemData); ///< NB code for On-Line Spare feature |
| 2095 | IN OUT VOID (*amdMemUDimmInit) (VOID *pMemData); ///< NB code for UDIMMs |
| 2096 | IN OUT VOID (*amdMemRDimmInit) (VOID *pMemData); ///< NB code for RDIMMs |
| 2097 | IN OUT VOID (*amdMemLrDimmInit) (VOID *pMemData); ///< NB code for LRDIMMs |
| 2098 | IN OUT UINT32 Reserved[100]; ///< Reserved for later function definition |
| 2099 | } MEM_FUNCTION_STRUCT; |
| 2100 | |
| 2101 | /// |
| 2102 | /// Socket Structure |
| 2103 | /// |
| 2104 | /// |
| 2105 | typedef struct _MEM_SOCKET_STRUCT { |
| 2106 | OUT VOID *ChannelPtr[MAX_CHANNELS_PER_SOCKET]; ///< Pointers to each channels training data |
| 2107 | |
| 2108 | OUT VOID *TimingsPtr[MAX_CHANNELS_PER_SOCKET]; ///< Pointers to each channels timing data |
| 2109 | } MEM_SOCKET_STRUCT; |
| 2110 | |
| 2111 | /// |
| 2112 | /// Contains all data relevant to Memory Initialization. |
| 2113 | /// |
| 2114 | typedef struct _MEM_DATA_STRUCT { |
| 2115 | IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header |
| 2116 | |
| 2117 | IN MEM_PARAMETER_STRUCT *ParameterListPtr; ///< List of input Parameters |
| 2118 | |
| 2119 | OUT MEM_FUNCTION_STRUCT FunctionList; ///< List of function Pointers |
| 2120 | |
| 2121 | IN OUT AGESA_STATUS (*GetPlatformCfg[MAX_PLATFORM_TYPES]) (struct _MEM_DATA_STRUCT *MemData, UINT8 SocketID, CH_DEF_STRUCT *CurrentChannel); ///< look-up platform info |
| 2122 | |
| 2123 | IN OUT BOOLEAN (*ErrorHandling)(struct _DIE_STRUCT *MCTPtr, UINT8 DCT, UINT16 ChipSelMask, AMD_CONFIG_PARAMS *StdHeader); ///< Error Handling |
| 2124 | |
| 2125 | |
| 2126 | OUT MEM_SOCKET_STRUCT SocketList[MAX_SOCKETS_SUPPORTED]; ///< Socket list for memory code. |
| 2127 | ///< SocketList is a shortcut for IBVs to retrieve training |
| 2128 | ///< and timing data for each channel indexed by socket/channel, |
| 2129 | ///< eliminating their need to parse die/dct/channel etc. |
| 2130 | ///< It contains pointers to the populated data structures for |
| 2131 | ///< each channel and skips the channel structures that are |
| 2132 | ///< unpopulated. In the case of channels sharing the same DCT, |
| 2133 | ///< the pTimings pointers will point to the same DCT Timing data. |
| 2134 | |
| 2135 | OUT DIE_STRUCT *DiesPerSystem; ///< Pointed to an array of DIE_STRUCTs |
| 2136 | OUT UINT8 DieCount; ///< Number of MCTs in the system. |
| 2137 | |
| 2138 | IN SPD_DEF_STRUCT *SpdDataStructure; ///< Pointer to SPD Data structure |
| 2139 | |
| 2140 | IN OUT struct _PLATFORM_CONFIGURATION *PlatFormConfig; ///< Platform profile/build option config structure |
| 2141 | |
| 2142 | IN OUT BOOLEAN IsFlowControlSupported; ///< Indicates if flow control is supported |
| 2143 | |
| 2144 | OUT UINT32 TscRate; ///< The rate at which the TSC increments in megahertz. |
| 2145 | |
| 2146 | } MEM_DATA_STRUCT; |
| 2147 | |
| 2148 | /// |
| 2149 | /// Uma Structure |
| 2150 | /// |
| 2151 | /// |
| 2152 | typedef struct _UMA_INFO { |
| 2153 | OUT UINT64 UmaBase; ///< UmaBase[63:0] = Addr[63:0] |
| 2154 | OUT UINT32 UmaSize; ///< UmaSize[31:0] = Addr[31:0] |
| 2155 | OUT UINT32 UmaAttributes; ///< Indicate the attribute of Uma |
| 2156 | OUT UINT8 UmaMode; ///< Indicate the mode of Uma |
| 2157 | OUT UINT16 MemClock; ///< Indicate memory running speed in MHz |
| 2158 | OUT UINT8 Reserved[3]; ///< Reserved for future usage |
| 2159 | } UMA_INFO; |
| 2160 | |
| 2161 | /// Bitfield for ID |
| 2162 | typedef struct { |
| 2163 | OUT UINT16 SocketId:8; ///< Socket ID |
| 2164 | OUT UINT16 ModuleId:8; ///< Module ID |
| 2165 | } ID_FIELD; |
| 2166 | /// |
| 2167 | /// Union for ID of socket and module that will be passed out in call out |
| 2168 | /// |
| 2169 | typedef union { |
| 2170 | OUT ID_FIELD IdField; ///< Bitfield for ID |
| 2171 | OUT UINT16 IdInformation; ///< ID information for call out |
| 2172 | } ID_INFO; |
| 2173 | |
| 2174 | // AGESA MEMORY ERRORS |
| 2175 | |
| 2176 | // AGESA_ALERT Memory Errors |
| 2177 | #define MEM_ALERT_USER_TMG_MODE_OVERRULED 0x04010000ul ///< TIMING_MODE_SPECIFIC is requested but |
| 2178 | ///< cannot be applied to current configurations. |
| 2179 | #define MEM_ALERT_ORG_MISMATCH_DIMM 0x04010100ul ///< DIMM organization miss-match |
| 2180 | #define MEM_ALERT_BK_INT_DIS 0x04010200ul ///< Bank interleaving disable for internal issue |
| 2181 | |
| 2182 | // AGESA_ERROR Memory Errors |
| 2183 | #define MEM_ERROR_NO_DQS_POS_RD_WINDOW 0x04010300ul ///< No DQS Position window for RD DQS |
| 2184 | #define MEM_ERROR_SMALL_DQS_POS_RD_WINDOW 0x04020300ul ///< Small DQS Position window for RD DQS |
| 2185 | #define MEM_ERROR_NO_DQS_POS_WR_WINDOW 0x04030300ul ///< No DQS Position window for WR DQS |
| 2186 | #define MEM_ERROR_SMALL_DQS_POS_WR_WINDOW 0x04040300ul ///< Small DQS Position window for WR DQS |
| 2187 | #define MEM_ERROR_DIMM_SPARING_NOT_ENABLED 0x04010500ul ///< DIMM sparing has not been enabled for an internal issues |
| 2188 | #define MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE 0x04050300ul ///< Receive Enable value is too large |
| 2189 | #define MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW 0x04060300ul ///< There is no DQS receiver enable window |
| 2190 | #define MEM_ERROR_DRAM_ENABLED_TIME_OUT 0x04010600ul ///< Time out when polling DramEnabled bit |
| 2191 | #define MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT 0x04010700ul ///< Time out when polling DctAccessDone bit |
| 2192 | #define MEM_ERROR_SEND_CTRL_WORD_TIME_OUT 0x04010800ul ///< Time out when polling SendCtrlWord bit |
| 2193 | #define MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT 0x04010900ul ///< Time out when polling PrefDramTrainMode bit |
| 2194 | #define MEM_ERROR_ENTER_SELF_REF_TIME_OUT 0x04010A00ul ///< Time out when polling EnterSelfRef bit |
| 2195 | #define MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT 0x04010B00ul ///< Time out when polling FreqChgInProg bit |
| 2196 | #define MEM_ERROR_EXIT_SELF_REF_TIME_OUT 0x04020A00ul ///< Time out when polling ExitSelfRef bit |
| 2197 | #define MEM_ERROR_SEND_MRS_CMD_TIME_OUT 0x04010C00ul ///< Time out when polling SendMrsCmd bit |
| 2198 | #define MEM_ERROR_SEND_ZQ_CMD_TIME_OUT 0x04010D00ul ///< Time out when polling SendZQCmd bit |
| 2199 | #define MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT 0x04010E00ul ///< Time out when polling DctExtraAccessDone bit |
| 2200 | #define MEM_ERROR_MEM_CLR_BUSY_TIME_OUT 0x04010F00ul ///< Time out when polling MemClrBusy bit |
| 2201 | #define MEM_ERROR_MEM_CLEARED_TIME_OUT 0x04020F00ul ///< Time out when polling MemCleared bit |
| 2202 | #define MEM_ERROR_FLUSH_WR_TIME_OUT 0x04011000ul ///< Time out when polling FlushWr bit |
| 2203 | #define MEM_ERROR_NBPSTATE_TRANSITION_TIME_OUT 0x04012600ul ///< Time out when polling CurNBPstate bit |
| 2204 | #define MEM_ERROR_MAX_LAT_NO_WINDOW 0x04070300ul ///< Fail to find pass during Max Rd Latency training |
| 2205 | #define MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL 0x04080300ul ///< Fail to launch training code on an AP |
| 2206 | #define MEM_ERROR_PARALLEL_TRAINING_TIME_OUT 0x04090300ul ///< Fail to finish parallel training |
| 2207 | #define MEM_ERROR_NO_ADDRESS_MAPPING 0x04011100ul ///< No address mapping found for a dimm |
| 2208 | #define MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT 0x040A0300ul ///< There is no DQS receiver enable window and the value is equal to the largest value |
| 2209 | #define MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE 0x040B0300ul ///< Receive Enable value is too large and is 1 less than limit |
| 2210 | #define MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR 0x04011200ul ///< SPD Checksum error for NV_SPDCHK_RESTRT |
| 2211 | #define MEM_ERROR_NO_CHIPSELECT 0x04011300ul ///< No chipselects found |
| 2212 | #define MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM 0x04011500ul ///< Unbuffered dimm is not supported at 333MHz |
| 2213 | #define MEM_ERROR_WL_PRE_OUT_OF_RANGE 0x040C0300ul ///< Returned PRE value during write levelizzation was out of range |
| 2214 | #define MEM_ERROR_LR_IBT_NOT_FOUND 0x04013500ul ///< No LR dimm IBT value is found |
| 2215 | #define MEM_ERROR_MR0_NOT_FOUND 0x04023500ul ///< No MR0 value is found |
| 2216 | #define MEM_ERROR_ODT_PATTERN_NOT_FOUND 0x04033500ul ///< No odt pattern value is found |
| 2217 | #define MEM_ERROR_RC2_IBT_NOT_FOUND 0x04043500ul ///< No RC2 IBT value is found |
| 2218 | #define MEM_ERROR_RC10_OP_SPEED_NOT_FOUND 0x04053500ul ///< No RC10 op speed is found |
| 2219 | #define MEM_ERROR_RTT_NOT_FOUND 0x04063500ul ///< No RTT value is found |
| 2220 | #define MEM_ERROR_P2D_NOT_FOUND 0x04073500ul ///< No 2D training config value is found |
| 2221 | #define MEM_ERROR_SAO_NOT_FOUND 0x04083500ul ///< No slow access mode, Address timing and Output driver compensation value is found |
| 2222 | #define MEM_ERROR_CLK_DIS_MAP_NOT_FOUND 0x04093500ul ///< No CLK disable map is found |
| 2223 | #define MEM_ERROR_CKE_TRI_MAP_NOT_FOUND 0x040A3500ul ///< No CKE tristate map is found |
| 2224 | #define MEM_ERROR_ODT_TRI_MAP_NOT_FOUND 0x040B3500ul ///< No ODT tristate map is found |
| 2225 | #define MEM_ERROR_CS_TRI_MAP_NOT_FOUND 0x040C3500ul ///< No CS tristate map is found |
| 2226 | #define MEM_ERROR_TRAINING_SEED_NOT_FOUND 0x040D3500ul ///< No training seed is found |
| 2227 | |
| 2228 | // AGESA_WARNING Memory Errors |
| 2229 | #define MEM_WARNING_UNSUPPORTED_QRDIMM 0x04011600ul ///< QR DIMMs detected but not supported |
| 2230 | #define MEM_WARNING_UNSUPPORTED_UDIMM 0x04021600ul ///< U DIMMs detected but not supported |
| 2231 | #define MEM_WARNING_UNSUPPORTED_SODIMM 0x04031600ul ///< SO-DIMMs detected but not supported |
| 2232 | #define MEM_WARNING_UNSUPPORTED_X4DIMM 0x04041600ul ///< x4 DIMMs detected but not supported |
| 2233 | #define MEM_WARNING_UNSUPPORTED_RDIMM 0x04051600ul ///< R DIMMs detected but not supported |
| 2234 | #define MEM_WARNING_UNSUPPORTED_LRDIMM 0x04061600ul ///< LR DIMMs detected but not supported |
| 2235 | #define MEM_WARNING_EMP_NOT_SUPPORTED 0x04011700ul ///< Processor is not capable for EMP |
| 2236 | #define MEM_WARNING_EMP_CONFLICT 0x04021700ul ///< EMP cannot be enabled if channel interleaving, |
| 2237 | #define MEM_WARNING_EMP_NOT_ENABLED 0x04031700ul ///< Memory size is not power of two. |
| 2238 | #define MEM_WARNING_ECC_DIS 0x04041700ul ///< ECC has been disabled as a result of an internal issue |
| 2239 | #define MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED 0x04011800ul ///< Performance has been enabled, but battery life is preferred. |
| 2240 | ///< bank interleaving, or bank swizzle is enabled. |
| 2241 | #define MEM_WARNING_NO_SPDTRC_FOUND 0x04011900ul ///< No Trc timing value found in SPD of a dimm. |
| 2242 | #define MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED 0x04012000ul ///< Node Interleaveing Requested, but could not be enabled |
| 2243 | #define MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED 0x04012100ul ///< Channel Interleaveing Requested, but could not be enabled |
| 2244 | #define MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED 0x04012200ul ///< Bank Interleaveing Requested, but could not be enabled |
| 2245 | #define MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED 0x04012300ul ///< Voltage 1.35 determined, but could not be supported |
| 2246 | #define MEM_WARNING_INITIAL_DDR3VOLT_NONZERO 0x04012400ul ///< DDR3 voltage initial value is not 0 |
| 2247 | #define MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO 0x04012500ul ///< Cannot find a commonly supported VDDIO |
| 2248 | |
| 2249 | // AGESA_FATAL Memory Errors |
| 2250 | #define MEM_ERROR_MINIMUM_MODE 0x04011A00ul ///< Running in minimum mode |
| 2251 | #define MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM 0x04011B00ul ///< DIMM modules are miss-matched |
| 2252 | #define MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM 0x04011C00ul ///< No DIMMs have been found |
| 2253 | #define MEM_ERROR_MISMATCH_DIMM_CLOCKS 0x04011D00ul ///< DIMM clocks miss-matched |
| 2254 | #define MEM_ERROR_NO_CYC_TIME 0x04011E00ul ///< No cycle time found |
| 2255 | #define MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS 0x04011F00ul ///< Heap allocation error with dynamic storing of trained timings |
| 2256 | #define MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs 0x04021F00ul ///< Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT |
| 2257 | #define MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV 0x04031F00ul ///< Heap allocation error with REMOTE_TRAINING_ENV |
| 2258 | #define MEM_ERROR_HEAP_ALLOCATE_FOR_SPD 0x04041F00ul ///< Heap allocation error for SPD data |
| 2259 | #define MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA 0x04051F00ul ///< Heap allocation error for RECEIVED_DATA during parallel training |
| 2260 | #define MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS 0x04061F00ul ///< Heap allocation error for S3 "SPECIAL_CASE_REGISTER" |
| 2261 | #define MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA 0x04071F00ul ///< Heap allocation error for Training Data |
| 2262 | #define MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK 0x04081F00ul ///< Heap allocation error for DIMM Identify "MEM_NB_BLOCK |
| 2263 | #define MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM 0x04022300ul ///< No Constructor for DIMM Identify |
| 2264 | #define MEM_ERROR_VDDIO_UNSUPPORTED 0x04022500ul ///< VDDIO of the dimms on the board is not supported |
| 2265 | #define MEM_ERROR_HEAP_ALLOCATE_FOR_2D 0x040B1F00ul ///< Heap allocation error for 2D training data |
| 2266 | #define MEM_ERROR_HEAP_DEALLOCATE_FOR_2D 0x040C1F00ul ///< Heap de-allocation error for 2D training data |
| 2267 | |
| 2268 | // AGESA_CRITICAL Memory Errors |
| 2269 | #define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3 0x04091F00ul ///< Heap allocation error for DMI table for DDR3 |
| 2270 | #define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2 0x040A1F00ul ///< Heap allocation error for DMI table for DDR2 |
| 2271 | #define MEM_ERROR_UNSUPPORTED_DIMM_CONFIG 0x04011400ul ///< Dimm population is not supported |
| 2272 | #define MEM_ERROR_HEAP_ALLOCATE_FOR_CRAT_MEM_AFFINITY 0x040D1F00ul ///< Heap allocation error for CRAT memory affinity info |
| 2273 | |
| 2274 | |
| 2275 | |
| 2276 | /*---------------------------------------------------------------------------- |
| 2277 | * |
| 2278 | * END OF MEMORY-SPECIFIC DATA STRUCTURES |
| 2279 | * |
| 2280 | *---------------------------------------------------------------------------- |
| 2281 | */ |
| 2282 | |
| 2283 | |
| 2284 | |
| 2285 | |
| 2286 | /*---------------------------------------------------------------------------- |
| 2287 | * |
| 2288 | * CPU RELATED DEFINITIONS |
| 2289 | * |
| 2290 | *---------------------------------------------------------------------------- |
| 2291 | */ |
| 2292 | |
| 2293 | // CPU Event definitions. |
| 2294 | |
| 2295 | // Defines used to filter CPU events based on functional blocks |
| 2296 | #define CPU_EVENT_PM_EVENT_MASK 0xFF00FF00ul |
| 2297 | #define CPU_EVENT_PM_EVENT_CLASS 0x08000400ul |
| 2298 | |
| 2299 | //================================================================ |
| 2300 | // CPU General events |
| 2301 | // Heap allocation (AppFunction = 01h) |
| 2302 | #define CPU_ERROR_HEAP_BUFFER_IS_NOT_PRESENT 0x08000100ul |
| 2303 | #define CPU_ERROR_HEAP_IS_ALREADY_INITIALIZED 0x08010100ul |
| 2304 | #define CPU_ERROR_HEAP_IS_FULL 0x08020100ul |
| 2305 | #define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED 0x08030100ul |
| 2306 | #define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT 0x08040100ul |
| 2307 | // BrandId (AppFunction = 02h) |
| 2308 | #define CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE 0x08000200ul |
| 2309 | // Micro code patch (AppFunction = 03h) |
| 2310 | #define CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED 0x08000300ul |
| 2311 | // Power management (AppFunction = 04h) |
| 2312 | #define CPU_EVENT_PM_PSTATE_OVERCURRENT 0x08000400ul |
| 2313 | #define CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT 0x08010400ul |
| 2314 | #define CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE 0x08020400ul |
| 2315 | #define CPU_ERROR_PM_NB_PSTATE_MISMATCH 0x08030400ul |
| 2316 | // Other CPU events (AppFunction = 05h) |
| 2317 | #define CPU_EVENT_BIST_ERROR 0x08000500ul |
| 2318 | #define CPU_EVENT_UNKNOWN_PROCESSOR_FAMILY 0x08010500ul |
| 2319 | #define CPU_EVENT_STACK_REENTRY 0x08020500ul |
| 2320 | #define CPU_EVENT_CORE_NOT_IDENTIFIED 0x08030500ul |
| 2321 | |
| 2322 | //================================================================= |
| 2323 | // CPU Feature events |
| 2324 | // Execution cache (AppFunction = 21h) |
| 2325 | // AGESA_CACHE_SIZE_REDUCED 2101 |
| 2326 | // AGESA_CACHE_REGIONS_ACROSS_1MB 2102 |
| 2327 | // AGESA_CACHE_REGIONS_ACROSS_4GB 2103 |
| 2328 | // AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY 2104 |
| 2329 | // AGESA_CACHE_START_ADDRESS_LESS_D0000 2105 |
| 2330 | // AGESA_THREE_CACHE_REGIONS_ABOVE_1MB 2106 |
| 2331 | // AGESA_DEALLOCATE_CACHE_REGIONS 2107 |
| 2332 | #define CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR 0x08002100ul |
| 2333 | // Core Leveling (AppFunction = 22h) |
| 2334 | #define CPU_WARNING_ADJUSTED_LEVELING_MODE 0x08002200ul |
| 2335 | // HT Assist (AppFunction = 23h) |
| 2336 | #define CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG 0x08002300ul |
| 2337 | |
| 2338 | // CPU Build Configuration structures and definitions |
| 2339 | |
| 2340 | /// Build Configuration structure for BLDCFG_AP_MTRR_SETTINGS |
| 2341 | typedef struct { |
| 2342 | IN UINT32 MsrAddr; ///< Fixed-Sized MTRR address |
| 2343 | IN UINT64 MsrData; ///< MTRR Settings |
| 2344 | } AP_MTRR_SETTINGS; |
| 2345 | |
| 2346 | #define AMD_AP_MTRR_FIX64k_00000 0x00000250ul |
| 2347 | #define AMD_AP_MTRR_FIX16k_80000 0x00000258ul |
| 2348 | #define AMD_AP_MTRR_FIX16k_A0000 0x00000259ul |
| 2349 | #define AMD_AP_MTRR_FIX4k_C0000 0x00000268ul |
| 2350 | #define AMD_AP_MTRR_FIX4k_C8000 0x00000269ul |
| 2351 | #define AMD_AP_MTRR_FIX4k_D0000 0x0000026Aul |
| 2352 | #define AMD_AP_MTRR_FIX4k_D8000 0x0000026Bul |
| 2353 | #define AMD_AP_MTRR_FIX4k_E0000 0x0000026Cul |
| 2354 | #define AMD_AP_MTRR_FIX4k_E8000 0x0000026Dul |
| 2355 | #define AMD_AP_MTRR_FIX4k_F0000 0x0000026Eul |
| 2356 | #define AMD_AP_MTRR_FIX4k_F8000 0x0000026Ful |
| 2357 | #define CPU_LIST_TERMINAL 0xFFFFFFFFul |
| 2358 | |
| 2359 | /// Data structure for the Mapping Item between Unified ID for IDS Setup Option |
| 2360 | /// and the option value. |
| 2361 | /// |
| 2362 | typedef struct { |
| 2363 | IN UINT16 IdsNvId; ///< Unified ID for IDS Setup Option. |
| 2364 | OUT UINT16 IdsNvValue; ///< The value of IDS Setup Option. |
| 2365 | } IDS_NV_ITEM; |
| 2366 | |
| 2367 | /// Data Structure for IDS CallOut Function |
| 2368 | typedef struct { |
| 2369 | IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header |
| 2370 | IN IDS_NV_ITEM *IdsNvPtr; ///< Memory Pointer of IDS NV Table |
| 2371 | IN OUT UINTN Reserved; ///< reserved |
| 2372 | } IDS_CALLOUT_STRUCT; |
| 2373 | |
| 2374 | /************************************************************************ |
| 2375 | * |
| 2376 | * AGESA interface Call-Out function parameter structures |
| 2377 | * |
| 2378 | ***********************************************************************/ |
| 2379 | |
| 2380 | /// Parameters structure for interface call-out AgesaAllocateBuffer |
| 2381 | typedef struct { |
| 2382 | IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header |
| 2383 | IN OUT UINT32 BufferLength; ///< Size of buffer to allocate |
| 2384 | IN UINT32 BufferHandle; ///< Identifier or name for the buffer |
| 2385 | OUT VOID *BufferPointer; ///< location of the created buffer |
| 2386 | } AGESA_BUFFER_PARAMS; |
| 2387 | |
| 2388 | /// Parameters structure for interface call-out AgesaRunCodeOnAp |
| 2389 | typedef struct { |
| 2390 | IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header |
| 2391 | IN UINT32 FunctionNumber; ///< Index of the procedure to execute |
| 2392 | IN VOID *RelatedDataBlock; ///< Location of data structure the procedure will use |
| 2393 | IN UINT32 RelatedBlockLength; ///< Size of the related data block |
| 2394 | } AP_EXE_PARAMS; |
| 2395 | |
| 2396 | /// Parameters structure for the interface call-out AgesaReadSpd & AgesaReadSpdRecovery |
| 2397 | typedef struct { |
| 2398 | IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header |
| 2399 | IN UINT8 SocketId; ///< Address of SPD - socket ID |
| 2400 | IN UINT8 MemChannelId; ///< Address of SPD - memory channel ID |
| 2401 | IN UINT8 DimmId; ///< Address of SPD - DIMM ID |
| 2402 | IN OUT UINT8 *Buffer; ///< Location where to place the SPD content |
| 2403 | IN OUT MEM_DATA_STRUCT *MemData; ///< Location of the MemData structure, for reference |
| 2404 | } AGESA_READ_SPD_PARAMS; |
| 2405 | |
| 2406 | /// Buffer Handles |
| 2407 | typedef enum { |
| 2408 | AMD_DMI_INFO_BUFFER_HANDLE = 0x000D000, ///< Assign 0x000D000 buffer handle to DMI function |
| 2409 | AMD_PSTATE_DATA_BUFFER_HANDLE, ///< Assign 0x000D001 buffer handle to Pstate data |
| 2410 | AMD_PSTATE_ACPI_BUFFER_HANDLE, ///< Assign 0x000D002 buffer handle to Pstate table |
| 2411 | AMD_BRAND_ID_BUFFER_HANDLE, ///< Assign 0x000D003 buffer handle to Brand ID |
| 2412 | AMD_ACPI_SLIT_BUFFER_HANDLE, ///< Assign 0x000D004 buffer handle to SLIT function |
| 2413 | AMD_SRAT_INFO_BUFFER_HANDLE, ///< Assign 0x000D005 buffer handle to SRAT function |
| 2414 | AMD_WHEA_BUFFER_HANDLE, ///< Assign 0x000D006 buffer handle to WHEA function |
| 2415 | AMD_S3_INFO_BUFFER_HANDLE, ///< Assign 0x000D007 buffer handle to S3 function |
| 2416 | AMD_S3_NB_INFO_BUFFER_HANDLE, ///< Assign 0x000D008 buffer handle to S3 NB device info |
| 2417 | AMD_ACPI_ALIB_BUFFER_HANDLE, ///< Assign 0x000D009 buffer handle to ALIB SSDT table |
| 2418 | AMD_ACPI_IVRS_BUFFER_HANDLE, ///< Assign 0x000D00A buffer handle to IOMMU IVRS table |
| 2419 | AMD_CRAT_INFO_BUFFER_HANDLE, ///< Assign 0x000D00B buffer handle to CRAT function |
| 2420 | AMD_ACPI_CDIT_BUFFER_HANDLE ///< Assign 0x000D00C buffer handle to CDIT function |
| 2421 | } AMD_BUFFER_HANDLE; |
| 2422 | |
| 2423 | |
| 2424 | /************************************************************************ |
| 2425 | * |
| 2426 | * AGESA interface Call-Out function prototypes |
| 2427 | * |
| 2428 | ***********************************************************************/ |
| 2429 | |
| 2430 | VOID |
| 2431 | AgesaDoReset ( |
| 2432 | IN UINTN ResetType, |
| 2433 | IN OUT AMD_CONFIG_PARAMS *StdHeader |
| 2434 | ); |
| 2435 | |
| 2436 | AGESA_STATUS |
| 2437 | AgesaAllocateBuffer ( |
| 2438 | IN UINTN FcnData, |
| 2439 | IN OUT AGESA_BUFFER_PARAMS *AllocParams |
| 2440 | ); |
| 2441 | |
| 2442 | AGESA_STATUS |
| 2443 | AgesaDeallocateBuffer ( |
| 2444 | IN UINTN FcnData, |
| 2445 | IN OUT AGESA_BUFFER_PARAMS *DeallocParams |
| 2446 | ); |
| 2447 | |
| 2448 | AGESA_STATUS |
| 2449 | AgesaLocateBuffer ( |
| 2450 | IN UINTN FcnData, |
| 2451 | IN OUT AGESA_BUFFER_PARAMS *LocateParams |
| 2452 | ); |
| 2453 | |
| 2454 | AGESA_STATUS |
| 2455 | AgesaReadSpd ( |
| 2456 | IN UINTN FcnData, |
| 2457 | IN OUT AGESA_READ_SPD_PARAMS *ReadSpd |
| 2458 | ); |
| 2459 | |
| 2460 | AGESA_STATUS |
| 2461 | AgesaReadSpdRecovery ( |
| 2462 | IN UINTN FcnData, |
| 2463 | IN OUT AGESA_READ_SPD_PARAMS *ReadSpd |
| 2464 | ); |
| 2465 | |
| 2466 | AGESA_STATUS |
| 2467 | AgesaHookBeforeDramInitRecovery ( |
| 2468 | IN UINTN FcnData, |
| 2469 | IN OUT MEM_DATA_STRUCT *MemData |
| 2470 | ); |
| 2471 | |
| 2472 | AGESA_STATUS |
| 2473 | AgesaRunFcnOnAp ( |
| 2474 | IN UINTN ApicIdOfCore, |
| 2475 | IN AP_EXE_PARAMS *LaunchApParams |
| 2476 | ); |
| 2477 | |
| 2478 | AGESA_STATUS |
| 2479 | AgesaHookBeforeDramInit ( |
| 2480 | IN UINTN SocketIdModuleId, |
| 2481 | IN OUT MEM_DATA_STRUCT *MemData |
| 2482 | ); |
| 2483 | |
| 2484 | AGESA_STATUS |
| 2485 | AgesaHookBeforeDQSTraining ( |
| 2486 | IN UINTN SocketIdModuleId, |
| 2487 | IN OUT MEM_DATA_STRUCT *MemData |
| 2488 | ); |
| 2489 | |
| 2490 | AGESA_STATUS |
| 2491 | AgesaHookBeforeExitSelfRefresh ( |
| 2492 | IN UINTN FcnData, |
| 2493 | IN OUT MEM_DATA_STRUCT *MemData |
| 2494 | ); |
| 2495 | |
| 2496 | AGESA_STATUS |
| 2497 | AgesaPcieSlotResetControl ( |
| 2498 | IN UINTN FcnData, |
| 2499 | IN PCIe_SLOT_RESET_INFO *ResetInfo |
| 2500 | ); |
| 2501 | |
| 2502 | AGESA_STATUS |
| 2503 | AgesaGetVbiosImage ( |
| 2504 | IN UINTN FcnData, |
| 2505 | IN OUT GFX_VBIOS_IMAGE_INFO *VbiosImageInfo |
| 2506 | ); |
| 2507 | |
| 2508 | AGESA_STATUS |
| 2509 | AgesaFchOemCallout ( |
| 2510 | IN VOID *FchData |
| 2511 | ); |
| 2512 | |
| 2513 | AGESA_STATUS |
| 2514 | excel331 ( |
| 2515 | IN UINTN SocketIdModuleId, |
| 2516 | IN OUT MEM_DATA_STRUCT *MemData |
| 2517 | ); |
| 2518 | |
| 2519 | AGESA_STATUS |
| 2520 | AgesaGetIdsData ( |
| 2521 | IN UINTN Data, |
| 2522 | IN OUT IDS_CALLOUT_STRUCT *IdsCalloutData |
| 2523 | ); |
| 2524 | /************************************************************************ |
| 2525 | * |
| 2526 | * AGESA interface structure definition and function prototypes |
| 2527 | * |
| 2528 | ***********************************************************************/ |
| 2529 | |
| 2530 | /********************************************************************** |
| 2531 | * Platform Configuration: The parameters in boot branch function |
| 2532 | **********************************************************************/ |
| 2533 | |
| 2534 | /// The possible platform control flow settings. |
| 2535 | typedef enum { |
| 2536 | Nfcm, ///< Normal Flow Control Mode. |
| 2537 | UmaDr, ///< UMA using Display Refresh flow control. |
| 2538 | UmaIfcm, ///< UMA using Isochronous Flow Control. |
| 2539 | Ifcm, ///< Isochronous Flow Control Mode (other than for UMA). |
| 2540 | Iommu, ///< An IOMMU is in use in the system. |
| 2541 | MaxControlFlow ///< Not a control flow mode, use for limit checking. |
| 2542 | } PLATFORM_CONTROL_FLOW; |
| 2543 | |
| 2544 | /// Platform Deemphasis Levels. |
| 2545 | /// |
| 2546 | /// The deemphasis level is set for the receiver, based on link characterization. The DCV level is |
| 2547 | /// set based on the level of the far transmitter. |
| 2548 | typedef enum { |
| 2549 | DeemphasisLevelNone, ///< No Deemphasis. |
| 2550 | DeemphasisLevelMinus3, ///< Minus 3 db deemphasis. |
| 2551 | DeemphasisLevelMinus6, ///< Minus 6 db deemphasis. |
| 2552 | DeemphasisLevelMinus8, ///< Minus 8 db deemphasis. |
| 2553 | DeemphasisLevelMinus11, ///< Minus 11 db deemphasis. |
| 2554 | DeemphasisLevelMinus11pre8, ///< Minus 11, Minus 8 precursor db deemphasis. |
| 2555 | DcvLevelNone = 16, ///< No DCV Deemphasis. |
| 2556 | DcvLevelMinus2, ///< Minus 2 db DCV deemphasis. |
| 2557 | DcvLevelMinus3, ///< Minus 3 db DCV deemphasis. |
| 2558 | DcvLevelMinus5, ///< Minus 5 db DCV deemphasis. |
| 2559 | DcvLevelMinus6, ///< Minus 6 db DCV deemphasis. |
| 2560 | DcvLevelMinus7, ///< Minus 7 db DCV deemphasis. |
| 2561 | DcvLevelMinus8, ///< Minus 8 db DCV deemphasis. |
| 2562 | DcvLevelMinus9, ///< Minus 9 db DCV deemphasis. |
| 2563 | DcvLevelMinus11, ///< Minus 11 db DCV deemphasis. |
| 2564 | MaxPlatformDeemphasisLevel ///< Not a deemphasis level, use for limit checking. |
| 2565 | } PLATFORM_DEEMPHASIS_LEVEL; |
| 2566 | |
| 2567 | /// Provide Deemphasis Levels for HT Links. |
| 2568 | /// |
| 2569 | /// For each CPU to CPU or CPU to IO device HT link, the list of Deemphasis Levels will |
| 2570 | /// be checked for a match. The item matches for a Socket, Link if the link frequency is |
| 2571 | /// is in the inclusive range HighFreq:LoFreq. |
| 2572 | /// AGESA does not set deemphasis in IO devices, only in processors. |
| 2573 | |
| 2574 | typedef struct { |
| 2575 | // Match fields |
| 2576 | IN UINT8 Socket; ///< One Socket on which this Link is located |
| 2577 | IN UINT8 Link; ///< The Link on this Processor. |
| 2578 | IN UINT8 LoFreq; ///< If the link is set to this frequency or greater, apply these levels, and |
| 2579 | IN UINT8 HighFreq; ///< If the link is set to this frequency or less, apply these levels. |
| 2580 | // Value fields |
| 2581 | IN PLATFORM_DEEMPHASIS_LEVEL ReceiverDeemphasis; ///< The deemphasis level for this link |
| 2582 | IN PLATFORM_DEEMPHASIS_LEVEL DcvDeemphasis; ///< The DCV, or far transmitter deemphasis level. |
| 2583 | } CPU_HT_DEEMPHASIS_LEVEL; |
| 2584 | |
| 2585 | |
| 2586 | /// The possible hardware prefetch mode settings. |
| 2587 | typedef enum { |
| 2588 | HARDWARE_PREFETCHER_AUTO, ///< Use the recommended setting for the processor. In most cases, the recommended setting is enabled. |
| 2589 | DISABLE_L1_PREFETCHER, ///< Use the recommended settings for the hardware prefetcher, but disable L1 prefetching. |
| 2590 | DISABLE_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES, ///< Use the recommended setting for the hardware prefetcher, but disable training on software prefetches. |
| 2591 | DISABLE_L1_PREFETCHER_AND_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES, ///< Use the recommended settings for the hardware prefetcher, but disable both the L1 prefetcher and training on software prefetches. |
| 2592 | DISABLE_HARDWARE_PREFETCH, ///< Disable hardware prefetching. |
| 2593 | MAX_HARDWARE_PREFETCH_MODE ///< Not a hardware prefetch mode, use for limit checking. |
| 2594 | } HARDWARE_PREFETCH_MODE; |
| 2595 | |
| 2596 | /// The possible software prefetch mode settings. |
| 2597 | typedef enum { |
| 2598 | SOFTWARE_PREFETCHES_AUTO, ///< Use the recommended setting for the processor. In most cases, the recommended setting is enabled. |
| 2599 | DISABLE_SOFTWARE_PREFETCHES, ///< Disable software prefetches (convert software prefetch instructions to NOP). |
| 2600 | MAX_SOFTWARE_PREFETCH_MODE ///< Not a software prefetch mode, use for limit checking. |
| 2601 | } SOFTWARE_PREFETCH_MODE; |
| 2602 | |
| 2603 | /// Advanced performance tunings, prefetchers. |
| 2604 | /// These settings provide for performance tuning to optimize for specific workloads. |
| 2605 | typedef struct { |
| 2606 | IN HARDWARE_PREFETCH_MODE HardwarePrefetchMode; ///< This value provides for advanced performance tuning by controlling the hardware prefetcher setting. |
| 2607 | IN SOFTWARE_PREFETCH_MODE SoftwarePrefetchMode; ///< This value provides for advanced performance tuning by controlling the software prefetch instructions. |
| 2608 | IN DRAM_PREFETCH_MODE DramPrefetchMode; ///< This value provides for advanced performance tuning by controlling the DRAM prefetcher setting. |
| 2609 | } ADVANCED_PERFORMANCE_PROFILE; |
| 2610 | |
| 2611 | /// The possible platform power policy settings. |
| 2612 | typedef enum { |
| 2613 | Performance, ///< Optimize for performance. |
| 2614 | BatteryLife, ///< Optimize for battery life. |
| 2615 | MaxPowerPolicy ///< Not a power policy mode, use for limit checking. |
| 2616 | } PLATFORM_POWER_POLICY; |
| 2617 | |
| 2618 | /// Platform performance settings for optimized settings. |
| 2619 | /// Several configuration settings for the processor depend upon other parts and |
| 2620 | /// general designer choices for the system. The determination of these data points |
| 2621 | /// is not standard for all platforms, so the host environment needs to provide these |
| 2622 | /// to specify how the system is to be configured. |
| 2623 | typedef struct { |
| 2624 | IN PLATFORM_CONTROL_FLOW PlatformControlFlowMode; ///< The platform's control flow mode for optimum platform performance. |
| 2625 | ///< @BldCfgItem{BLDCFG_PLATFORM_CONTROL_FLOW_MODE} |
| 2626 | IN BOOLEAN UseHtAssist; ///< HyperTransport link traffic optimization. |
| 2627 | ///< @BldCfgItem{BLDCFG_USE_HT_ASSIST} |
| 2628 | IN BOOLEAN UseAtmMode; ///< HyperTransport link traffic optimization. |
| 2629 | ///< @BldCfgItem{BLDCFG_USE_ATM_MODE} |
| 2630 | IN BOOLEAN Use32ByteRefresh; ///< Display Refresh traffic generates 32 byte requests. |
| 2631 | ///< @BldCfgItem{BLDCFG_USE_32_BYTE_REFRESH} |
| 2632 | IN BOOLEAN UseVariableMctIsocPriority; ///< The Memory controller will be set to Variable Isoc Priority. |
| 2633 | ///< @BldCfgItem{BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY} |
| 2634 | IN ADVANCED_PERFORMANCE_PROFILE AdvancedPerformanceProfile; ///< The advanced platform performance settings. |
| 2635 | IN PLATFORM_POWER_POLICY PlatformPowerPolicy; ///< The platform's desired power policy |
| 2636 | ///< @BldCfgItem{BLDCFG_PLATFORM_POWER_POLICY_MODE} |
| 2637 | } PERFORMANCE_PROFILE; |
| 2638 | |
| 2639 | /// Platform settings that describe the voltage regulator modules of the system. |
| 2640 | /// Many power management settings are dependent upon the characteristics of the |
| 2641 | /// on-board voltage regulator module (VRM). The host environment needs to provide |
| 2642 | /// these to specify how the system is to be configured. |
| 2643 | typedef struct { |
| 2644 | IN UINT32 CurrentLimit; ///< Vrm Current Limit. |
| 2645 | ///< @BldCfgItem{BLDCFG_VRM_CURRENT_LIMIT} |
| 2646 | ///< @BldCfgItem{BLDCFG_VRM_NB_CURRENT_LIMIT} |
| 2647 | IN UINT32 LowPowerThreshold; ///< Vrm Low Power Threshold. |
| 2648 | ///< @BldCfgItem{BLDCFG_VRM_LOW_POWER_THRESHOLD} |
| 2649 | ///< @BldCfgItem{BLDCFG_VRM_NB_LOW_POWER_THRESHOLD} |
| 2650 | IN UINT32 SlewRate; ///< Vrm Slew Rate. |
| 2651 | ///< @BldCfgItem{BLDCFG_VRM_SLEW_RATE} |
| 2652 | ///< @BldCfgItem{BLDCFG_VRM_NB_SLEW_RATE} |
| 2653 | IN UINT32 AdditionalDelay; ///< Vrm Additional Delay. |
| 2654 | ///< @BldCfgItem{BLDCFG_VRM_ADDITIONAL_DELAY} |
| 2655 | ///< @BldCfgItem{BLDCFG_VRM_NB_ADDITIONAL_DELAY} |
| 2656 | IN BOOLEAN HiSpeedEnable; ///< Select high speed VRM. |
| 2657 | ///< @BldCfgItem{BLDCFG_VRM_HIGH_SPEED_ENABLE} |
| 2658 | ///< @BldCfgItem{BLDCFG_VRM_NB_HIGH_SPEED_ENABLE} |
| 2659 | IN UINT32 InrushCurrentLimit; ///< Vrm Inrush Current Limit. |
| 2660 | ///< @BldCfgItem{BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT} |
| 2661 | ///< @BldCfgItem{BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT} |
| 2662 | IN UINT32 SviOcpLevel; ///< SVI OCP Level. |
| 2663 | ///< @BldCfgItem{BLDCFG_VRM_SVI_OCP_LEVEL} |
| 2664 | ///< @BldCfgItem{BLDCFG_VRM_NB_SVI_OCP_LEVEL} |
| 2665 | } PLATFORM_VRM_CONFIGURATION; |
| 2666 | |
| 2667 | /// The VRM types to characterize. |
| 2668 | typedef enum { |
| 2669 | CoreVrm, ///< VDD plane. |
| 2670 | NbVrm, ///< VDDNB plane. |
| 2671 | MaxVrmType ///< Not a valid VRM type, use for limit checking. |
| 2672 | } PLATFORM_VRM_TYPE; |
| 2673 | |
| 2674 | |
| 2675 | /// FCH Platform Configuration Policy |
| 2676 | typedef struct { |
| 2677 | IN UINT16 CfgSmbus0BaseAddress; ///< SMBUS0 Controller Base Address |
| 2678 | IN UINT16 CfgSmbus1BaseAddress; ///< SMBUS1 Controller Base Address |
| 2679 | IN UINT16 CfgSioPmeBaseAddress; ///< I/O base address for LPC I/O target range |
| 2680 | IN UINT16 CfgAcpiPm1EvtBlkAddr; ///< I/O base address of ACPI power management Event Block |
| 2681 | IN UINT16 CfgAcpiPm1CntBlkAddr; ///< I/O base address of ACPI power management Control Block |
| 2682 | IN UINT16 CfgAcpiPmTmrBlkAddr; ///< I/O base address of ACPI power management Timer Block |
| 2683 | IN UINT16 CfgCpuControlBlkAddr; ///< I/O base address of ACPI power management CPU Control Block |
| 2684 | IN UINT16 CfgAcpiGpe0BlkAddr; ///< I/O base address of ACPI power management General Purpose Event Block |
| 2685 | IN UINT16 CfgSmiCmdPortAddr; ///< I/O base address of ACPI SMI Command Block |
| 2686 | IN UINT16 CfgAcpiPmaCntBlkAddr; ///< I/O base address of ACPI power management additional control block |
| 2687 | IN UINT32 CfgGecShadowRomBase; ///< 32-bit base address to the GEC shadow ROM |
| 2688 | IN UINT32 CfgWatchDogTimerBase; ///< Watchdog Timer base address |
| 2689 | IN UINT32 CfgSpiRomBaseAddress; ///< Base address for the SPI ROM controller |
| 2690 | IN UINT32 CfgHpetBaseAddress; ///< HPET MMIO base address |
| 2691 | IN UINT32 CfgAzaliaSsid; ///< Subsystem ID of HD Audio controller |
| 2692 | IN UINT32 CfgSmbusSsid; ///< Subsystem ID of SMBUS controller |
| 2693 | IN UINT32 CfgIdeSsid; ///< Subsystem ID of IDE controller |
| 2694 | IN UINT32 CfgSataAhciSsid; ///< Subsystem ID of SATA controller in AHCI mode |
| 2695 | IN UINT32 CfgSataIdeSsid; ///< Subsystem ID of SATA controller in IDE mode |
| 2696 | IN UINT32 CfgSataRaid5Ssid; ///< Subsystem ID of SATA controller in RAID5 mode |
| 2697 | IN UINT32 CfgSataRaidSsid; ///< Subsystem ID of SATA controller in RAID mode |
| 2698 | IN UINT32 CfgEhciSsid; ///< Subsystem ID of EHCI |
| 2699 | IN UINT32 CfgOhciSsid; ///< Subsystem ID of OHCI |
| 2700 | IN UINT32 CfgLpcSsid; ///< Subsystem ID of LPC ISA Bridge |
| 2701 | IN UINT32 CfgSdSsid; ///< Subsystem ID of SecureDigital controller |
| 2702 | IN UINT32 CfgXhciSsid; ///< Subsystem ID of XHCI |
| 2703 | IN BOOLEAN CfgFchPort80BehindPcib; ///< Is port80 cycle going to the PCI bridge |
| 2704 | IN BOOLEAN CfgFchEnableAcpiSleepTrap; ///< ACPI sleep SMI enable/disable |
| 2705 | IN GPP_LINKMODE CfgFchGppLinkConfig; ///< GPP link configuration |
| 2706 | IN BOOLEAN CfgFchGppPort0Present; ///< Is FCH GPP port 0 present |
| 2707 | IN BOOLEAN CfgFchGppPort1Present; ///< Is FCH GPP port 1 present |
| 2708 | IN BOOLEAN CfgFchGppPort2Present; ///< Is FCH GPP port 2 present |
| 2709 | IN BOOLEAN CfgFchGppPort3Present; ///< Is FCH GPP port 3 present |
| 2710 | IN BOOLEAN CfgFchGppPort0HotPlug; ///< Is FCH GPP port 0 hotplug capable |
| 2711 | IN BOOLEAN CfgFchGppPort1HotPlug; ///< Is FCH GPP port 1 hotplug capable |
| 2712 | IN BOOLEAN CfgFchGppPort2HotPlug; ///< Is FCH GPP port 2 hotplug capable |
| 2713 | IN BOOLEAN CfgFchGppPort3HotPlug; ///< Is FCH GPP port 3 hotplug capable |
| 2714 | |
| 2715 | IN UINT8 CfgFchEsataPortBitMap; ///< ESATA Port definition, eg: [0]=1, means port 0 is ESATA capable |
| 2716 | IN UINT8 CfgFchIrPinControl; ///< Register bitfield describing Infrared Pin Control: |
| 2717 | ///< [0] - IR Enable 0 |
| 2718 | ///< [1] - IR Enable 1 |
| 2719 | ///< [2] - IR Tx0 |
| 2720 | ///< [3] - IR Tx1 |
| 2721 | ///< [4] - IR Open Drain |
| 2722 | ///< [5] - IR Enable LED |
| 2723 | IN SD_CLOCK_CONTROL CfgFchSdClockControl; ///< FCH SD Clock Control |
| 2724 | IN SCI_MAP_CONTROL *CfgFchSciMapControl; ///< FCH SCI Mapping Control |
| 2725 | IN SATA_PHY_CONTROL *CfgFchSataPhyControl; ///< FCH SATA PHY Control |
| 2726 | IN GPIO_CONTROL *CfgFchGpioControl; ///< FCH GPIO Control |
| 2727 | } FCH_PLATFORM_POLICY; |
| 2728 | |
| 2729 | |
| 2730 | /// Build Option/Configuration Boolean Structure. |
| 2731 | typedef struct { |
| 2732 | IN AMD_CODE_HEADER VersionString; ///< AMD embedded code version string |
| 2733 | |
| 2734 | //Build Option Area |
| 2735 | IN BOOLEAN OptionUDimms; ///< @ref BLDOPT_REMOVE_UDIMMS_SUPPORT "BLDOPT_REMOVE_UDIMMS_SUPPORT" |
| 2736 | IN BOOLEAN OptionRDimms; ///< @ref BLDOPT_REMOVE_RDIMMS_SUPPORT "BLDOPT_REMOVE_RDIMMS_SUPPORT" |
| 2737 | IN BOOLEAN OptionLrDimms; ///< @ref BLDOPT_REMOVE_LRDIMMS_SUPPORT "BLDOPT_REMOVE_LRDIMMS_SUPPORT" |
| 2738 | IN BOOLEAN OptionEcc; ///< @ref BLDOPT_REMOVE_ECC_SUPPORT "BLDOPT_REMOVE_ECC_SUPPORT" |
| 2739 | IN BOOLEAN OptionBankInterleave; ///< @ref BLDOPT_REMOVE_BANK_INTERLEAVE "BLDOPT_REMOVE_BANK_INTERLEAVE" |
| 2740 | IN BOOLEAN OptionDctInterleave; ///< @ref BLDOPT_REMOVE_DCT_INTERLEAVE "BLDOPT_REMOVE_DCT_INTERLEAVE" |
| 2741 | IN BOOLEAN OptionNodeInterleave; ///< @ref BLDOPT_REMOVE_NODE_INTERLEAVE "BLDOPT_REMOVE_NODE_INTERLEAVE" |
| 2742 | IN BOOLEAN OptionParallelTraining; ///< @ref BLDOPT_REMOVE_PARALLEL_TRAINING "BLDOPT_REMOVE_PARALLEL_TRAINING" |
| 2743 | IN BOOLEAN OptionOnlineSpare; ///< @ref BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT "BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT" |
| 2744 | IN BOOLEAN OptionMemRestore; ///< @ref BLDOPT_REMOVE_MEM_RESTORE_SUPPORT "BLDOPT_REMOVE_MEM_RESTORE_SUPPORT" |
| 2745 | IN BOOLEAN OptionMultisocket; ///< @ref BLDOPT_REMOVE_MULTISOCKET_SUPPORT "BLDOPT_REMOVE_MULTISOCKET_SUPPORT" |
| 2746 | IN BOOLEAN OptionAcpiPstates; ///< @ref BLDOPT_REMOVE_ACPI_PSTATES "BLDOPT_REMOVE_ACPI_PSTATES" |
| 2747 | IN BOOLEAN OptionPStatesInHpcMode; ///< @ref BLDCFG_PSTATE_HPC_MODE "BLDCFG_PSTATE_HPC_MODE" |
| 2748 | IN BOOLEAN OptionCrat; ///< @ref BLDOPT_REMOVE_CRAT "BLDOPT_REMOVE_CRAT" |
| 2749 | IN BOOLEAN OptionCdit; ///< @ref BLDOPT_REMOVE_CDIT "BLDOPT_REMOVE_CDIT" |
| 2750 | IN BOOLEAN OptionSrat; ///< @ref BLDOPT_REMOVE_SRAT "BLDOPT_REMOVE_SRAT" |
| 2751 | IN BOOLEAN OptionSlit; ///< @ref BLDOPT_REMOVE_SLIT "BLDOPT_REMOVE_SLIT" |
| 2752 | IN BOOLEAN OptionWhea; ///< @ref BLDOPT_REMOVE_WHEA "BLDOPT_REMOVE_WHEA" |
| 2753 | IN BOOLEAN OptionDmi; ///< @ref BLDOPT_REMOVE_DMI "BLDOPT_REMOVE_DMI" |
| 2754 | IN BOOLEAN OptionEarlySamples; ///< @ref BLDOPT_REMOVE_EARLY_SAMPLES "BLDOPT_REMOVE_EARLY_SAMPLES" |
| 2755 | IN BOOLEAN OptionAddrToCsTranslator; ///< ADDR_TO_CS_TRANSLATOR |
| 2756 | |
| 2757 | //Build Configuration Area |
| 2758 | IN UINT64 CfgPciMmioAddress; ///< Pci Mmio Base Address to use for PCI Config accesses. |
| 2759 | ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCI_MMIO_BASE} |
| 2760 | IN UINT32 CfgPciMmioSize; ///< Pci Mmio region Size. |
| 2761 | ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCI_MMIO_SIZE} |
| 2762 | IN PLATFORM_VRM_CONFIGURATION CfgPlatVrmCfg[MaxVrmType]; ///< Several configuration settings for the voltage regulator modules. |
| 2763 | IN UINT32 CfgPlatNumIoApics; ///< The number of IO APICS for the platform. |
| 2764 | IN UINT32 CfgMemInitPstate; ///< Memory Init Pstate. |
| 2765 | IN PLATFORM_C1E_MODES CfgPlatformC1eMode; ///< Select the C1e Mode that will used. |
| 2766 | IN UINT32 CfgPlatformC1eOpData; ///< An IO port or additional C1e setup data, depends on C1e mode. |
| 2767 | IN UINT32 CfgPlatformC1eOpData1; ///< An IO port or additional C1e setup data, depends on C1e mode. |
| 2768 | IN UINT32 CfgPlatformC1eOpData2; ///< An IO port or additional C1e setup data, depends on C1e mode. |
| 2769 | IN UINT32 CfgPlatformC1eOpData3; ///< An IO port or additional C1e setup data, depends on C1e mode. |
| 2770 | IN PLATFORM_CSTATE_MODES CfgPlatformCStateMode; ///< Select the C-State Mode that will used. |
| 2771 | IN UINT32 CfgPlatformCStateOpData; ///< An IO port or additional C-State setup data, depends on C-State mode. |
| 2772 | IN UINT16 CfgPlatformCStateIoBaseAddress; ///< Specifies I/O ports that can be used to allow CPU to enter CStates |
| 2773 | IN PLATFORM_CPB_MODES CfgPlatformCpbMode; ///< Enable or disable core performance boost |
| 2774 | IN PLATFORM_LOW_POWER_PSTATE_MODES CfgLowPowerPstateForProcHot; ///< Low power Pstate for PROCHOT mode |
| 2775 | IN UINT32 CfgCoreLevelingMode; ///< Apply any downcoring or core count leveling as specified. |
| 2776 | IN PERFORMANCE_PROFILE CfgPerformanceProfile; ///< The platform's control flow mode and platform performance settings. |
| 2777 | IN CPU_HT_DEEMPHASIS_LEVEL *CfgPlatformDeemphasisList; ///< Deemphasis levels for the platform's HT links. |
| 2778 | |
| 2779 | IN UINT32 CfgAmdPlatformType; ///< Designate the platform as a Server, Desktop, or Mobile. |
| 2780 | IN UINT32 CfgAmdPstateCapValue; ///< Amd pstate ceiling enabling deck |
| 2781 | |
| 2782 | IN MEMORY_BUS_SPEED CfgMemoryBusFrequencyLimit; ///< Memory Bus Frequency Limit. |
| 2783 | ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT} |
| 2784 | IN BOOLEAN CfgMemoryModeUnganged; ///< Memory Mode Unganged. |
| 2785 | ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_MODE_UNGANGED} |
| 2786 | IN BOOLEAN CfgMemoryQuadRankCapable; ///< Memory Quad Rank Capable. |
| 2787 | ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_QUAD_RANK_CAPABLE} |
| 2788 | IN QUANDRANK_TYPE CfgMemoryQuadrankType; ///< Memory Quadrank Type. |
| 2789 | ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_QUADRANK_TYPE} |
| 2790 | IN BOOLEAN CfgMemoryRDimmCapable; ///< Memory RDIMM Capable. |
| 2791 | IN BOOLEAN CfgMemoryLRDimmCapable; ///< Memory LRDIMM Capable. |
| 2792 | IN BOOLEAN CfgMemoryUDimmCapable; ///< Memory UDIMM Capable. |
| 2793 | IN BOOLEAN CfgMemorySODimmCapable; ///< Memory SODimm Capable. |
| 2794 | ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_SODIMM_CAPABLE} |
| 2795 | IN BOOLEAN CfgLimitMemoryToBelow1Tb; ///< Limit memory address space to below 1TB |
| 2796 | IN BOOLEAN CfgMemoryEnableBankInterleaving; ///< Memory Enable Bank Interleaving. |
| 2797 | IN BOOLEAN CfgMemoryEnableNodeInterleaving; ///< Memory Enable Node Interleaving. |
| 2798 | IN BOOLEAN CfgMemoryChannelInterleaving; ///< Memory Channel Interleaving. |
| 2799 | IN BOOLEAN CfgMemoryPowerDown; ///< Memory Power Down. |
| 2800 | IN POWER_DOWN_MODE CfgPowerDownMode; ///< Power Down Mode. |
| 2801 | IN BOOLEAN CfgOnlineSpare; ///< Online Spare. |
| 2802 | IN BOOLEAN CfgMemoryParityEnable; ///< Memory Parity Enable. |
| 2803 | IN BOOLEAN CfgBankSwizzle; ///< Bank Swizzle. |
| 2804 | IN USER_MEMORY_TIMING_MODE CfgTimingModeSelect; ///< Timing Mode Select. |
| 2805 | IN MEMORY_BUS_SPEED CfgMemoryClockSelect; ///< Memory Clock Select. |
| 2806 | IN BOOLEAN CfgDqsTrainingControl; ///< Dqs Training Control. |
| 2807 | ///< Build-time customizable only - @BldCfgItem{BLDCFG_DQS_TRAINING_CONTROL} |
| 2808 | IN BOOLEAN CfgIgnoreSpdChecksum; ///< Ignore Spd Checksum. |
| 2809 | ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGNORE_SPD_CHECKSUM} |
| 2810 | IN BOOLEAN CfgUseBurstMode; ///< Use Burst Mode. |
| 2811 | ///< Build-time customizable only - @BldCfgItem{BLDCFG_USE_BURST_MODE} |
| 2812 | IN BOOLEAN CfgMemoryAllClocksOn; ///< Memory All Clocks On. |
| 2813 | ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_ALL_CLOCKS_ON} |
| 2814 | IN BOOLEAN CfgEnableEccFeature; ///< Enable ECC Feature. |
| 2815 | IN BOOLEAN CfgEccRedirection; ///< ECC Redirection. |
| 2816 | ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_REDIRECTION} |
| 2817 | IN UINT16 CfgScrubDramRate; ///< Scrub Dram Rate. |
| 2818 | ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_DRAM_RATE} |
| 2819 | IN UINT16 CfgScrubL2Rate; ///< Scrub L2Rate. |
| 2820 | ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_L2_RATE} |
| 2821 | IN UINT16 CfgScrubL3Rate; ///< Scrub L3Rate. |
| 2822 | ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_L3_RATE} |
| 2823 | IN UINT16 CfgScrubIcRate; ///< Scrub Ic Rate. |
| 2824 | ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_IC_RATE} |
| 2825 | IN UINT16 CfgScrubDcRate; ///< Scrub Dc Rate. |
| 2826 | ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_DC_RATE} |
| 2827 | IN BOOLEAN CfgEccSyncFlood; ///< ECC Sync Flood. |
| 2828 | ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_SYNC_FLOOD} |
| 2829 | IN UINT16 CfgEccSymbolSize; ///< ECC Symbol Size. |
| 2830 | ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_SYMBOL_SIZE} |
| 2831 | IN UINT64 CfgHeapDramAddress; ///< Heap contents will be temporarily stored in this address during the transition. |
| 2832 | ///< Build-time customizable only - @BldCfgItem{BLDCFG_HEAP_DRAM_ADDRESS} |
| 2833 | IN BOOLEAN CfgNodeMem1GBAlign; ///< Node Mem 1GB boundary Alignment |
| 2834 | IN BOOLEAN CfgS3LateRestore; ///< S3 Late Restore |
| 2835 | IN BOOLEAN CfgAcpiPstateIndependent; ///< PSD method dependent/Independent |
| 2836 | IN AP_MTRR_SETTINGS *CfgApMtrrSettingsList; ///< The AP's MTRR settings before final halt |
| 2837 | ///< Build-time customizable only - @BldCfgItem{BLDCFG_AP_MTRR_SETTINGS_LIST} |
| 2838 | IN UMA_MODE CfgUmaMode; ///< Uma Mode |
| 2839 | IN UINT32 CfgUmaSize; ///< Uma Size [31:0]=Addr[47:16] |
| 2840 | IN BOOLEAN CfgUmaAbove4G; ///< Uma Above 4G Support |
| 2841 | IN UMA_ALIGNMENT CfgUmaAlignment; ///< Uma alignment |
| 2842 | IN BOOLEAN CfgProcessorScopeInSb; ///< ACPI Processor Object in \\_SB scope |
| 2843 | IN CHAR8 CfgProcessorScopeName0; ///< OEM specific 1st character of processor scope name. |
| 2844 | IN CHAR8 CfgProcessorScopeName1; ///< OEM specific 2nd character of processor scope name. |
| 2845 | IN UINT8 CfgGnbHdAudio; ///< GNB HD Audio |
| 2846 | IN UINT8 CfgAbmSupport; ///< Abm Support |
| 2847 | IN UINT8 CfgDynamicRefreshRate; ///< DRR Dynamic Refresh Rate |
| 2848 | IN UINT16 CfgLcdBackLightControl; ///< LCD Backlight Control |
| 2849 | IN UINT8 CfgGnb3dStereoPinIndex; ///< 3D Stereo Pin ID. |
| 2850 | IN UINT32 CfgTempPcieMmioBaseAddress; ///< Temp pcie MMIO base Address |
| 2851 | ///< Build-time customizable only - @BldCfgItem{BLDCFG_TEMP_PCIE_MMIO_BASE_ADDRESS} |
| 2852 | IN UINT32 CfgGnbIGPUSSID; ///< Gnb internal GPU SSID |
| 2853 | ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGPU_SUBSYSTEM_ID} |
| 2854 | IN UINT32 CfgGnbHDAudioSSID; ///< Gnb HD Audio SSID |
| 2855 | ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID} |
| 2856 | IN UINT32 CfgGnbPcieSSID; ///< Gnb PCIe SSID |
| 2857 | ///< Build-time customizable only - @BldCfgItem{BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID} |
| 2858 | IN UINT16 CfgLvdsSpreadSpectrum; ///< Lvds Spread Spectrum |
| 2859 | ///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM} |
| 2860 | IN UINT16 CfgLvdsSpreadSpectrumRate; ///< Lvds Spread Spectrum Rate |
| 2861 | ///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE} |
| 2862 | IN FCH_PLATFORM_POLICY *FchBldCfg; ///< FCH platform build configuration policy |
| 2863 | |
| 2864 | IN BOOLEAN CfgIommuSupport; ///< IOMMU support |
| 2865 | IN UINT8 CfgLvdsPowerOnSeqDigonToDe; ///< Panel initialization timing |
| 2866 | IN UINT8 CfgLvdsPowerOnSeqDeToVaryBl; ///< Panel initialization timing |
| 2867 | IN UINT8 CfgLvdsPowerOnSeqDeToDigon; ///< Panel initialization timing |
| 2868 | IN UINT8 CfgLvdsPowerOnSeqVaryBlToDe; ///< Panel initialization timing |
| 2869 | IN UINT8 CfgLvdsPowerOnSeqOnToOffDelay; ///< Panel initialization timing |
| 2870 | IN UINT8 CfgLvdsPowerOnSeqVaryBlToBlon; ///< Panel initialization timing |
| 2871 | IN UINT8 CfgLvdsPowerOnSeqBlonToVaryBl; ///< Panel initialization timing |
| 2872 | IN UINT16 CfgLvdsMaxPixelClockFreq; ///< The maximum pixel clock frequency supported |
| 2873 | IN UINT32 CfgLcdBitDepthControlValue; ///< The LCD bit depth control settings |
| 2874 | IN UINT8 CfgLvds24bbpPanelMode; ///< The LVDS 24 BBP mode |
| 2875 | IN LVDS_MISC_CONTROL CfgLvdsMiscControl; ///< THe LVDS Misc control |
| 2876 | IN UINT16 CfgPcieRefClkSpreadSpectrum; ///< PCIe Reference Clock Spread Spectrum |
| 2877 | ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM} |
| 2878 | IN BOOLEAN CfgExternalVrefCtlFeature; ///< External Vref control |
| 2879 | IN FORCE_TRAIN_MODE CfgForceTrainMode; ///< Force Train Mode |
| 2880 | IN BOOLEAN CfgGnbRemoteDisplaySupport; ///< Wireless Display Support |
| 2881 | IN IOMMU_EXCLUSION_RANGE_DESCRIPTOR *CfgIvrsExclusionRangeList; |
| 2882 | IN BOOLEAN CfgGnbSyncFloodPinAsNmi; ///< @ref BLDCFG_USE_SYNCFLOOD_AS_NMI "BLDCFG_USE_SYNCFLOOD_AS_NMI" |
| 2883 | IN UINT8 CfgIgpuEnableDisablePolicy; ///< This item defines the iGPU Enable/Disable policy |
| 2884 | ///< @li 0 = Auto - use current default |
| 2885 | ///< @li 2 = Disable iGPU if ANY PCI or PCIe Graphics card is present |
| 2886 | ///< @BldCfgItem{BLDCFG_IGPU_ENABLE_DISABLE_POLICY} |
| 2887 | IN UINT8 CfgGnbSwTjOffset; ///< Software-writeable TjOffset to account for changes in junction temperature |
| 2888 | ///< Build-time customizable only - @BldCfgItem{BLDCFG_GNB_THERMAL_SENSOR_CORRECTION} |
| 2889 | IN UINT8 CfgLvdsMiscVoltAdjustment; ///< Travis register LVDS_CTRL_4 to adjust LVDS output voltage |
| 2890 | ///< Build-time customizable only - @BldCfgItem{BLDCFG_LVDS_MISC_VOL_ADJUSTMENT} |
| 2891 | IN DISPLAY_MISC_CONTROL CfgDisplayMiscControl; ///< The Display Misc control |
| 2892 | IN BOOLEAN Reserved; ///< reserved... |
| 2893 | } BUILD_OPT_CFG; |
| 2894 | |
| 2895 | /// A structure containing platform specific operational characteristics. This |
| 2896 | /// structure is initially populated by the initializer with a copy of the same |
| 2897 | /// structure that was created at build time using the build configuration controls. |
| 2898 | typedef struct _PLATFORM_CONFIGURATION { |
| 2899 | IN PERFORMANCE_PROFILE PlatformProfile; ///< Several configuration settings for the processor. |
| 2900 | IN CPU_HT_DEEMPHASIS_LEVEL *PlatformDeemphasisList; ///< Deemphasis levels for the platform's HT links. |
| 2901 | ///< @BldCfgItem{BLDCFG_PLATFORM_DEEMPHASIS_LIST}. |
| 2902 | ///< @n @e Examples: See @ref DeemphasisExamples "Deemphasis List Examples". |
| 2903 | IN UINT8 CoreLevelingMode; ///< Indicates how to balance the number of cores per processor. |
| 2904 | ///< @BldCfgItem{BLDCFG_CORE_LEVELING_MODE} |
| 2905 | IN PLATFORM_C1E_MODES C1eMode; ///< Specifies the method of C1e enablement - Disabled, HW, or message based. |
| 2906 | ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_MODE} |
| 2907 | IN UINT32 C1ePlatformData; ///< If C1eMode is HW, specifies the P_LVL3 I/O port of the platform. |
| 2908 | ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA} |
| 2909 | IN UINT32 C1ePlatformData1; ///< If C1eMode is SW, specifies the address of chipset's SMI command port. |
| 2910 | ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA1} |
| 2911 | IN UINT32 C1ePlatformData2; ///< If C1eMode is SW, specifies the unique number used by the SMI handler to identify SMI source. |
| 2912 | ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA2} |
| 2913 | IN UINT32 C1ePlatformData3; ///< If C1eMode is Auto, specifies the P_LVL3 I/O port of the platform for HW C1e |
| 2914 | ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA3} |
| 2915 | IN PLATFORM_CSTATE_MODES CStateMode; ///< Specifies the method of C-State enablement - Disabled, or C6. |
| 2916 | ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_MODE} |
| 2917 | IN UINT32 CStatePlatformData; ///< This element specifies some pertinent data needed for the operation of the Cstate feature |
| 2918 | ///< If CStateMode is CStateModeC6, this item is reserved |
| 2919 | ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_OPDATA} |
| 2920 | IN UINT16 CStateIoBaseAddress; ///< This item specifies a free block of 8 consecutive bytes of I/O ports that |
| 2921 | ///< can be used to allow the CPU to enter Cstates. |
| 2922 | ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS} |
| 2923 | IN PLATFORM_CPB_MODES CpbMode; ///< Specifies the method of core performance boost enablement - Disabled, or Auto. |
| 2924 | ///< @BldCfgItem{BLDCFG_PLATFORM_CPB_MODE} |
| 2925 | IN BOOLEAN UserOptionDmi; ///< When set to TRUE, the DMI data table is generated. |
| 2926 | IN BOOLEAN UserOptionPState; ///< When set to TRUE, the PState data tables are generated. |
| 2927 | IN BOOLEAN UserOptionCrat; ///< When set to TRUE, the CRAT data table is generated. |
| 2928 | IN BOOLEAN UserOptionCdit; ///< When set to TRUE, the CDIT data table is generated. |
| 2929 | IN BOOLEAN UserOptionSrat; ///< When set to TRUE, the SRAT data table is generated. |
| 2930 | IN BOOLEAN UserOptionSlit; ///< When set to TRUE, the SLIT data table is generated. |
| 2931 | IN BOOLEAN UserOptionWhea; ///< When set to TRUE, the WHEA data table is generated. |
| 2932 | IN PLATFORM_LOW_POWER_PSTATE_MODES LowPowerPstateForProcHot; ///< Specifies the method of low power Pstate for PROCHOT enablement - Disabled, or Auto. |
| 2933 | IN UINT32 PowerCeiling; ///< P-State Ceiling Enabling Deck - Max power milli-watts. |
| 2934 | IN BOOLEAN ForcePstateIndependent; ///< P-State _PSD independence or dependence. |
| 2935 | ///< @BldCfgItem{BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT} |
| 2936 | IN BOOLEAN PStatesInHpcMode; ///< @BldCfgItem{BLDCFG_PSTATE_HPC_MODE} |
| 2937 | IN UINT32 NumberOfIoApics; ///< Number of I/O APICs in the system |
| 2938 | ///< @BldCfgItem{BLDCFG_PLATFORM_NUM_IO_APICS} |
| 2939 | IN PLATFORM_VRM_CONFIGURATION VrmProperties[MaxVrmType]; ///< Several configuration settings for the voltage regulator modules. |
| 2940 | IN BOOLEAN ProcessorScopeInSb; ///< ACPI Processor Object in \\_SB scope |
| 2941 | ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_IN_SB} |
| 2942 | IN CHAR8 ProcessorScopeName0; ///< OEM specific 1st character of processor scope name. |
| 2943 | ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_NAME0} |
| 2944 | IN CHAR8 ProcessorScopeName1; ///< OEM specific 2nd character of processor scope name. |
| 2945 | ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_NAME1} |
| 2946 | IN UINT8 GnbHdAudio; ///< Control GFX HD Audio controller(Used for HDMI and DP display output), |
| 2947 | ///< essentially it enables function 1 of graphics device. |
| 2948 | ///< @li 0 = HD Audio disable |
| 2949 | ///< @li 1 = HD Audio enable |
| 2950 | ///< @BldCfgItem{BLDCFG_CFG_GNB_HD_AUDIO} |
| 2951 | IN UINT8 AbmSupport; ///< Automatic adjust LVDS/eDP Back light level support.It is |
| 2952 | ///< characteristic specific to display panel which used by platform design. |
| 2953 | ///< @li 0 = ABM support disabled |
| 2954 | ///< @li 1 = ABM support enabled |
| 2955 | ///< @BldCfgItem{BLDCFG_CFG_ABM_SUPPORT} |
| 2956 | IN UINT8 DynamicRefreshRate; ///< Adjust refresh rate on LVDS/eDP. |
| 2957 | ///< @BldCfgItem{BLDCFG_CFG_DYNAMIC_REFRESH_RATE} |
| 2958 | IN UINT16 LcdBackLightControl; ///< The PWM frequency to LCD backlight control. |
| 2959 | ///< If equal to 0 backlight not controlled by iGPU |
| 2960 | ///< @BldCfgItem{BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL} |
| 2961 | } PLATFORM_CONFIGURATION; |
| 2962 | |
| 2963 | |
| 2964 | /********************************************************************** |
| 2965 | * Structures for: AmdInitLate |
| 2966 | **********************************************************************/ |
| 2967 | #define PROC_VERSION_LENGTH 48 |
| 2968 | #define MAX_DIMMS_PER_SOCKET 16 |
| 2969 | #define PROC_MANU_LENGTH 29 |
| 2970 | |
| 2971 | /* Interface Parameter Structures */ |
| 2972 | /// DMI Type4 - Processor ID |
| 2973 | typedef struct { |
| 2974 | OUT UINT32 ProcIdLsd; ///< Lower half of 64b ID |
| 2975 | OUT UINT32 ProcIdMsd; ///< Upper half of 64b ID |
| 2976 | } TYPE4_PROC_ID; |
| 2977 | |
| 2978 | /// DMI Type 4 - Processor information |
| 2979 | typedef struct { |
| 2980 | OUT UINT8 T4ProcType; ///< CPU Type |
| 2981 | OUT UINT8 T4ProcFamily; ///< Family 1 |
| 2982 | OUT TYPE4_PROC_ID T4ProcId; ///< Id |
| 2983 | OUT UINT8 T4Voltage; ///< Voltage |
| 2984 | OUT UINT16 T4ExternalClock; ///< External clock |
| 2985 | OUT UINT16 T4MaxSpeed; ///< Max speed |
| 2986 | OUT UINT16 T4CurrentSpeed; ///< Current speed |
| 2987 | OUT UINT8 T4Status; ///< Status |
| 2988 | OUT UINT8 T4ProcUpgrade; ///< Up grade |
| 2989 | OUT UINT8 T4CoreCount; ///< Core count |
| 2990 | OUT UINT8 T4CoreEnabled; ///< Core Enable |
| 2991 | OUT UINT8 T4ThreadCount; ///< Thread count |
| 2992 | OUT UINT16 T4ProcCharacteristics; ///< Characteristics |
| 2993 | OUT UINT16 T4ProcFamily2; ///< Family 2 |
| 2994 | OUT CHAR8 T4ProcVersion[PROC_VERSION_LENGTH]; ///< Cpu version |
| 2995 | OUT CHAR8 T4ProcManufacturer[PROC_MANU_LENGTH]; ///< Manufacturer |
| 2996 | } TYPE4_DMI_INFO; |
| 2997 | |
| 2998 | /// DMI Type 7 - Cache information |
| 2999 | typedef struct _TYPE7_DMI_INFO { |
| 3000 | OUT UINT16 T7CacheCfg; ///< Cache cfg |
| 3001 | OUT UINT16 T7MaxCacheSize; ///< Max size |
| 3002 | OUT UINT16 T7InstallSize; ///< Install size |
| 3003 | OUT UINT16 T7SupportedSramType; ///< Supported Sram Type |
| 3004 | OUT UINT16 T7CurrentSramType; ///< Current type |
| 3005 | OUT UINT8 T7CacheSpeed; ///< Speed |
| 3006 | OUT UINT8 T7ErrorCorrectionType; ///< ECC type |
| 3007 | OUT UINT8 T7SystemCacheType; ///< Cache type |
| 3008 | OUT UINT8 T7Associativity; ///< Associativity |
| 3009 | } TYPE7_DMI_INFO; |
| 3010 | |
| 3011 | /// DMI Type 16 offset 04h - Location |
| 3012 | typedef enum { |
| 3013 | OtherLocation = 0x01, ///< Assign 01 to Other |
| 3014 | UnknownLocation, ///< Assign 02 to Unknown |
| 3015 | SystemboardOrMotherboard, ///< Assign 03 to systemboard or motherboard |
| 3016 | IsaAddonCard, ///< Assign 04 to ISA add-on card |
| 3017 | EisaAddonCard, ///< Assign 05 to EISA add-on card |
| 3018 | PciAddonCard, ///< Assign 06 to PCI add-on card |
| 3019 | McaAddonCard, ///< Assign 07 to MCA add-on card |
| 3020 | PcmciaAddonCard, ///< Assign 08 to PCMCIA add-on card |
| 3021 | ProprietaryAddonCard, ///< Assign 09 to proprietary add-on card |
| 3022 | NuBus, ///< Assign 0A to NuBus |
| 3023 | Pc98C20AddonCard, ///< Assign 0A0 to PC-98/C20 add-on card |
| 3024 | Pc98C24AddonCard, ///< Assign 0A1 to PC-98/C24 add-on card |
| 3025 | Pc98EAddoncard, ///< Assign 0A2 to PC-98/E add-on card |
| 3026 | Pc98LocalBusAddonCard ///< Assign 0A3 to PC-98/Local bus add-on card |
| 3027 | } DMI_T16_LOCATION; |
| 3028 | |
| 3029 | /// DMI Type 16 offset 05h - Memory Error Correction |
| 3030 | typedef enum { |
| 3031 | OtherUse = 0x01, ///< Assign 01 to Other |
| 3032 | UnknownUse, ///< Assign 02 to Unknown |
| 3033 | SystemMemory, ///< Assign 03 to system memory |
| 3034 | VideoMemory, ///< Assign 04 to video memory |
| 3035 | FlashMemory, ///< Assign 05 to flash memory |
| 3036 | NonvolatileRam, ///< Assign 06 to non-volatile RAM |
| 3037 | CacheMemory ///< Assign 07 to cache memory |
| 3038 | } DMI_T16_USE; |
| 3039 | |
| 3040 | /// DMI Type 16 offset 07h - Maximum Capacity |
| 3041 | typedef enum { |
| 3042 | Dmi16OtherErrCorrection = 0x01, ///< Assign 01 to Other |
| 3043 | Dmi16UnknownErrCorrection, ///< Assign 02 to Unknown |
| 3044 | Dmi16NoneErrCorrection, ///< Assign 03 to None |
| 3045 | Dmi16Parity, ///< Assign 04 to parity |
| 3046 | Dmi16SingleBitEcc, ///< Assign 05 to Single-bit ECC |
| 3047 | Dmi16MultiBitEcc, ///< Assign 06 to Multi-bit ECC |
| 3048 | Dmi16Crc ///< Assign 07 to CRC |
| 3049 | } DMI_T16_ERROR_CORRECTION; |
| 3050 | |
| 3051 | /// DMI Type 16 - Physical Memory Array |
| 3052 | typedef struct { |
| 3053 | OUT DMI_T16_LOCATION Location; ///< The physical location of the Memory Array, |
| 3054 | ///< whether on the system board or an add-in board. |
| 3055 | OUT DMI_T16_USE Use; ///< Identifies the function for which the array |
| 3056 | ///< is used. |
| 3057 | OUT DMI_T16_ERROR_CORRECTION MemoryErrorCorrection; ///< The primary hardware error correction or |
| 3058 | ///< detection method supported by this memory array. |
| 3059 | OUT UINT32 MaximumCapacity; ///< The maximum memory capacity, in kilobytes, |
| 3060 | ///< for the array. |
| 3061 | OUT UINT16 NumberOfMemoryDevices; ///< The number of slots or sockets available |
| 3062 | ///< for memory devices in this array. |
| 3063 | OUT UINT64 ExtMaxCapacity; ///< The maximum memory capacity, in bytes, |
| 3064 | ///< for this array. |
| 3065 | } TYPE16_DMI_INFO; |
| 3066 | |
| 3067 | /// DMI Type 17 offset 0Eh - Form Factor |
| 3068 | typedef enum { |
| 3069 | OtherFormFactor = 0x01, ///< Assign 01 to Other |
| 3070 | UnknowFormFactor, ///< Assign 02 to Unknown |
| 3071 | SimmFormFactor, ///< Assign 03 to SIMM |
| 3072 | SipFormFactor, ///< Assign 04 to SIP |
| 3073 | ChipFormFactor, ///< Assign 05 to Chip |
| 3074 | DipFormFactor, ///< Assign 06 to DIP |
| 3075 | ZipFormFactor, ///< Assign 07 to ZIP |
| 3076 | ProprietaryCardFormFactor, ///< Assign 08 to Proprietary Card |
| 3077 | DimmFormFactorFormFactor, ///< Assign 09 to DIMM |
| 3078 | TsopFormFactor, ///< Assign 10 to TSOP |
| 3079 | RowOfChipsFormFactor, ///< Assign 11 to Row of chips |
| 3080 | RimmFormFactor, ///< Assign 12 to RIMM |
| 3081 | SodimmFormFactor, ///< Assign 13 to SODIMM |
| 3082 | SrimmFormFactor, ///< Assign 14 to SRIMM |
| 3083 | FbDimmFormFactor ///< Assign 15 to FB-DIMM |
| 3084 | } DMI_T17_FORM_FACTOR; |
| 3085 | |
| 3086 | /// DMI Type 17 offset 12h - Memory Type |
| 3087 | typedef enum { |
| 3088 | OtherMemType = 0x01, ///< Assign 01 to Other |
| 3089 | UnknownMemType, ///< Assign 02 to Unknown |
| 3090 | DramMemType, ///< Assign 03 to DRAM |
| 3091 | EdramMemType, ///< Assign 04 to EDRAM |
| 3092 | VramMemType, ///< Assign 05 to VRAM |
| 3093 | SramMemType, ///< Assign 06 to SRAM |
| 3094 | RamMemType, ///< Assign 07 to RAM |
| 3095 | RomMemType, ///< Assign 08 to ROM |
| 3096 | FlashMemType, ///< Assign 09 to Flash |
| 3097 | EepromMemType, ///< Assign 10 to EEPROM |
| 3098 | FepromMemType, ///< Assign 11 to FEPROM |
| 3099 | EpromMemType, ///< Assign 12 to EPROM |
| 3100 | CdramMemType, ///< Assign 13 to CDRAM |
| 3101 | ThreeDramMemType, ///< Assign 14 to 3DRAM |
| 3102 | SdramMemType, ///< Assign 15 to SDRAM |
| 3103 | SgramMemType, ///< Assign 16 to SGRAM |
| 3104 | RdramMemType, ///< Assign 17 to RDRAM |
| 3105 | DdrMemType, ///< Assign 18 to DDR |
| 3106 | Ddr2MemType, ///< Assign 19 to DDR2 |
| 3107 | Ddr2FbdimmMemType, ///< Assign 20 to DDR2 FB-DIMM |
| 3108 | Ddr3MemType = 0x18, ///< Assign 24 to DDR3 |
| 3109 | Fbd2MemType ///< Assign 25 to FBD2 |
| 3110 | } DMI_T17_MEMORY_TYPE; |
| 3111 | |
| 3112 | /// DMI Type 17 offset 13h - Type Detail |
| 3113 | typedef struct { |
| 3114 | OUT UINT16 Reserved1:1; ///< Reserved |
| 3115 | OUT UINT16 Other:1; ///< Other |
| 3116 | OUT UINT16 Unknown:1; ///< Unknown |
| 3117 | OUT UINT16 FastPaged:1; ///< Fast-Paged |
| 3118 | OUT UINT16 StaticColumn:1; ///< Static column |
| 3119 | OUT UINT16 PseudoStatic:1; ///< Pseudo-static |
| 3120 | OUT UINT16 Rambus:1; ///< RAMBUS |
| 3121 | OUT UINT16 Synchronous:1; ///< Synchronous |
| 3122 | OUT UINT16 Cmos:1; ///< CMOS |
| 3123 | OUT UINT16 Edo:1; ///< EDO |
| 3124 | OUT UINT16 WindowDram:1; ///< Window DRAM |
| 3125 | OUT UINT16 CacheDram:1; ///< Cache Dram |
| 3126 | OUT UINT16 NonVolatile:1; ///< Non-volatile |
| 3127 | OUT UINT16 Registered:1; ///< Registered (Buffered) |
| 3128 | OUT UINT16 Unbuffered:1; ///< Unbuffered (Unregistered) |
| 3129 | OUT UINT16 Reserved2:1; ///< Reserved |
| 3130 | } DMI_T17_TYPE_DETAIL; |
| 3131 | |
| 3132 | /// DMI Type 17 - Memory Device |
| 3133 | typedef struct { |
| 3134 | OUT UINT16 TotalWidth; ///< Total Width, in bits, of this memory device, including any check or error-correction bits. |
| 3135 | OUT UINT16 DataWidth; ///< Data Width, in bits, of this memory device. |
| 3136 | OUT UINT16 MemorySize; ///< The size of the memory device. |
| 3137 | OUT DMI_T17_FORM_FACTOR FormFactor; ///< The implementation form factor for this memory device. |
| 3138 | OUT UINT8 DeviceSet; ///< Identifies when the Memory Device is one of a set of |
| 3139 | ///< Memory Devices that must be populated with all devices of |
| 3140 | ///< the same type and size, and the set to which this device belongs. |
| 3141 | OUT CHAR8 DeviceLocator[8]; ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located. |
| 3142 | OUT CHAR8 BankLocator[10]; ///< The string number of the string that identifies the physically labeled bank where the memory device is located. |
| 3143 | OUT DMI_T17_MEMORY_TYPE MemoryType; ///< The type of memory used in this device. |
| 3144 | OUT DMI_T17_TYPE_DETAIL TypeDetail; ///< Additional detail on the memory device type |
| 3145 | OUT UINT16 Speed; ///< Identifies the speed of the device, in megahertz (MHz). |
| 3146 | OUT UINT64 ManufacturerIdCode; ///< Manufacturer ID code. |
| 3147 | OUT CHAR8 SerialNumber[9]; ///< Serial Number. |
| 3148 | OUT CHAR8 PartNumber[19]; ///< Part Number. |
| 3149 | OUT UINT8 Attributes; ///< Bits 7-4: Reserved, Bits 3-0: rank. |
| 3150 | OUT UINT32 ExtSize; ///< Extended Size. |
| 3151 | OUT UINT16 ConfigSpeed; ///< Configured memory clock speed |
| 3152 | } TYPE17_DMI_INFO; |
| 3153 | |
| 3154 | /// Memory DMI Type 17 and 20 - for memory use |
| 3155 | typedef struct { |
| 3156 | OUT UINT16 TotalWidth; ///< Total Width, in bits, of this memory device, including any check or error-correction bits. |
| 3157 | OUT UINT16 DataWidth; ///< Data Width, in bits, of this memory device. |
| 3158 | OUT UINT16 MemorySize; ///< The size of the memory device. |
| 3159 | OUT DMI_T17_FORM_FACTOR FormFactor; ///< The implementation form factor for this memory device. |
| 3160 | OUT UINT8 DeviceLocator; ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located. |
| 3161 | OUT UINT8 BankLocator; ///< The string number of the string that identifies the physically labeled bank where the memory device is located. |
| 3162 | OUT UINT16 Speed; ///< Identifies the speed of the device, in megahertz (MHz). |
| 3163 | OUT UINT64 ManufacturerIdCode; ///< Manufacturer ID code. |
| 3164 | OUT UINT8 SerialNumber[4]; ///< Serial Number. |
| 3165 | OUT UINT8 PartNumber[18]; ///< Part Number. |
| 3166 | OUT UINT8 Attributes; ///< Bits 7-4: Reserved, Bits 3-0: rank. |
| 3167 | OUT UINT32 ExtSize; ///< Extended Size. |
| 3168 | OUT UINT8 Socket:3; ///< Socket ID |
| 3169 | OUT UINT8 Channel:2; ///< Channel ID |
| 3170 | OUT UINT8 Dimm:2; ///< DIMM ID |
| 3171 | OUT UINT8 DimmPresent:1; ///< Dimm Present |
| 3172 | OUT UINT32 StartingAddr; ///< The physical address, in kilobytes, of a range |
| 3173 | ///< of memory mapped to the referenced Memory Device. |
| 3174 | OUT UINT32 EndingAddr; ///< The handle, or instance number, associated with |
| 3175 | ///< the Memory Device structure to which this address |
| 3176 | ///< range is mapped. |
| 3177 | OUT UINT16 ConfigSpeed; ///< Configured memory clock speed |
| 3178 | OUT UINT64 ExtStartingAddr; ///< The physical address, in bytes, of a range of |
| 3179 | ///< memory mapped to the referenced Memory Device. |
| 3180 | OUT UINT64 ExtEndingAddr; ///< The physical ending address, in bytes, of the last of |
| 3181 | ///< a range of addresses mapped to the referenced Memory Device. |
| 3182 | } MEM_DMI_INFO; |
| 3183 | |
| 3184 | /// DMI Type 19 - Memory Array Mapped Address |
| 3185 | typedef struct { |
| 3186 | OUT UINT32 StartingAddr; ///< The physical address, in kilobytes, |
| 3187 | ///< of a range of memory mapped to the |
| 3188 | ///< specified physical memory array. |
| 3189 | OUT UINT32 EndingAddr; ///< The physical ending address of the |
| 3190 | ///< last kilobyte of a range of addresses |
| 3191 | ///< mapped to the specified physical memory array. |
| 3192 | OUT UINT16 MemoryArrayHandle; ///< The handle, or instance number, associated |
| 3193 | ///< with the physical memory array to which this |
| 3194 | ///< address range is mapped. |
| 3195 | OUT UINT8 PartitionWidth; ///< Identifies the number of memory devices that |
| 3196 | ///< form a single row of memory for the address |
| 3197 | ///< partition defined by this structure. |
| 3198 | OUT UINT64 ExtStartingAddr; ///< The physical address, in bytes, of a range of |
| 3199 | ///< memory mapped to the specified Physical Memory Array. |
| 3200 | OUT UINT64 ExtEndingAddr; ///< The physical address, in bytes, of a range of |
| 3201 | ///< memory mapped to the specified Physical Memory Array. |
| 3202 | } TYPE19_DMI_INFO; |
| 3203 | |
| 3204 | ///DMI Type 20 - Memory Device Mapped Address |
| 3205 | typedef struct { |
| 3206 | OUT UINT32 StartingAddr; ///< The physical address, in kilobytes, of a range |
| 3207 | ///< of memory mapped to the referenced Memory Device. |
| 3208 | OUT UINT32 EndingAddr; ///< The handle, or instance number, associated with |
| 3209 | ///< the Memory Device structure to which this address |
| 3210 | ///< range is mapped. |
| 3211 | OUT UINT16 MemoryDeviceHandle; ///< The handle, or instance number, associated with |
| 3212 | ///< the Memory Device structure to which this address |
| 3213 | ///< range is mapped. |
| 3214 | OUT UINT16 MemoryArrayMappedAddressHandle; ///< The handle, or instance number, associated |
| 3215 | ///< with the Memory Array Mapped Address structure to |
| 3216 | ///< which this device address range is mapped. |
| 3217 | OUT UINT8 PartitionRowPosition; ///< Identifies the position of the referenced Memory |
| 3218 | ///< Device in a row of the address partition. |
| 3219 | OUT UINT8 InterleavePosition; ///< The position of the referenced Memory Device in |
| 3220 | ///< an interleave. |
| 3221 | OUT UINT8 InterleavedDataDepth; ///< The maximum number of consecutive rows from the |
| 3222 | ///< referenced Memory Device that are accessed in a |
| 3223 | ///< single interleaved transfer. |
| 3224 | OUT UINT64 ExtStartingAddr; ///< The physical address, in bytes, of a range of |
| 3225 | ///< memory mapped to the referenced Memory Device. |
| 3226 | OUT UINT64 ExtEndingAddr; ///< The physical ending address, in bytes, of the last of |
| 3227 | ///< a range of addresses mapped to the referenced Memory Device. |
| 3228 | } TYPE20_DMI_INFO; |
| 3229 | |
| 3230 | /// Collection of pointers to the DMI records |
| 3231 | typedef struct { |
| 3232 | OUT TYPE4_DMI_INFO T4[MAX_SOCKETS_SUPPORTED]; ///< Type 4 struc |
| 3233 | OUT TYPE7_DMI_INFO T7L1[MAX_SOCKETS_SUPPORTED]; ///< Type 7 struc 1 |
| 3234 | OUT TYPE7_DMI_INFO T7L2[MAX_SOCKETS_SUPPORTED]; ///< Type 7 struc 2 |
| 3235 | OUT TYPE7_DMI_INFO T7L3[MAX_SOCKETS_SUPPORTED]; ///< Type 7 struc 3 |
| 3236 | OUT TYPE16_DMI_INFO T16; ///< Type 16 struc |
| 3237 | OUT TYPE17_DMI_INFO T17[MAX_SOCKETS_SUPPORTED][MAX_CHANNELS_PER_SOCKET][MAX_DIMMS_PER_CHANNEL]; ///< Type 17 struc |
| 3238 | OUT TYPE19_DMI_INFO T19; ///< Type 19 struc |
| 3239 | OUT TYPE20_DMI_INFO T20[MAX_SOCKETS_SUPPORTED][MAX_CHANNELS_PER_SOCKET][MAX_DIMMS_PER_CHANNEL]; ///< Type 20 struc |
| 3240 | } DMI_INFO; |
| 3241 | |
| 3242 | /********************************************************************** |
| 3243 | * Interface call: AllocateExecutionCache |
| 3244 | **********************************************************************/ |
| 3245 | #define MAX_CACHE_REGIONS 3 |
| 3246 | |
| 3247 | /// AllocateExecutionCache sub param structure for cached memory region |
| 3248 | typedef struct { |
| 3249 | IN OUT UINT32 ExeCacheStartAddr; ///< Start address |
| 3250 | IN OUT UINT32 ExeCacheSize; ///< Size |
| 3251 | } EXECUTION_CACHE_REGION; |
| 3252 | |
| 3253 | /********************************************************************** |
| 3254 | * Interface call: AmdGetAvailableExeCacheSize |
| 3255 | **********************************************************************/ |
| 3256 | /// Get available Cache remain |
| 3257 | typedef struct { |
| 3258 | IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header |
| 3259 | OUT UINT32 AvailableExeCacheSize; ///< Remain size |
| 3260 | } AMD_GET_EXE_SIZE_PARAMS; |
| 3261 | |
| 3262 | AGESA_STATUS |
| 3263 | AmdGetAvailableExeCacheSize ( |
| 3264 | IN OUT AMD_GET_EXE_SIZE_PARAMS *AmdGetExeSizeParams |
| 3265 | ); |
| 3266 | |
| 3267 | /// Selection type for core leveling |
| 3268 | typedef enum { |
| 3269 | CORE_LEVEL_LOWEST, ///< Level to lowest common denominator |
| 3270 | CORE_LEVEL_TWO, ///< Level to 2 cores |
| 3271 | CORE_LEVEL_POWER_OF_TWO, ///< Level to 1,2,4 or 8 |
| 3272 | CORE_LEVEL_NONE, ///< Do no leveling |
| 3273 | CORE_LEVEL_COMPUTE_UNIT, ///< Level cores to one core per compute unit |
| 3274 | CORE_LEVEL_ONE, ///< Level to 1 core |
| 3275 | CORE_LEVEL_THREE, ///< Level to 3 cores |
| 3276 | CORE_LEVEL_FOUR, ///< Level to 4 cores |
| 3277 | CORE_LEVEL_FIVE, ///< Level to 5 cores |
| 3278 | CORE_LEVEL_SIX, ///< Level to 6 cores |
| 3279 | CORE_LEVEL_SEVEN, ///< Level to 7 cores |
| 3280 | CORE_LEVEL_EIGHT, ///< Level to 8 cores |
| 3281 | CORE_LEVEL_NINE, ///< Level to 9 cores |
| 3282 | CORE_LEVEL_TEN, ///< Level to 10 cores |
| 3283 | CORE_LEVEL_ELEVEN, ///< Level to 11 cores |
| 3284 | CORE_LEVEL_TWELVE, ///< Level to 12 cores |
| 3285 | CORE_LEVEL_THIRTEEN, ///< Level to 13 cores |
| 3286 | CORE_LEVEL_FOURTEEN, ///< Level to 14 cores |
| 3287 | CORE_LEVEL_FIFTEEN, ///< Level to 15 cores |
| 3288 | CoreLevelModeMax ///< Used for bounds checking |
| 3289 | } CORE_LEVELING_TYPE; |
| 3290 | |
| 3291 | |
| 3292 | |
| 3293 | |
| 3294 | |
| 3295 | /************************************************************************ |
| 3296 | * |
| 3297 | * AGESA Basic Level interface structure definition and function prototypes |
| 3298 | * |
| 3299 | ***********************************************************************/ |
| 3300 | |
| 3301 | /********************************************************************** |
| 3302 | * Interface call: AmdCreateStruct |
| 3303 | **********************************************************************/ |
| 3304 | AGESA_STATUS |
| 3305 | AmdCreateStruct ( |
| 3306 | IN OUT AMD_INTERFACE_PARAMS *InterfaceParams |
| 3307 | ); |
| 3308 | |
| 3309 | /********************************************************************** |
| 3310 | * Interface call: AmdReleaseStruct |
| 3311 | **********************************************************************/ |
| 3312 | AGESA_STATUS |
| 3313 | AmdReleaseStruct ( |
| 3314 | IN OUT AMD_INTERFACE_PARAMS *InterfaceParams |
| 3315 | ); |
| 3316 | |
| 3317 | /********************************************************************** |
| 3318 | * Interface call: AmdInitReset |
| 3319 | **********************************************************************/ |
| 3320 | /// AmdInitReset param structure |
| 3321 | typedef struct { |
| 3322 | IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header |
| 3323 | IN EXECUTION_CACHE_REGION CacheRegion[3]; ///< The cached memory region |
| 3324 | IN AMD_HT_RESET_INTERFACE HtConfig; ///< The interface for Ht Recovery |
| 3325 | IN FCH_RESET_INTERFACE FchInterface; ///< Interface for FCH configuration |
| 3326 | } AMD_RESET_PARAMS; |
| 3327 | |
| 3328 | AGESA_STATUS |
| 3329 | AmdInitReset ( |
| 3330 | IN OUT AMD_RESET_PARAMS *ResetParams |
| 3331 | ); |
| 3332 | |
| 3333 | |
| 3334 | /********************************************************************** |
| 3335 | * Interface call: AmdInitEarly |
| 3336 | **********************************************************************/ |
| 3337 | /// InitEarly param structure |
| 3338 | /// |
| 3339 | /// Provide defaults or customizations to each service performed in AmdInitEarly. |
| 3340 | /// |
| 3341 | typedef struct { |
| 3342 | IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header |
| 3343 | IN EXECUTION_CACHE_REGION CacheRegion[3]; ///< Execution Map Interface |
| 3344 | IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. |
| 3345 | IN AMD_HT_INTERFACE HtConfig; ///< HyperTransport Interface |
| 3346 | IN GNB_CONFIGURATION GnbConfig; ///< GNB configuration |
| 3347 | } AMD_EARLY_PARAMS; |
| 3348 | |
| 3349 | AGESA_STATUS |
| 3350 | AmdInitEarly ( |
| 3351 | IN OUT AMD_EARLY_PARAMS *EarlyParams |
| 3352 | ); |
| 3353 | |
| 3354 | |
| 3355 | /********************************************************************** |
| 3356 | * Interface call: AmdInitPost |
| 3357 | **********************************************************************/ |
| 3358 | /// AmdInitPost param structure |
| 3359 | typedef struct { |
| 3360 | IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header |
| 3361 | IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. |
| 3362 | IN MEM_PARAMETER_STRUCT MemConfig; ///< Memory post param |
| 3363 | IN GNB_POST_CONFIGURATION GnbPostConfig; ///< GNB post param |
| 3364 | } AMD_POST_PARAMS; |
| 3365 | |
| 3366 | AGESA_STATUS |
| 3367 | AmdInitPost ( |
| 3368 | IN OUT AMD_POST_PARAMS *PostParams ///< Amd Cpu init param |
| 3369 | ); |
| 3370 | |
| 3371 | |
| 3372 | /********************************************************************** |
| 3373 | * Interface call: AmdInitEnv |
| 3374 | **********************************************************************/ |
| 3375 | /// AmdInitEnv param structure |
| 3376 | typedef struct { |
| 3377 | IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header |
| 3378 | IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. |
| 3379 | IN GNB_ENV_CONFIGURATION GnbEnvConfiguration; ///< GNB configuration |
| 3380 | IN FCH_INTERFACE FchInterface; ///< FCH configuration |
| 3381 | } AMD_ENV_PARAMS; |
| 3382 | |
| 3383 | AGESA_STATUS |
| 3384 | AmdInitEnv ( |
| 3385 | IN OUT AMD_ENV_PARAMS *EnvParams |
| 3386 | ); |
| 3387 | |
| 3388 | |
| 3389 | /********************************************************************** |
| 3390 | * Interface call: AmdInitMid |
| 3391 | **********************************************************************/ |
| 3392 | /// AmdInitMid param structure |
| 3393 | typedef struct { |
| 3394 | IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header |
| 3395 | IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. |
| 3396 | IN GNB_MID_CONFIGURATION GnbMidConfiguration; ///< GNB configuration |
| 3397 | IN FCH_INTERFACE FchInterface; ///< FCH configuration |
| 3398 | } AMD_MID_PARAMS; |
| 3399 | |
| 3400 | AGESA_STATUS |
| 3401 | AmdInitMid ( |
| 3402 | IN OUT AMD_MID_PARAMS *MidParams |
| 3403 | ); |
| 3404 | |
| 3405 | |
| 3406 | /********************************************************************** |
| 3407 | * Interface call: AmdInitLate |
| 3408 | **********************************************************************/ |
| 3409 | /// AmdInitLate param structure |
| 3410 | typedef struct { |
| 3411 | IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header |
| 3412 | IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. |
| 3413 | IN IOMMU_EXCLUSION_RANGE_DESCRIPTOR *IvrsExclusionRangeList; ///< Pointer to array of exclusion ranges |
| 3414 | OUT DMI_INFO *DmiTable; ///< DMI Interface |
| 3415 | OUT VOID *AcpiPState; ///< Acpi Pstate SSDT Table |
| 3416 | OUT VOID *AcpiSrat; ///< SRAT Table |
| 3417 | OUT VOID *AcpiSlit; ///< SLIT Table |
| 3418 | OUT VOID *AcpiWheaMce; ///< WHEA MCE Table |
| 3419 | OUT VOID *AcpiWheaCmc; ///< WHEA CMC Table |
| 3420 | OUT VOID *AcpiAlib; ///< ACPI SSDT table with ALIB implementation |
| 3421 | OUT VOID *AcpiIvrs; ///< IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table |
| 3422 | OUT VOID *AcpiCrat; ///< Component Resource Affinity Table table |
| 3423 | OUT VOID *AcpiCdit; ///< Component Locality Distance Information table |
| 3424 | } AMD_LATE_PARAMS; |
| 3425 | |
| 3426 | AGESA_STATUS |
| 3427 | AmdInitLate ( |
| 3428 | IN OUT AMD_LATE_PARAMS *LateParams |
| 3429 | ); |
| 3430 | |
| 3431 | /********************************************************************** |
| 3432 | * Interface call: AmdInitRecovery |
| 3433 | **********************************************************************/ |
| 3434 | /// CPU Recovery Parameters |
| 3435 | typedef struct { |
| 3436 | IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header |
| 3437 | IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. |
| 3438 | } AMD_CPU_RECOVERY_PARAMS; |
| 3439 | |
| 3440 | /// AmdInitRecovery param structure |
| 3441 | typedef struct { |
| 3442 | IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header |
| 3443 | IN MEM_PARAMETER_STRUCT MemConfig; ///< Memory post param |
| 3444 | IN EXECUTION_CACHE_REGION CacheRegion[3]; ///< The cached memory region. And the max cache region is 3 |
| 3445 | IN AMD_CPU_RECOVERY_PARAMS CpuRecoveryParams; ///< Params for CPU related recovery init. |
| 3446 | } AMD_RECOVERY_PARAMS; |
| 3447 | |
| 3448 | AGESA_STATUS |
| 3449 | AmdInitRecovery ( |
| 3450 | IN OUT AMD_RECOVERY_PARAMS *RecoveryParams |
| 3451 | ); |
| 3452 | |
| 3453 | /********************************************************************** |
| 3454 | * Interface call: AmdInitResume |
| 3455 | **********************************************************************/ |
| 3456 | /// AmdInitResume param structure |
| 3457 | typedef struct { |
| 3458 | IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header |
| 3459 | IN PLATFORM_CONFIGURATION PlatformConfig; ///< Platform operational characteristics |
| 3460 | IN AMD_S3_PARAMS S3DataBlock; ///< Save state data |
| 3461 | } AMD_RESUME_PARAMS; |
| 3462 | |
| 3463 | AGESA_STATUS |
| 3464 | AmdInitResume ( |
| 3465 | IN AMD_RESUME_PARAMS *ResumeParams |
| 3466 | ); |
| 3467 | |
| 3468 | |
| 3469 | /********************************************************************** |
| 3470 | * Interface call: AmdS3LateRestore |
| 3471 | **********************************************************************/ |
| 3472 | /// AmdS3LateRestore param structure |
| 3473 | typedef struct { |
| 3474 | IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header |
| 3475 | IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. |
| 3476 | IN AMD_S3_PARAMS S3DataBlock; ///< Save state data |
| 3477 | } AMD_S3LATE_PARAMS; |
| 3478 | |
| 3479 | AGESA_STATUS |
| 3480 | AmdS3LateRestore ( |
| 3481 | IN OUT AMD_S3LATE_PARAMS *S3LateParams |
| 3482 | ); |
| 3483 | |
| 3484 | |
| 3485 | /********************************************************************** |
| 3486 | * Interface call: AmdS3Save |
| 3487 | **********************************************************************/ |
| 3488 | /// AmdS3Save param structure |
| 3489 | typedef struct { |
| 3490 | IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header |
| 3491 | IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. |
| 3492 | OUT AMD_S3_PARAMS S3DataBlock; ///< Standard header |
| 3493 | IN FCH_INTERFACE FchInterface; ///< FCH configuration |
| 3494 | } AMD_S3SAVE_PARAMS; |
| 3495 | |
| 3496 | AGESA_STATUS |
| 3497 | AmdS3Save ( |
| 3498 | IN OUT AMD_S3SAVE_PARAMS *AmdS3SaveParams |
| 3499 | ); |
| 3500 | |
| 3501 | |
| 3502 | /********************************************************************** |
| 3503 | * Interface call: AmdLateRunApTask |
| 3504 | **********************************************************************/ |
| 3505 | /** |
| 3506 | * Entry point for AP tasking. |
| 3507 | */ |
| 3508 | AGESA_STATUS |
| 3509 | AmdLateRunApTask ( |
| 3510 | IN AP_EXE_PARAMS *AmdApExeParams |
| 3511 | ); |
| 3512 | |
| 3513 | // |
| 3514 | // General Services API |
| 3515 | // |
| 3516 | |
| 3517 | /********************************************************************** |
| 3518 | * Interface service call: AmdGetApicId |
| 3519 | **********************************************************************/ |
| 3520 | /// Request the APIC ID of a particular core. |
| 3521 | |
| 3522 | typedef struct { |
| 3523 | IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header |
| 3524 | IN UINT8 Socket; ///< The Core's Socket. |
| 3525 | IN UINT8 Core; ///< The Core id. |
| 3526 | OUT BOOLEAN IsPresent; ///< The Core is present, and ApicAddress is valid. |
| 3527 | OUT UINT8 ApicAddress; ///< The Core's APIC ID. |
| 3528 | } AMD_APIC_PARAMS; |
| 3529 | |
| 3530 | /** |
| 3531 | * Get a specified Core's APIC ID. |
| 3532 | */ |
| 3533 | AGESA_STATUS |
| 3534 | AmdGetApicId ( |
| 3535 | IN OUT AMD_APIC_PARAMS *AmdParamApic |
| 3536 | ); |
| 3537 | |
| 3538 | /********************************************************************** |
| 3539 | * Interface service call: AmdGetPciAddress |
| 3540 | **********************************************************************/ |
| 3541 | /// Request the PCI Address of a Processor Module (that is, its Northbridge) |
| 3542 | |
| 3543 | typedef struct { |
| 3544 | IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header |
| 3545 | IN UINT8 Socket; ///< The Processor's socket |
| 3546 | IN UINT8 Module; ///< The Module in that Processor |
| 3547 | OUT BOOLEAN IsPresent; ///< The Core is present, and PciAddress is valid. |
| 3548 | OUT PCI_ADDR PciAddress; ///< The Processor's PCI Config Space address (Function 0, Register 0) |
| 3549 | } AMD_GET_PCI_PARAMS; |
| 3550 | |
| 3551 | /** |
| 3552 | * Get Processor Module's PCI Config Space address. |
| 3553 | */ |
| 3554 | AGESA_STATUS |
| 3555 | AmdGetPciAddress ( |
| 3556 | IN OUT AMD_GET_PCI_PARAMS *AmdParamGetPci |
| 3557 | ); |
| 3558 | |
| 3559 | /********************************************************************** |
| 3560 | * Interface service call: AmdIdentifyCore |
| 3561 | **********************************************************************/ |
| 3562 | /// Request the identity (Socket, Module, Core) of the current Processor Core |
| 3563 | |
| 3564 | typedef struct { |
| 3565 | IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header |
| 3566 | OUT UINT8 Socket; ///< The current Core's Socket |
| 3567 | OUT UINT8 Module; ///< The current Core's Processor Module |
| 3568 | OUT UINT8 Core; ///< The current Core's core id. |
| 3569 | } AMD_IDENTIFY_PARAMS; |
| 3570 | |
| 3571 | /** |
| 3572 | * "Who am I" for the current running core. |
| 3573 | */ |
| 3574 | AGESA_STATUS |
| 3575 | AmdIdentifyCore ( |
| 3576 | IN OUT AMD_IDENTIFY_PARAMS *AmdParamIdentify |
| 3577 | ); |
| 3578 | |
| 3579 | /********************************************************************** |
| 3580 | * Interface service call: AmdReadEventLog |
| 3581 | **********************************************************************/ |
| 3582 | /// An Event Log Entry. |
| 3583 | typedef struct { |
| 3584 | IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header |
| 3585 | OUT UINT32 EventClass; ///< The severity of this event, matches AGESA_STATUS. |
| 3586 | OUT UINT32 EventInfo; ///< The unique event identifier, zero means "no event". |
| 3587 | OUT UINT32 DataParam1; ///< Data specific to the Event. |
| 3588 | OUT UINT32 DataParam2; ///< Data specific to the Event. |
| 3589 | OUT UINT32 DataParam3; ///< Data specific to the Event. |
| 3590 | OUT UINT32 DataParam4; ///< Data specific to the Event. |
| 3591 | } EVENT_PARAMS; |
| 3592 | |
| 3593 | /** |
| 3594 | * Read an Event from the Event Log. |
| 3595 | */ |
| 3596 | AGESA_STATUS |
| 3597 | AmdReadEventLog ( |
| 3598 | IN EVENT_PARAMS *Event |
| 3599 | ); |
| 3600 | |
| 3601 | /********************************************************************** |
| 3602 | * Interface service call: AmdIdentifyDimm |
| 3603 | **********************************************************************/ |
| 3604 | /// Request the identity of dimm from system address |
| 3605 | |
| 3606 | typedef struct { |
| 3607 | IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header |
| 3608 | IN UINT64 MemoryAddress; ///< System Address that needs to be translated to dimm identification. |
| 3609 | OUT UINT8 SocketId; ///< The socket on which the targeted address locates. |
| 3610 | OUT UINT8 MemChannelId; ///< The channel on which the targeted address locates. |
| 3611 | OUT UINT8 DimmId; ///< The dimm on which the targeted address locates. |
| 3612 | } AMD_IDENTIFY_DIMM; |
| 3613 | |
| 3614 | /** |
| 3615 | * Get the dimm identification for the address. |
| 3616 | */ |
| 3617 | AGESA_STATUS |
| 3618 | AmdIdentifyDimm ( |
| 3619 | IN OUT AMD_IDENTIFY_DIMM *AmdDimmIdentify |
| 3620 | ); |
| 3621 | |
| 3622 | AGESA_STATUS |
| 3623 | AmdIdsRunApTaskLate ( |
| 3624 | IN AP_EXE_PARAMS *AmdApExeParams |
| 3625 | ); |
| 3626 | |
| 3627 | |
| 3628 | #define AGESA_IDS_DFT_VAL 0xFFFF ///< Default value of every uninitlized NV item, the action for it will be ignored |
| 3629 | #define AGESA_IDS_NV_END 0xFFFF ///< Flag specify end of option structure |
| 3630 | /// WARNING: Don't change the comment below, it used as signature for script |
| 3631 | /// AGESA IDS NV ID Definitions |
| 3632 | typedef enum { |
| 3633 | AGESA_IDS_EXT_ID_START = 0x0000,///< 0x0000 specify the start of external NV id |
| 3634 | |
| 3635 | AGESA_IDS_NV_UCODE, ///< 0x0001 Enable or disable microcode patching |
| 3636 | |
| 3637 | AGESA_IDS_NV_TARGET_PSTATE, ///< 0x0002 Set the P-state required to be activated |
| 3638 | AGESA_IDS_NV_POSTPSTATE, ///< 0x0003 Set the P-state required to be activated through POST |
| 3639 | |
| 3640 | AGESA_IDS_NV_BANK_INTERLEAVE, ///< 0x0004 Enable or disable Bank Interleave |
| 3641 | AGESA_IDS_NV_CHANNEL_INTERLEAVE, ///< 0x0005 Enable or disable Channel Interleave |
| 3642 | AGESA_IDS_NV_NODE_INTERLEAVE, ///< 0x0006 Enable or disable Node Interleave |
| 3643 | AGESA_IDS_NV_MEMHOLE, ///< 0x0007 Enables or disable memory hole |
| 3644 | |
| 3645 | AGESA_IDS_NV_SCRUB_REDIRECTION, ///< 0x0008 Enable or disable a write to dram with corrected data |
| 3646 | AGESA_IDS_NV_DRAM_SCRUB, ///< 0x0009 Set the rate of background scrubbing for DRAM |
| 3647 | AGESA_IDS_NV_DCACHE_SCRUB, ///< 0x000A Set the rate of background scrubbing for the DCache. |
| 3648 | AGESA_IDS_NV_L2_SCRUB, ///< 0x000B Set the rate of background scrubbing for the L2 cache |
| 3649 | AGESA_IDS_NV_L3_SCRUB, ///< 0x000C Set the rate of background scrubbing for the L3 cache |
| 3650 | AGESA_IDS_NV_ICACHE_SCRUB, ///< 0x000D Set the rate of background scrubbing for the Icache |
| 3651 | AGESA_IDS_NV_SYNC_ON_ECC_ERROR, ///< 0x000E Enable or disable the sync flood on un-correctable ECC error |
| 3652 | AGESA_IDS_NV_ECC_SYMBOL_SIZE, ///< 0x000F Set ECC symbol size |
| 3653 | |
| 3654 | AGESA_IDS_NV_ALL_MEMCLKS, ///< 0x0010 Enable or disable all memory clocks enable |
| 3655 | AGESA_IDS_NV_DCT_GANGING_MODE, ///< 0x0011 Set the Ganged mode |
| 3656 | AGESA_IDS_NV_DRAM_BURST_LENGTH32, ///< 0x0012 Set the DRAM Burst Length 32 |
| 3657 | AGESA_IDS_NV_MEMORY_POWER_DOWN, ///< 0x0013 Enable or disable Memory power down mode |
| 3658 | AGESA_IDS_NV_MEMORY_POWER_DOWN_MODE, ///< 0x0014 Set the Memory power down mode |
| 3659 | AGESA_IDS_NV_DLL_SHUT_DOWN, ///< 0x0015 Enable or disable DLLShutdown |
| 3660 | AGESA_IDS_NV_ONLINE_SPARE, ///< 0x0016 Enable or disable the Dram controller to designate a DIMM bank as a spare for logical swap |
| 3661 | |
| 3662 | AGESA_IDS_NV_HT_ASSIST, ///< 0x0017 Enable or Disable HT Assist |
| 3663 | AGESA_IDS_NV_ATMMODE, ///< 0x0018 Enable or Disable ATM mode |
| 3664 | |
| 3665 | AGESA_IDS_NV_HDTOUT, ///< 0x0019 Enable or disable HDTOUT feature |
| 3666 | |
| 3667 | AGESA_IDS_NV_HTLINKSOCKET, ///< 0x001A HT Link Socket |
| 3668 | AGESA_IDS_NV_HTLINKPORT, ///< 0x001B HT Link Port |
| 3669 | AGESA_IDS_NV_HTLINKFREQ, ///< 0x001C HT Link Frequency |
| 3670 | AGESA_IDS_NV_HTLINKWIDTHIN, ///< 0x001D HT Link In Width |
| 3671 | AGESA_IDS_NV_HTLINKWIDTHOUT, ///< 0x001E HT Link Out Width |
| 3672 | |
| 3673 | AGESA_IDS_NV_GNBHDAUDIOEN, ///< 0x001F Enable or disable GNB HD Audio |
| 3674 | |
| 3675 | AGESA_IDS_NV_CPB_EN, ///< 0x0020 Core Performance Boost |
| 3676 | |
| 3677 | AGESA_IDS_NV_HTC_EN, ///< 0x0021 HTC Enable |
| 3678 | AGESA_IDS_NV_HTC_OVERRIDE, ///< 0x0022 HTC Override |
| 3679 | AGESA_IDS_NV_HTC_PSTATE_LIMIT, ///< 0x0023 HTC P-state limit select |
| 3680 | AGESA_IDS_NV_HTC_TEMP_HYS, ///< 0x0024 HTC Temperature Hysteresis |
| 3681 | AGESA_IDS_NV_HTC_ACT_TEMP, ///< 0x0025 HTC Activation Temp |
| 3682 | |
| 3683 | AGESA_IDS_NV_POWER_POLICY, ///< 0x0026 Select Platform Power Policy |
| 3684 | AGESA_IDS_EXT_ID_END, ///< 0x0027 specify the end of external NV ID |
| 3685 | } IDS_EX_NV_ID; |
| 3686 | |
| 3687 | |
| 3688 | #define IDS_NUM_EXT_NV_ITEM (AGESA_IDS_EXT_ID_END - AGESA_IDS_EXT_ID_START + 1) |
| 3689 | |
| 3690 | |
| 3691 | #endif // _AGESA_H_ |