Raul E Rangel | 6b4b4a8 | 2021-05-26 16:58:30 -0600 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
| 3 | #include <acpi/acpi_device.h> |
| 4 | #include <acpi/acpigen.h> |
| 5 | #include <acpi/acpigen_pci.h> |
| 6 | #include <assert.h> |
| 7 | #include <console/console.h> |
| 8 | #include <device/device.h> |
| 9 | #include <device/pci.h> |
| 10 | #include <device/pci_ids.h> |
| 11 | #include <device/pci_ops.h> |
| 12 | #include "chip.h" |
| 13 | |
| 14 | /* |
Raul E Rangel | 6b4b4a8 | 2021-05-26 16:58:30 -0600 | [diff] [blame] | 15 | * Writes the ACPI power resources for a PCI device so it can enter D3Cold. |
| 16 | * |
| 17 | * If the device is a storage class, then the StorageD3Enable _DSD will |
| 18 | * also be added. |
| 19 | * |
| 20 | * e.g., |
| 21 | * |
| 22 | * Scope (\_SB.PCI0.GP14) |
| 23 | * { |
| 24 | * Device (NVME) |
| 25 | * { |
| 26 | * Name (_PR0, Package (0x01) // _PR0: Power Resources for D0 |
| 27 | * { |
| 28 | * PRIC |
| 29 | * }) |
| 30 | * Name (_PR3, Package (0x01) // _PR3: Power Resources for D3hot |
| 31 | * { |
| 32 | * PRIC |
| 33 | * }) |
| 34 | * PowerResource (PRIC, 0x00, 0x0000) |
| 35 | * { |
| 36 | * Method (_STA, 0, NotSerialized) // _STA: Status |
| 37 | * { |
| 38 | * ... |
| 39 | * } |
| 40 | * |
| 41 | * Method (_ON, 0, Serialized) // _ON_: Power On |
| 42 | * { |
| 43 | * ... |
| 44 | * } |
| 45 | * |
| 46 | * Method (_OFF, 0, Serialized) // _OFF: Power Off |
| 47 | * { |
| 48 | * ... |
| 49 | * } |
| 50 | * } |
| 51 | * |
| 52 | * Name (_ADR, 0x0000000000000000) // _ADR: Address |
| 53 | * Method (_STA, 0, NotSerialized) // _STA: Status |
| 54 | * { |
| 55 | * Return (0x0F) |
| 56 | * } |
| 57 | * |
| 58 | * Name (_DSD, Package (0x02) // _DSD: Device-Specific Data |
| 59 | * { |
| 60 | * ToUUID ("5025030f-842f-4ab4-a561-99a5189762d0"), |
| 61 | * Package (0x01) |
| 62 | * { |
| 63 | * Package (0x02) |
| 64 | * { |
| 65 | * "StorageD3Enable", |
| 66 | * One |
| 67 | * } |
| 68 | * } |
| 69 | * }) |
| 70 | * } |
| 71 | * } |
| 72 | */ |
| 73 | static void pcie_rtd3_device_acpi_fill_ssdt(const struct device *dev) |
| 74 | { |
Raul E Rangel | 6b4b4a8 | 2021-05-26 16:58:30 -0600 | [diff] [blame] | 75 | const struct drivers_pcie_rtd3_device_config *config = config_of(dev); |
| 76 | /* Copy the GPIOs to avoid discards 'const' qualifier error */ |
| 77 | struct acpi_gpio reset_gpio = config->reset_gpio; |
| 78 | struct acpi_gpio enable_gpio = config->enable_gpio; |
| 79 | const struct acpi_power_res_params power_res_params = { |
| 80 | .reset_gpio = &reset_gpio, |
| 81 | .reset_delay_ms = config->reset_delay_ms, |
| 82 | .reset_off_delay_ms = config->reset_off_delay_ms, |
| 83 | .enable_gpio = &enable_gpio, |
| 84 | .enable_delay_ms = config->enable_delay_ms, |
| 85 | .enable_off_delay_ms = config->enable_off_delay_ms, |
| 86 | .use_gpio_for_status = true, |
| 87 | }; |
| 88 | const char *scope = acpi_device_scope(dev); |
| 89 | const char *name = acpi_device_name(dev); |
| 90 | |
| 91 | assert(name); |
| 92 | assert(scope); |
| 93 | |
| 94 | printk(BIOS_INFO, "%s.%s: Enable RTD3 for %s (%s)\n", scope, name, dev_path(dev), |
| 95 | dev->chip_ops->name); |
| 96 | |
| 97 | acpigen_write_scope(scope); |
| 98 | acpigen_write_device(acpi_device_name(dev)); |
| 99 | |
| 100 | acpi_device_add_power_res(&power_res_params); |
| 101 | |
| 102 | acpigen_write_ADR_pci_device(dev); |
| 103 | acpigen_write_STA(acpi_device_status(dev)); |
| 104 | |
| 105 | /* Storage devices won't enter D3 without this property */ |
| 106 | if ((dev->class >> 16) == PCI_BASE_CLASS_STORAGE) { |
Kapil Porwal | 65bcb57 | 2022-11-28 18:53:40 +0530 | [diff] [blame] | 107 | acpi_device_add_storage_d3_enable(NULL); |
Raul E Rangel | 6b4b4a8 | 2021-05-26 16:58:30 -0600 | [diff] [blame] | 108 | |
| 109 | printk(BIOS_INFO, "%s.%s: Added StorageD3Enable property\n", scope, name); |
| 110 | } |
| 111 | |
| 112 | acpigen_write_device_end(); |
| 113 | acpigen_write_scope_end(); |
| 114 | |
| 115 | /* Call the default PCI acpi_fill_ssdt */ |
| 116 | pci_rom_ssdt(dev); |
| 117 | } |
| 118 | |
| 119 | static const char *pcie_rtd3_device_acpi_name(const struct device *dev) |
| 120 | { |
| 121 | const struct drivers_pcie_rtd3_device_config *config = config_of(dev); |
| 122 | |
| 123 | return config->name; |
| 124 | } |
| 125 | |
| 126 | static struct device_operations pcie_rtd3_device_ops = { |
| 127 | .read_resources = pci_dev_read_resources, |
| 128 | .set_resources = pci_dev_set_resources, |
| 129 | .enable_resources = pci_dev_enable_resources, |
| 130 | .init = pci_dev_init, |
| 131 | .ops_pci = &pci_dev_ops_pci, |
| 132 | .write_acpi_tables = pci_rom_write_acpi_tables, |
| 133 | .acpi_fill_ssdt = pcie_rtd3_device_acpi_fill_ssdt, |
| 134 | .acpi_name = pcie_rtd3_device_acpi_name, |
| 135 | }; |
| 136 | |
| 137 | static void pcie_rtd3_device_enable(struct device *dev) |
| 138 | { |
| 139 | struct drivers_pcie_rtd3_device_config *config = dev ? dev->chip_info : NULL; |
| 140 | |
| 141 | if (!config) |
| 142 | return; |
| 143 | |
| 144 | if (dev->path.type != DEVICE_PATH_PCI) { |
| 145 | printk(BIOS_ERR, "%s: Invalid device type\n", dev_path(dev)); |
| 146 | return; |
| 147 | } |
| 148 | |
| 149 | dev->ops = &pcie_rtd3_device_ops; |
| 150 | } |
| 151 | |
| 152 | struct chip_operations drivers_pcie_rtd3_device_ops = { |
| 153 | CHIP_NAME("PCIe Device w/ Runtime D3") |
| 154 | .enable_dev = pcie_rtd3_device_enable |
| 155 | }; |