Angel Pons | f94ac9a | 2020-04-05 15:46:48 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 2 | |
Kyösti Mälkki | de64078 | 2019-12-03 07:30:26 +0200 | [diff] [blame] | 3 | #include <arch/bootblock.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 4 | #include <device/pci_ops.h> |
Julius Werner | 4ee4bd5 | 2014-10-20 13:46:39 -0700 | [diff] [blame] | 5 | #include <soc/pci_devs.h> |
| 6 | #include <soc/systemagent.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 7 | |
Arthur Heymans | 5bb15f1 | 2018-12-22 16:02:25 +0100 | [diff] [blame] | 8 | void bootblock_early_northbridge_init(void) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 9 | { |
| 10 | uint32_t reg; |
| 11 | |
| 12 | /* |
| 13 | * The "io" variant of the config access is explicitly used to |
Martin Roth | f48acbd | 2020-07-24 12:24:27 -0600 | [diff] [blame^] | 14 | * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 15 | * to true. That way all subsequent non-explicit config accesses use |
| 16 | * MCFG. This code also assumes that bootblock_northbridge_init() is |
| 17 | * the first thing called in the non-asm boot block code. The final |
| 18 | * assumption is that no assembly code is using the |
Martin Roth | f48acbd | 2020-07-24 12:24:27 -0600 | [diff] [blame^] | 19 | * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses. |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 20 | * |
| 21 | * The PCIEXBAR is assumed to live in the memory mapped IO space under |
| 22 | * 4GiB. |
| 23 | */ |
| 24 | reg = 0; |
| 25 | pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, reg); |
| 26 | reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ |
| 27 | pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR, reg); |
| 28 | } |