Angel Pons | 585495e | 2020-04-03 01:21:38 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Martin Roth | b28f466 | 2018-05-26 17:58:47 -0600 | [diff] [blame] | 2 | |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 3 | #include <device/pci_ops.h> |
Patrick Rudolph | 1af8923 | 2018-11-11 12:50:51 +0100 | [diff] [blame] | 4 | #include <bootblock_common.h> |
Angel Pons | 22a6d11 | 2020-06-21 18:50:22 +0200 | [diff] [blame] | 5 | #include <southbridge/intel/common/early_spi.h> |
Patrick Rudolph | 1af8923 | 2018-11-11 12:50:51 +0100 | [diff] [blame] | 6 | #include <southbridge/intel/i82801ix/i82801ix.h> |
Patrick Rudolph | fbdeb4a | 2019-02-14 19:47:03 +0100 | [diff] [blame] | 7 | #include <console/console.h> |
Kyösti Mälkki | b9646a2 | 2013-07-03 08:06:32 +0300 | [diff] [blame] | 8 | |
| 9 | /* Just define these here, there is no gm35.h file to include. */ |
| 10 | #define D0F0_PCIEXBAR_LO 0x60 |
| 11 | #define D0F0_PCIEXBAR_HI 0x64 |
| 12 | |
| 13 | static void bootblock_northbridge_init(void) |
| 14 | { |
| 15 | uint32_t reg; |
| 16 | |
| 17 | /* |
| 18 | * The "io" variant of the config access is explicitly used to |
Martin Roth | f48acbd | 2020-07-24 12:24:27 -0600 | [diff] [blame^] | 19 | * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to |
Kyösti Mälkki | b9646a2 | 2013-07-03 08:06:32 +0300 | [diff] [blame] | 20 | * to true. That way all subsequent non-explicit config accesses use |
| 21 | * MCFG. This code also assumes that bootblock_northbridge_init() is |
| 22 | * the first thing called in the non-asm boot block code. The final |
| 23 | * assumption is that no assembly code is using the |
Martin Roth | f48acbd | 2020-07-24 12:24:27 -0600 | [diff] [blame^] | 24 | * CONFIG(MMCONF_SUPPORT) option to do PCI config acceses. |
Kyösti Mälkki | b9646a2 | 2013-07-03 08:06:32 +0300 | [diff] [blame] | 25 | * |
| 26 | * The PCIEXBAR is assumed to live in the memory mapped IO space under |
| 27 | * 4GiB. |
| 28 | */ |
| 29 | reg = 0; |
| 30 | pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_HI, reg); |
| 31 | reg = CONFIG_MMCONF_BASE_ADDRESS | 1; /* 256MiB - 0-255 buses. */ |
| 32 | pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_LO, reg); |
Patrick Rudolph | fbdeb4a | 2019-02-14 19:47:03 +0100 | [diff] [blame] | 33 | |
| 34 | /* MCFG is now active. If it's not qemu was started for machine PC */ |
| 35 | if (CONFIG(BOOTBLOCK_CONSOLE) && |
| 36 | (pci_read_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO) != |
| 37 | (CONFIG_MMCONF_BASE_ADDRESS | 1))) |
| 38 | die("You must run qemu for machine Q35 (-M q35)"); |
Kyösti Mälkki | b9646a2 | 2013-07-03 08:06:32 +0300 | [diff] [blame] | 39 | } |
| 40 | |
Patrick Rudolph | 1af8923 | 2018-11-11 12:50:51 +0100 | [diff] [blame] | 41 | static void bootblock_southbridge_init(void) |
| 42 | { |
Angel Pons | 22a6d11 | 2020-06-21 18:50:22 +0200 | [diff] [blame] | 43 | enable_spi_prefetching_and_caching(); |
Patrick Rudolph | 1af8923 | 2018-11-11 12:50:51 +0100 | [diff] [blame] | 44 | |
| 45 | /* Enable RCBA */ |
Peter Lemenkov | 7b42811 | 2018-10-23 11:12:46 +0200 | [diff] [blame] | 46 | pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, |
Patrick Rudolph | 1af8923 | 2018-11-11 12:50:51 +0100 | [diff] [blame] | 47 | (uintptr_t)DEFAULT_RCBA | 1); |
| 48 | } |
| 49 | |
| 50 | void bootblock_soc_init(void) |
Kyösti Mälkki | b9646a2 | 2013-07-03 08:06:32 +0300 | [diff] [blame] | 51 | { |
| 52 | bootblock_northbridge_init(); |
| 53 | bootblock_southbridge_init(); |
| 54 | } |