Angel Pons | 3bd1e3d | 2020-04-05 15:47:17 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 2 | |
| 3 | /* |
| 4 | * Helper functions for dealing with power management registers |
| 5 | * and the differences between PCH variants. |
| 6 | */ |
| 7 | |
Angel Pons | a15a604 | 2021-02-19 17:34:26 +0100 | [diff] [blame] | 8 | #define __SIMPLE_DEVICE__ |
| 9 | |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 10 | #include <acpi/acpi.h> |
Dinesh Gehlot | 770a46c | 2023-01-17 05:54:17 +0000 | [diff] [blame] | 11 | #include <console/console.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 12 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 13 | #include <device/pci_ops.h> |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 14 | #include <device/device.h> |
| 15 | #include <device/pci.h> |
Dinesh Gehlot | 770a46c | 2023-01-17 05:54:17 +0000 | [diff] [blame] | 16 | #include <gpio.h> |
Shaunak Saha | d347680 | 2017-07-08 01:08:40 -0700 | [diff] [blame] | 17 | #include <intelblocks/pmclib.h> |
Ravi Sarawadi | 1483d1f | 2017-09-28 17:06:01 -0700 | [diff] [blame] | 18 | #include <intelblocks/lpc_lib.h> |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 19 | #include <intelblocks/tco.h> |
Duncan Laurie | f0ba225 | 2016-10-25 20:03:56 -0700 | [diff] [blame] | 20 | #include <soc/gpe.h> |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 21 | #include <soc/iomap.h> |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 22 | #include <soc/pci_devs.h> |
| 23 | #include <soc/pm.h> |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 24 | #include <soc/pmc.h> |
| 25 | #include <soc/smbus.h> |
Philipp Deppenwiese | fea2429 | 2017-10-17 17:02:29 +0200 | [diff] [blame] | 26 | #include <security/vboot/vbnv.h> |
Elyes HAOUAS | add76f9 | 2019-03-21 09:55:49 +0100 | [diff] [blame] | 27 | |
Duncan Laurie | f0ba225 | 2016-10-25 20:03:56 -0700 | [diff] [blame] | 28 | #include "chip.h" |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 29 | |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 30 | /* |
| 31 | * SMI |
| 32 | */ |
| 33 | |
Shaunak Saha | d347680 | 2017-07-08 01:08:40 -0700 | [diff] [blame] | 34 | const char *const *soc_smi_sts_array(size_t *smi_arr) |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 35 | { |
Shaunak Saha | d347680 | 2017-07-08 01:08:40 -0700 | [diff] [blame] | 36 | static const char *const smi_sts_bits[] = { |
Angel Pons | df8462c | 2021-02-19 16:35:45 +0100 | [diff] [blame] | 37 | [BIOS_STS_BIT] = "BIOS", |
| 38 | [LEGACY_USB_STS_BIT] = "LEGACY_USB", |
| 39 | [SMI_ON_SLP_EN_STS_BIT] = "SLP_SMI", |
| 40 | [APM_STS_BIT] = "APM", |
| 41 | [SWSMI_TMR_STS_BIT] = "SWSMI_TMR", |
| 42 | [PM1_STS_BIT] = "PM1", |
| 43 | [GPE0_STS_BIT] = "GPE0", |
| 44 | [GPIO_STS_BIT] = "GPI", |
| 45 | [MCSMI_STS_BIT] = "MCSMI", |
| 46 | [DEVMON_STS_BIT] = "DEVMON", |
| 47 | [TCO_STS_BIT] = "TCO", |
| 48 | [PERIODIC_STS_BIT] = "PERIODIC", |
| 49 | [SERIRQ_SMI_STS_BIT] = "SERIRQ_SMI", |
| 50 | [SMBUS_SMI_STS_BIT] = "SMBUS_SMI", |
| 51 | [PCI_EXP_SMI_STS_BIT] = "PCI_EXP_SMI", |
| 52 | [MONITOR_STS_BIT] = "MONITOR", |
| 53 | [SPI_SMI_STS_BIT] = "SPI", |
| 54 | [GPIO_UNLOCK_SMI_STS_BIT] = "GPIO_UNLOCK", |
| 55 | [ESPI_SMI_STS_BIT] = "ESPI_SMI", |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 56 | }; |
| 57 | |
Shaunak Saha | d347680 | 2017-07-08 01:08:40 -0700 | [diff] [blame] | 58 | *smi_arr = ARRAY_SIZE(smi_sts_bits); |
| 59 | return smi_sts_bits; |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 60 | } |
| 61 | |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 62 | /* |
| 63 | * TCO |
| 64 | */ |
| 65 | |
Shaunak Saha | d347680 | 2017-07-08 01:08:40 -0700 | [diff] [blame] | 66 | const char *const *soc_tco_sts_array(size_t *tco_arr) |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 67 | { |
Shaunak Saha | d347680 | 2017-07-08 01:08:40 -0700 | [diff] [blame] | 68 | static const char *const tco_sts_bits[] = { |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 69 | [0] = "NMI2SMI", |
| 70 | [1] = "SW_TCO", |
| 71 | [2] = "TCO_INT", |
| 72 | [3] = "TIMEOUT", |
| 73 | [7] = "NEWCENTURY", |
| 74 | [8] = "BIOSWR", |
| 75 | [9] = "DMISCI", |
| 76 | [10] = "DMISMI", |
| 77 | [12] = "DMISERR", |
| 78 | [13] = "SLVSEL", |
| 79 | [16] = "INTRD_DET", |
| 80 | [17] = "SECOND_TO", |
| 81 | [18] = "BOOT", |
| 82 | [20] = "SMLINK_SLV" |
| 83 | }; |
| 84 | |
Shaunak Saha | d347680 | 2017-07-08 01:08:40 -0700 | [diff] [blame] | 85 | *tco_arr = ARRAY_SIZE(tco_sts_bits); |
| 86 | return tco_sts_bits; |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 87 | } |
| 88 | |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 89 | /* |
| 90 | * GPE0 |
| 91 | */ |
| 92 | |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 93 | const char *const *soc_std_gpe_sts_array(size_t *gpe_arr) |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 94 | { |
Shaunak Saha | d347680 | 2017-07-08 01:08:40 -0700 | [diff] [blame] | 95 | static const char *const gpe_sts_bits[] = { |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 96 | [1] = "HOTPLUG", |
| 97 | [2] = "SWGPE", |
| 98 | [6] = "TCO_SCI", |
| 99 | [7] = "SMB_WAK", |
| 100 | [9] = "PCI_EXP", |
| 101 | [10] = "BATLOW", |
| 102 | [11] = "PME", |
| 103 | [12] = "ME", |
| 104 | [13] = "PME_B0", |
Aaron Durbin | 7f78849 | 2015-07-24 17:10:31 -0500 | [diff] [blame] | 105 | [14] = "eSPI", |
| 106 | [15] = "GPIO Tier-2", |
| 107 | [16] = "LAN_WAKE", |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 108 | [18] = "WADT" |
| 109 | }; |
| 110 | |
Shaunak Saha | d347680 | 2017-07-08 01:08:40 -0700 | [diff] [blame] | 111 | *gpe_arr = ARRAY_SIZE(gpe_sts_bits); |
| 112 | return gpe_sts_bits; |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 113 | } |
| 114 | |
Angel Pons | f643b63 | 2021-04-17 12:55:59 +0200 | [diff] [blame] | 115 | void pmc_set_disb(void) |
| 116 | { |
| 117 | /* Set the DISB after DRAM init */ |
| 118 | u32 disb_val; |
| 119 | const pci_devfn_t dev = PCH_DEV_PMC; |
| 120 | |
| 121 | disb_val = pci_read_config32(dev, GEN_PMCON_A); |
| 122 | disb_val |= DISB; |
| 123 | |
| 124 | /* Don't clear bits that are write-1-to-clear */ |
| 125 | disb_val &= ~(GBL_RST_STS | MS4V); |
| 126 | pci_write_config32(dev, GEN_PMCON_A, disb_val); |
| 127 | } |
| 128 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 129 | uint8_t *pmc_mmio_regs(void) |
| 130 | { |
| 131 | uint32_t reg32; |
| 132 | |
| 133 | reg32 = pci_read_config32(PCH_DEV_PMC, PWRMBASE); |
| 134 | |
| 135 | /* 4KiB alignment. */ |
| 136 | reg32 &= ~0xfff; |
| 137 | |
Elyes Haouas | 9018dee | 2022-11-18 15:07:33 +0100 | [diff] [blame] | 138 | return (void *)(uintptr_t)reg32; |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 139 | } |
| 140 | |
Shaunak Saha | d347680 | 2017-07-08 01:08:40 -0700 | [diff] [blame] | 141 | uintptr_t soc_read_pmc_base(void) |
| 142 | { |
Elyes Haouas | 9018dee | 2022-11-18 15:07:33 +0100 | [diff] [blame] | 143 | return (uintptr_t)(pmc_mmio_regs()); |
Shaunak Saha | d347680 | 2017-07-08 01:08:40 -0700 | [diff] [blame] | 144 | } |
| 145 | |
Michael Niewöhner | 35e76dd | 2019-11-02 12:14:06 +0100 | [diff] [blame] | 146 | uint32_t *soc_pmc_etr_addr(void) |
| 147 | { |
| 148 | /* |
| 149 | * The pointer returned must not be cached, because the address depends on the |
| 150 | * MMCONF base address and the assigned PCI bus number, which both may change |
| 151 | * during the boot process! |
| 152 | */ |
| 153 | return pci_mmio_config32_addr(PCH_DEVFN_PMC << 12, ETR); |
| 154 | } |
| 155 | |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 156 | void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) |
Duncan Laurie | f0ba225 | 2016-10-25 20:03:56 -0700 | [diff] [blame] | 157 | { |
Aaron Durbin | e4d7abc | 2017-04-16 22:05:36 -0500 | [diff] [blame] | 158 | DEVTREE_CONST struct soc_intel_skylake_config *config; |
Duncan Laurie | f0ba225 | 2016-10-25 20:03:56 -0700 | [diff] [blame] | 159 | |
Kyösti Mälkki | d5f645c | 2019-09-28 00:20:27 +0300 | [diff] [blame] | 160 | config = config_of_soc(); |
Duncan Laurie | f0ba225 | 2016-10-25 20:03:56 -0700 | [diff] [blame] | 161 | |
Shaunak Saha | d347680 | 2017-07-08 01:08:40 -0700 | [diff] [blame] | 162 | /* Assign to out variable */ |
| 163 | *dw0 = config->gpe0_dw0; |
| 164 | *dw1 = config->gpe0_dw1; |
| 165 | *dw2 = config->gpe0_dw2; |
Duncan Laurie | f0ba225 | 2016-10-25 20:03:56 -0700 | [diff] [blame] | 166 | } |
Aaron Durbin | d1fc8c1 | 2017-09-15 12:37:05 -0600 | [diff] [blame] | 167 | |
| 168 | int rtc_failure(void) |
| 169 | { |
| 170 | u8 reg8; |
| 171 | int rtc_failed; |
| 172 | /* PMC Controller Device 0x1F, Func 02 */ |
Angel Pons | a15a604 | 2021-02-19 17:34:26 +0100 | [diff] [blame] | 173 | const pci_devfn_t dev = PCH_DEV_PMC; |
| 174 | |
Aaron Durbin | d1fc8c1 | 2017-09-15 12:37:05 -0600 | [diff] [blame] | 175 | reg8 = pci_read_config8(dev, GEN_PMCON_B); |
| 176 | rtc_failed = reg8 & RTC_BATTERY_DEAD; |
| 177 | if (rtc_failed) { |
| 178 | reg8 &= ~RTC_BATTERY_DEAD; |
| 179 | pci_write_config8(dev, GEN_PMCON_B, reg8); |
| 180 | printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); |
| 181 | } |
| 182 | |
| 183 | return !!rtc_failed; |
| 184 | } |
Aaron Durbin | 0990fbf | 2017-09-15 15:23:04 -0600 | [diff] [blame] | 185 | |
| 186 | int vbnv_cmos_failed(void) |
| 187 | { |
| 188 | return rtc_failure(); |
| 189 | } |
Furquan Shaikh | 3efeeb2 | 2017-10-14 19:24:43 -0700 | [diff] [blame] | 190 | |
| 191 | /* Return 0, 3, or 5 to indicate the previous sleep state. */ |
Angel Pons | f5d090d | 2021-02-19 17:49:00 +0100 | [diff] [blame] | 192 | int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state) |
Furquan Shaikh | 3efeeb2 | 2017-10-14 19:24:43 -0700 | [diff] [blame] | 193 | { |
| 194 | /* |
| 195 | * Check for any power failure to determine if this a wake from |
| 196 | * S5 because the PCH does not set the WAK_STS bit when waking |
| 197 | * from a true G3 state. |
| 198 | */ |
| 199 | if (!(ps->pm1_sts & WAK_STS) && |
| 200 | (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR))) |
| 201 | prev_sleep_state = ACPI_S5; |
| 202 | |
| 203 | /* |
| 204 | * If waking from S3 determine if deep S3 is enabled. If not, |
| 205 | * need to check both deep sleep well and normal suspend well. |
| 206 | * Otherwise just check deep sleep well. |
| 207 | */ |
| 208 | if (prev_sleep_state == ACPI_S3) { |
| 209 | /* PWR_FLR represents deep sleep power well loss. */ |
| 210 | uint32_t mask = PWR_FLR; |
| 211 | |
| 212 | /* If deep s3 isn't enabled check the suspend well too. */ |
| 213 | if (!deep_s3_enabled()) |
| 214 | mask |= SUS_PWR_FLR; |
| 215 | |
| 216 | if (ps->gen_pmcon_b & mask) |
| 217 | prev_sleep_state = ACPI_S5; |
| 218 | } |
| 219 | return prev_sleep_state; |
| 220 | } |
| 221 | |
| 222 | void soc_fill_power_state(struct chipset_power_state *ps) |
| 223 | { |
Furquan Shaikh | 3efeeb2 | 2017-10-14 19:24:43 -0700 | [diff] [blame] | 224 | uint8_t *pmc; |
| 225 | |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 226 | ps->tco1_sts = tco_read_reg(TCO1_STS); |
| 227 | ps->tco2_sts = tco_read_reg(TCO2_STS); |
Furquan Shaikh | 3efeeb2 | 2017-10-14 19:24:43 -0700 | [diff] [blame] | 228 | |
Angel Pons | f5d090d | 2021-02-19 17:49:00 +0100 | [diff] [blame] | 229 | printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts); |
Furquan Shaikh | 3efeeb2 | 2017-10-14 19:24:43 -0700 | [diff] [blame] | 230 | |
| 231 | ps->gen_pmcon_a = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_A); |
| 232 | ps->gen_pmcon_b = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_B); |
| 233 | |
| 234 | pmc = pmc_mmio_regs(); |
| 235 | ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0); |
| 236 | ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1); |
| 237 | |
| 238 | printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n", |
| 239 | ps->gen_pmcon_a, ps->gen_pmcon_b); |
| 240 | |
| 241 | printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", |
| 242 | ps->gblrst_cause[0], ps->gblrst_cause[1]); |
| 243 | } |
Eugene Myers | ebc8423 | 2020-01-21 16:46:16 -0500 | [diff] [blame] | 244 | |
| 245 | /* STM Support */ |
| 246 | uint16_t get_pmbase(void) |
| 247 | { |
| 248 | return ACPI_BASE_ADDRESS; |
| 249 | } |
Angel Pons | 505e383 | 2021-04-17 13:02:37 +0200 | [diff] [blame] | 250 | |
| 251 | /* |
| 252 | * Set which power state system will be after reapplying |
| 253 | * the power (from G3 State) |
| 254 | */ |
| 255 | void pmc_soc_set_afterg3_en(const bool on) |
| 256 | { |
| 257 | uint8_t reg8; |
| 258 | const pci_devfn_t dev = PCH_DEV_PMC; |
| 259 | |
| 260 | reg8 = pci_read_config8(dev, GEN_PMCON_B); |
| 261 | if (on) |
| 262 | reg8 &= ~SLEEP_AFTER_POWER_FAIL; |
| 263 | else |
| 264 | reg8 |= SLEEP_AFTER_POWER_FAIL; |
| 265 | pci_write_config8(dev, GEN_PMCON_B, reg8); |
| 266 | } |