blob: b5f5f2ad74378a0e884d22bd5c4999f899136773 [file] [log] [blame]
Martin Roth9231f0b2022-10-28 22:39:23 -06001## SPDX-License-Identifier: GPL-2.0-only
Tan, Lean Sheng05dfe312020-08-25 20:40:17 -07002ifeq ($(CONFIG_SOC_INTEL_ELKHARTLAKE),y)
3
4subdirs-y += romstage
5subdirs-y += ../../../cpu/intel/microcode
6subdirs-y += ../../../cpu/intel/turbo
Tan, Lean Sheng05dfe312020-08-25 20:40:17 -07007
8# all (bootblock, verstage, romstage, postcar, ramstage)
9all-y += gspi.c
10all-y += i2c.c
11all-y += pmutil.c
12all-y += spi.c
13all-y += uart.c
14
15bootblock-y += bootblock/bootblock.c
Tan, Lean Sheng05dfe312020-08-25 20:40:17 -070016bootblock-y += bootblock/pch.c
17bootblock-y += bootblock/report_platform.c
18bootblock-y += espi.c
19bootblock-y += gpio.c
20bootblock-y += p2sb.c
21
22romstage-y += espi.c
23romstage-y += gpio.c
24romstage-y += meminit.c
Nico Huber8b4677f2024-01-12 16:22:19 +010025romstage-y += pcie_rp.c
Tan, Lean Sheng05dfe312020-08-25 20:40:17 -070026romstage-y += reset.c
27
28ramstage-y += acpi.c
29ramstage-y += chip.c
30ramstage-y += cpu.c
Tan, Lean Sheng05dfe312020-08-25 20:40:17 -070031ramstage-y += espi.c
32ramstage-y += finalize.c
33ramstage-y += fsp_params.c
34ramstage-y += gpio.c
35ramstage-y += lockdown.c
36ramstage-y += p2sb.c
Nico Huber8b4677f2024-01-12 16:22:19 +010037ramstage-y += pcie_rp.c
Tan, Lean Sheng05dfe312020-08-25 20:40:17 -070038ramstage-y += pmc.c
39ramstage-y += reset.c
Tan, Lean Sheng05dfe312020-08-25 20:40:17 -070040ramstage-y += systemagent.c
41ramstage-y += sd.c
Mario Scheithauereda66c32022-04-26 13:50:52 +020042ramstage-$(CONFIG_EHL_TSN_DRIVER) += tsn_gbe.c
Tan, Lean Sheng05dfe312020-08-25 20:40:17 -070043
44smm-y += gpio.c
45smm-y += p2sb.c
Tan, Lean Sheng05dfe312020-08-25 20:40:17 -070046smm-y += pmutil.c
47smm-y += smihandler.c
48smm-y += uart.c
49
50verstage-y += gpio.c
51
52CPPFLAGS_common += -I$(src)/soc/intel/elkhartlake
53CPPFLAGS_common += -I$(src)/soc/intel/elkhartlake/include
54
Arthur Heymansed8081c2021-12-11 14:23:31 +010055# B0 stepping
56cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-96-01
Lean Sheng Tan5cd75792021-06-09 13:58:12 -070057cbfs-files-$(CONFIG_ADD_PSE_IMAGE_TO_CBFS) += pse.bin
58pse.bin-file := $(CONFIG_PSE_IMAGE_FILE)
59pse.bin-type := raw
60pse.bin-compression := lzma
61
62# Add a build time check if the PSE file size fits
63ifeq ($(CONFIG_ADD_PSE_IMAGE_TO_CBFS),y)
64ifeq ($(call int-gt,\
65 $(call file-size,$(CONFIG_PSE_IMAGE_FILE))\
66 $(shell printf "%d" $(call int-shift-left, $(CONFIG_PSE_FW_FILE_SIZE_KIB) 10))), 1)
67$(error PSE binary larger than CONFIG_PSE_FW_FILE_SIZE_KIB.)
68endif
69endif # CONFIG_ADD_PSE_IMAGE_TO_CBFS
Arthur Heymansed8081c2021-12-11 14:23:31 +010070
Tan, Lean Sheng05dfe312020-08-25 20:40:17 -070071endif