Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | /* |
| 21 | * This is a ramstage driver for the Intel Management Engine found in the |
| 22 | * southbridge. It handles the required boot-time messages over the |
| 23 | * MMIO-based Management Engine Interface to tell the ME that the BIOS is |
| 24 | * finished with POST. Additional messages are defined for debug but are |
| 25 | * not used unless the console loglevel is high enough. |
| 26 | */ |
| 27 | |
| 28 | #include <arch/acpi.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 29 | #include <arch/io.h> |
| 30 | #include <console/console.h> |
| 31 | #include <device/device.h> |
| 32 | #include <device/pci.h> |
| 33 | #include <device/pci_ids.h> |
| 34 | #include <device/pci_def.h> |
| 35 | #include <string.h> |
| 36 | #include <delay.h> |
| 37 | #include <elog.h> |
| 38 | #include <broadwell/me.h> |
| 39 | #include <broadwell/lpc.h> |
| 40 | #include <broadwell/pch.h> |
| 41 | #include <broadwell/pci_devs.h> |
| 42 | #include <broadwell/ramstage.h> |
| 43 | #include <broadwell/rcba.h> |
| 44 | #include <chip.h> |
| 45 | |
| 46 | #if CONFIG_CHROMEOS |
| 47 | #include <vendorcode/google/chromeos/chromeos.h> |
| 48 | #include <vendorcode/google/chromeos/gnvs.h> |
| 49 | #endif |
| 50 | |
| 51 | /* Path that the BIOS should take based on ME state */ |
| 52 | static const char *me_bios_path_values[] = { |
| 53 | [ME_NORMAL_BIOS_PATH] = "Normal", |
| 54 | [ME_S3WAKE_BIOS_PATH] = "S3 Wake", |
| 55 | [ME_ERROR_BIOS_PATH] = "Error", |
| 56 | [ME_RECOVERY_BIOS_PATH] = "Recovery", |
| 57 | [ME_DISABLE_BIOS_PATH] = "Disable", |
| 58 | [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", |
| 59 | }; |
| 60 | static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev); |
| 61 | |
| 62 | /* MMIO base address for MEI interface */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 63 | static u8 *mei_base_address; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 64 | void intel_me_mbp_clear(device_t dev); |
| 65 | |
| 66 | #if CONFIG_DEBUG_INTEL_ME |
| 67 | static void mei_dump(void *ptr, int dword, int offset, const char *type) |
| 68 | { |
| 69 | struct mei_csr *csr; |
| 70 | |
| 71 | printk(BIOS_SPEW, "%-9s[%02x] : ", type, offset); |
| 72 | |
| 73 | switch (offset) { |
| 74 | case MEI_H_CSR: |
| 75 | case MEI_ME_CSR_HA: |
| 76 | csr = ptr; |
| 77 | if (!csr) { |
| 78 | printk(BIOS_SPEW, "ERROR: 0x%08x\n", dword); |
| 79 | break; |
| 80 | } |
| 81 | printk(BIOS_SPEW, "cbd=%u cbrp=%02u cbwp=%02u ready=%u " |
| 82 | "reset=%u ig=%u is=%u ie=%u\n", csr->buffer_depth, |
| 83 | csr->buffer_read_ptr, csr->buffer_write_ptr, |
| 84 | csr->ready, csr->reset, csr->interrupt_generate, |
| 85 | csr->interrupt_status, csr->interrupt_enable); |
| 86 | break; |
| 87 | case MEI_ME_CB_RW: |
| 88 | case MEI_H_CB_WW: |
| 89 | printk(BIOS_SPEW, "CB: 0x%08x\n", dword); |
| 90 | break; |
| 91 | default: |
| 92 | printk(BIOS_SPEW, "0x%08x\n", offset); |
| 93 | break; |
| 94 | } |
| 95 | } |
| 96 | #else |
| 97 | # define mei_dump(ptr,dword,offset,type) do {} while (0) |
| 98 | #endif |
| 99 | |
| 100 | /* |
| 101 | * ME/MEI access helpers using memcpy to avoid aliasing. |
| 102 | */ |
| 103 | |
| 104 | static inline void mei_read_dword_ptr(void *ptr, int offset) |
| 105 | { |
| 106 | u32 dword = read32(mei_base_address + offset); |
| 107 | memcpy(ptr, &dword, sizeof(dword)); |
| 108 | mei_dump(ptr, dword, offset, "READ"); |
| 109 | } |
| 110 | |
| 111 | static inline void mei_write_dword_ptr(void *ptr, int offset) |
| 112 | { |
| 113 | u32 dword = 0; |
| 114 | memcpy(&dword, ptr, sizeof(dword)); |
| 115 | write32(mei_base_address + offset, dword); |
| 116 | mei_dump(ptr, dword, offset, "WRITE"); |
| 117 | } |
| 118 | |
| 119 | static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset) |
| 120 | { |
| 121 | u32 dword = pci_read_config32(dev, offset); |
| 122 | memcpy(ptr, &dword, sizeof(dword)); |
| 123 | mei_dump(ptr, dword, offset, "PCI READ"); |
| 124 | } |
| 125 | |
| 126 | static inline void read_host_csr(struct mei_csr *csr) |
| 127 | { |
| 128 | mei_read_dword_ptr(csr, MEI_H_CSR); |
| 129 | } |
| 130 | |
| 131 | static inline void write_host_csr(struct mei_csr *csr) |
| 132 | { |
| 133 | mei_write_dword_ptr(csr, MEI_H_CSR); |
| 134 | } |
| 135 | |
| 136 | static inline void read_me_csr(struct mei_csr *csr) |
| 137 | { |
| 138 | mei_read_dword_ptr(csr, MEI_ME_CSR_HA); |
| 139 | } |
| 140 | |
| 141 | static inline void write_cb(u32 dword) |
| 142 | { |
| 143 | write32(mei_base_address + MEI_H_CB_WW, dword); |
| 144 | mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE"); |
| 145 | } |
| 146 | |
| 147 | static inline u32 read_cb(void) |
| 148 | { |
| 149 | u32 dword = read32(mei_base_address + MEI_ME_CB_RW); |
| 150 | mei_dump(NULL, dword, MEI_ME_CB_RW, "READ"); |
| 151 | return dword; |
| 152 | } |
| 153 | |
| 154 | /* Wait for ME ready bit to be asserted */ |
| 155 | static int mei_wait_for_me_ready(void) |
| 156 | { |
| 157 | struct mei_csr me; |
| 158 | unsigned try = ME_RETRY; |
| 159 | |
| 160 | while (try--) { |
| 161 | read_me_csr(&me); |
| 162 | if (me.ready) |
| 163 | return 0; |
| 164 | udelay(ME_DELAY); |
| 165 | } |
| 166 | |
| 167 | printk(BIOS_ERR, "ME: failed to become ready\n"); |
| 168 | return -1; |
| 169 | } |
| 170 | |
| 171 | static void mei_reset(void) |
| 172 | { |
| 173 | struct mei_csr host; |
| 174 | |
| 175 | if (mei_wait_for_me_ready() < 0) |
| 176 | return; |
| 177 | |
| 178 | /* Reset host and ME circular buffers for next message */ |
| 179 | read_host_csr(&host); |
| 180 | host.reset = 1; |
| 181 | host.interrupt_generate = 1; |
| 182 | write_host_csr(&host); |
| 183 | |
| 184 | if (mei_wait_for_me_ready() < 0) |
| 185 | return; |
| 186 | |
| 187 | /* Re-init and indicate host is ready */ |
| 188 | read_host_csr(&host); |
| 189 | host.interrupt_generate = 1; |
| 190 | host.ready = 1; |
| 191 | host.reset = 0; |
| 192 | write_host_csr(&host); |
| 193 | } |
| 194 | |
| 195 | static int mei_send_packet(struct mei_header *mei, void *req_data) |
| 196 | { |
| 197 | struct mei_csr host; |
| 198 | unsigned ndata, n; |
| 199 | u32 *data; |
| 200 | |
| 201 | /* Number of dwords to write */ |
| 202 | ndata = mei->length >> 2; |
| 203 | |
| 204 | /* Pad non-dword aligned request message length */ |
| 205 | if (mei->length & 3) |
| 206 | ndata++; |
| 207 | if (!ndata) { |
| 208 | printk(BIOS_DEBUG, "ME: request has no data\n"); |
| 209 | return -1; |
| 210 | } |
| 211 | ndata++; /* Add MEI header */ |
| 212 | |
| 213 | /* |
| 214 | * Make sure there is still room left in the circular buffer. |
| 215 | * Reset the buffer pointers if the requested message will not fit. |
| 216 | */ |
| 217 | read_host_csr(&host); |
| 218 | if ((host.buffer_depth - host.buffer_write_ptr) < ndata) { |
| 219 | printk(BIOS_ERR, "ME: circular buffer full, resetting...\n"); |
| 220 | mei_reset(); |
| 221 | read_host_csr(&host); |
| 222 | } |
| 223 | |
| 224 | /* Ensure the requested length will fit in the circular buffer. */ |
| 225 | if ((host.buffer_depth - host.buffer_write_ptr) < ndata) { |
| 226 | printk(BIOS_ERR, "ME: message (%u) too large for buffer (%u)\n", |
| 227 | ndata + 2, host.buffer_depth); |
| 228 | return -1; |
| 229 | } |
| 230 | |
| 231 | /* Write MEI header */ |
| 232 | mei_write_dword_ptr(mei, MEI_H_CB_WW); |
| 233 | ndata--; |
| 234 | |
| 235 | /* Write message data */ |
| 236 | data = req_data; |
| 237 | for (n = 0; n < ndata; ++n) |
| 238 | write_cb(*data++); |
| 239 | |
| 240 | /* Generate interrupt to the ME */ |
| 241 | read_host_csr(&host); |
| 242 | host.interrupt_generate = 1; |
| 243 | write_host_csr(&host); |
| 244 | |
| 245 | /* Make sure ME is ready after sending request data */ |
| 246 | return mei_wait_for_me_ready(); |
| 247 | } |
| 248 | |
| 249 | static int mei_send_data(u8 me_address, u8 host_address, |
| 250 | void *req_data, int req_bytes) |
| 251 | { |
| 252 | struct mei_header header = { |
| 253 | .client_address = me_address, |
| 254 | .host_address = host_address, |
| 255 | }; |
| 256 | struct mei_csr host; |
| 257 | int current = 0; |
| 258 | u8 *req_ptr = req_data; |
| 259 | |
| 260 | while (!header.is_complete) { |
| 261 | int remain = req_bytes - current; |
| 262 | int buf_len; |
| 263 | |
| 264 | read_host_csr(&host); |
| 265 | buf_len = host.buffer_depth - host.buffer_write_ptr; |
| 266 | |
| 267 | if (buf_len > remain) { |
| 268 | /* Send all remaining data as final message */ |
| 269 | header.length = req_bytes - current; |
| 270 | header.is_complete = 1; |
| 271 | } else { |
| 272 | /* Send as much data as the buffer can hold */ |
| 273 | header.length = buf_len; |
| 274 | } |
| 275 | |
| 276 | mei_send_packet(&header, req_ptr); |
| 277 | |
| 278 | req_ptr += header.length; |
| 279 | current += header.length; |
| 280 | } |
| 281 | |
| 282 | return 0; |
| 283 | } |
| 284 | |
| 285 | static int mei_send_header(u8 me_address, u8 host_address, |
| 286 | void *header, int header_len, int complete) |
| 287 | { |
| 288 | struct mei_header mei = { |
| 289 | .client_address = me_address, |
| 290 | .host_address = host_address, |
| 291 | .length = header_len, |
| 292 | .is_complete = complete, |
| 293 | }; |
| 294 | return mei_send_packet(&mei, header); |
| 295 | } |
| 296 | |
| 297 | static int mei_recv_msg(void *header, int header_bytes, |
| 298 | void *rsp_data, int rsp_bytes) |
| 299 | { |
| 300 | struct mei_header mei_rsp; |
| 301 | struct mei_csr me, host; |
| 302 | unsigned ndata, n; |
| 303 | unsigned expected; |
| 304 | u32 *data; |
| 305 | |
| 306 | /* Total number of dwords to read from circular buffer */ |
| 307 | expected = (rsp_bytes + sizeof(mei_rsp) + header_bytes) >> 2; |
| 308 | if (rsp_bytes & 3) |
| 309 | expected++; |
| 310 | |
| 311 | if (mei_wait_for_me_ready() < 0) |
| 312 | return -1; |
| 313 | |
| 314 | /* |
| 315 | * The interrupt status bit does not appear to indicate that the |
| 316 | * message has actually been received. Instead we wait until the |
| 317 | * expected number of dwords are present in the circular buffer. |
| 318 | */ |
| 319 | for (n = ME_RETRY; n; --n) { |
| 320 | read_me_csr(&me); |
| 321 | if ((me.buffer_write_ptr - me.buffer_read_ptr) >= expected) |
| 322 | break; |
| 323 | udelay(ME_DELAY); |
| 324 | } |
| 325 | if (!n) { |
| 326 | printk(BIOS_ERR, "ME: timeout waiting for data: expected " |
| 327 | "%u, available %u\n", expected, |
| 328 | me.buffer_write_ptr - me.buffer_read_ptr); |
| 329 | return -1; |
| 330 | } |
| 331 | |
| 332 | /* Read and verify MEI response header from the ME */ |
| 333 | mei_read_dword_ptr(&mei_rsp, MEI_ME_CB_RW); |
| 334 | if (!mei_rsp.is_complete) { |
| 335 | printk(BIOS_ERR, "ME: response is not complete\n"); |
| 336 | return -1; |
| 337 | } |
| 338 | |
| 339 | /* Handle non-dword responses and expect at least the header */ |
| 340 | ndata = mei_rsp.length >> 2; |
| 341 | if (mei_rsp.length & 3) |
| 342 | ndata++; |
| 343 | if (ndata != (expected - 1)) { |
| 344 | printk(BIOS_ERR, "ME: response is missing data %d != %d\n", |
| 345 | ndata, (expected - 1)); |
| 346 | return -1; |
| 347 | } |
| 348 | |
| 349 | /* Read response header from the ME */ |
| 350 | data = header; |
| 351 | for (n = 0; n < (header_bytes >> 2); ++n) |
| 352 | *data++ = read_cb(); |
| 353 | ndata -= header_bytes >> 2; |
| 354 | |
| 355 | /* Make sure caller passed a buffer with enough space */ |
| 356 | if (ndata != (rsp_bytes >> 2)) { |
| 357 | printk(BIOS_ERR, "ME: not enough room in response buffer: " |
| 358 | "%u != %u\n", ndata, rsp_bytes >> 2); |
| 359 | return -1; |
| 360 | } |
| 361 | |
| 362 | /* Read response data from the circular buffer */ |
| 363 | data = rsp_data; |
| 364 | for (n = 0; n < ndata; ++n) |
| 365 | *data++ = read_cb(); |
| 366 | |
| 367 | /* Tell the ME that we have consumed the response */ |
| 368 | read_host_csr(&host); |
| 369 | host.interrupt_status = 1; |
| 370 | host.interrupt_generate = 1; |
| 371 | write_host_csr(&host); |
| 372 | |
| 373 | return mei_wait_for_me_ready(); |
| 374 | } |
| 375 | |
| 376 | static inline int mei_sendrecv_mkhi(struct mkhi_header *mkhi, |
| 377 | void *req_data, int req_bytes, |
| 378 | void *rsp_data, int rsp_bytes) |
| 379 | { |
| 380 | struct mkhi_header mkhi_rsp; |
| 381 | |
| 382 | /* Send header */ |
| 383 | if (mei_send_header(MEI_ADDRESS_MKHI, MEI_HOST_ADDRESS, |
| 384 | mkhi, sizeof(*mkhi), req_bytes ? 0 : 1) < 0) |
| 385 | return -1; |
| 386 | |
| 387 | /* Send data if available */ |
| 388 | if (req_bytes && mei_send_data(MEI_ADDRESS_MKHI, MEI_HOST_ADDRESS, |
| 389 | req_data, req_bytes) < 0) |
| 390 | return -1; |
| 391 | |
| 392 | /* Return now if no response expected */ |
| 393 | if (!rsp_bytes) |
| 394 | return 0; |
| 395 | |
| 396 | /* Read header and data */ |
| 397 | if (mei_recv_msg(&mkhi_rsp, sizeof(mkhi_rsp), |
| 398 | rsp_data, rsp_bytes) < 0) |
| 399 | return -1; |
| 400 | |
| 401 | if (!mkhi_rsp.is_response || |
| 402 | mkhi->group_id != mkhi_rsp.group_id || |
| 403 | mkhi->command != mkhi_rsp.command) { |
| 404 | printk(BIOS_ERR, "ME: invalid response, group %u ?= %u," |
| 405 | "command %u ?= %u, is_response %u\n", mkhi->group_id, |
| 406 | mkhi_rsp.group_id, mkhi->command, mkhi_rsp.command, |
| 407 | mkhi_rsp.is_response); |
| 408 | return -1; |
| 409 | } |
| 410 | |
| 411 | return 0; |
| 412 | } |
| 413 | |
| 414 | static inline int mei_sendrecv_icc(struct icc_header *icc, |
| 415 | void *req_data, int req_bytes, |
| 416 | void *rsp_data, int rsp_bytes) |
| 417 | { |
| 418 | struct icc_header icc_rsp; |
| 419 | |
| 420 | /* Send header */ |
| 421 | if (mei_send_header(MEI_ADDRESS_ICC, MEI_HOST_ADDRESS, |
| 422 | icc, sizeof(*icc), req_bytes ? 0 : 1) < 0) |
| 423 | return -1; |
| 424 | |
| 425 | /* Send data if available */ |
| 426 | if (req_bytes && mei_send_data(MEI_ADDRESS_ICC, MEI_HOST_ADDRESS, |
| 427 | req_data, req_bytes) < 0) |
| 428 | return -1; |
| 429 | |
| 430 | /* Read header and data, if needed */ |
| 431 | if (rsp_bytes && mei_recv_msg(&icc_rsp, sizeof(icc_rsp), |
| 432 | rsp_data, rsp_bytes) < 0) |
| 433 | return -1; |
| 434 | |
| 435 | return 0; |
| 436 | } |
| 437 | |
| 438 | /* |
| 439 | * mbp give up routine. This path is taken if hfs.mpb_rdy is 0 or the read |
| 440 | * state machine on the BIOS end doesn't match the ME's state machine. |
| 441 | */ |
| 442 | static void intel_me_mbp_give_up(device_t dev) |
| 443 | { |
| 444 | struct mei_csr csr; |
| 445 | |
| 446 | pci_write_config32(dev, PCI_ME_H_GS2, PCI_ME_MBP_GIVE_UP); |
| 447 | |
| 448 | read_host_csr(&csr); |
| 449 | csr.reset = 1; |
| 450 | csr.interrupt_generate = 1; |
| 451 | write_host_csr(&csr); |
| 452 | } |
| 453 | |
| 454 | /* |
| 455 | * mbp clear routine. This will wait for the ME to indicate that |
| 456 | * the MBP has been read and cleared. |
| 457 | */ |
| 458 | void intel_me_mbp_clear(device_t dev) |
| 459 | { |
| 460 | int count; |
| 461 | struct me_hfs2 hfs2; |
| 462 | |
| 463 | /* Wait for the mbp_cleared indicator */ |
| 464 | for (count = ME_RETRY; count > 0; --count) { |
| 465 | pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2); |
| 466 | if (hfs2.mbp_cleared) |
| 467 | break; |
| 468 | udelay(ME_DELAY); |
| 469 | } |
| 470 | |
| 471 | if (count == 0) { |
| 472 | printk(BIOS_WARNING, "ME: Timeout waiting for mbp_cleared\n"); |
| 473 | intel_me_mbp_give_up(dev); |
| 474 | } else { |
| 475 | printk(BIOS_INFO, "ME: MBP cleared\n"); |
| 476 | } |
| 477 | } |
| 478 | |
| 479 | #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 480 | static void me_print_fw_version(mbp_fw_version_name *vers_name) |
| 481 | { |
| 482 | if (!vers_name) { |
| 483 | printk(BIOS_ERR, "ME: mbp missing version report\n"); |
| 484 | return; |
| 485 | } |
| 486 | |
| 487 | printk(BIOS_DEBUG, "ME: found version %d.%d.%d.%d\n", |
| 488 | vers_name->major_version, vers_name->minor_version, |
| 489 | vers_name->hotfix_version, vers_name->build_version); |
| 490 | } |
| 491 | |
| 492 | #if CONFIG_DEBUG_INTEL_ME |
Edward O'Callaghan | 8cc5dc1 | 2015-01-07 15:50:43 +1100 | [diff] [blame] | 493 | static inline void print_cap(const char *name, int state) |
| 494 | { |
| 495 | printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", |
| 496 | name, state ? " en" : "dis"); |
| 497 | } |
| 498 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 499 | /* Get ME Firmware Capabilities */ |
| 500 | static int mkhi_get_fwcaps(mbp_mefwcaps *cap) |
| 501 | { |
| 502 | u32 rule_id = 0; |
| 503 | struct me_fwcaps cap_msg; |
| 504 | struct mkhi_header mkhi = { |
| 505 | .group_id = MKHI_GROUP_ID_FWCAPS, |
| 506 | .command = MKHI_FWCAPS_GET_RULE, |
| 507 | }; |
| 508 | |
| 509 | /* Send request and wait for response */ |
| 510 | if (mei_sendrecv_mkhi(&mkhi, &rule_id, sizeof(u32), |
| 511 | &cap_msg, sizeof(cap_msg)) < 0) { |
| 512 | printk(BIOS_ERR, "ME: GET FWCAPS message failed\n"); |
| 513 | return -1; |
| 514 | } |
| 515 | *cap = cap_msg.caps_sku; |
| 516 | return 0; |
| 517 | } |
| 518 | |
| 519 | /* Get ME Firmware Capabilities */ |
| 520 | static void me_print_fwcaps(mbp_mefwcaps *cap) |
| 521 | { |
| 522 | mbp_mefwcaps local_caps; |
| 523 | if (!cap) { |
| 524 | cap = &local_caps; |
| 525 | printk(BIOS_ERR, "ME: mbp missing fwcaps report\n"); |
| 526 | if (mkhi_get_fwcaps(cap)) |
| 527 | return; |
| 528 | } |
| 529 | |
| 530 | print_cap("Full Network manageability", cap->full_net); |
| 531 | print_cap("Regular Network manageability", cap->std_net); |
| 532 | print_cap("Manageability", cap->manageability); |
| 533 | print_cap("IntelR Anti-Theft (AT)", cap->intel_at); |
| 534 | print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls); |
| 535 | print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc); |
| 536 | print_cap("ICC Over Clocking", cap->icc_over_clocking); |
Edward O'Callaghan | 8cc5dc1 | 2015-01-07 15:50:43 +1100 | [diff] [blame] | 537 | print_cap("Protected Audio Video Path (PAVP)", cap->pavp); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 538 | print_cap("IPV6", cap->ipv6); |
| 539 | print_cap("KVM Remote Control (KVM)", cap->kvm); |
| 540 | print_cap("Outbreak Containment Heuristic (OCH)", cap->och); |
| 541 | print_cap("Virtual LAN (VLAN)", cap->vlan); |
| 542 | print_cap("TLS", cap->tls); |
| 543 | print_cap("Wireless LAN (WLAN)", cap->wlan); |
| 544 | } |
| 545 | #endif |
| 546 | #endif |
| 547 | |
| 548 | /* Send END OF POST message to the ME */ |
| 549 | static int mkhi_end_of_post(void) |
| 550 | { |
| 551 | struct mkhi_header mkhi = { |
| 552 | .group_id = MKHI_GROUP_ID_GEN, |
| 553 | .command = MKHI_END_OF_POST, |
| 554 | }; |
| 555 | u32 eop_ack; |
| 556 | |
| 557 | /* Send request and wait for response */ |
| 558 | printk(BIOS_NOTICE, "ME: %s\n", __FUNCTION__); |
| 559 | if (mei_sendrecv_mkhi(&mkhi, NULL, 0, &eop_ack, sizeof(eop_ack)) < 0) { |
| 560 | printk(BIOS_ERR, "ME: END OF POST message failed\n"); |
| 561 | return -1; |
| 562 | } |
| 563 | |
| 564 | printk(BIOS_INFO, "ME: END OF POST message successful (%d)\n", eop_ack); |
| 565 | return 0; |
| 566 | } |
| 567 | |
| 568 | void intel_me_finalize(void) |
| 569 | { |
| 570 | device_t dev = PCH_DEV_ME; |
| 571 | struct me_hfs hfs; |
| 572 | u32 reg32; |
| 573 | |
| 574 | /* S3 path will have hidden this device already */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 575 | if (!mei_base_address || mei_base_address == (u8 *)0xfffffff0) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 576 | return; |
| 577 | |
| 578 | #if CONFIG_ME_MBP_CLEAR_LATE |
| 579 | /* Wait for ME MBP Cleared indicator */ |
| 580 | intel_me_mbp_clear(dev); |
| 581 | #endif |
| 582 | |
| 583 | /* Make sure ME is in a mode that expects EOP */ |
| 584 | reg32 = pci_read_config32(dev, PCI_ME_HFS); |
| 585 | memcpy(&hfs, ®32, sizeof(u32)); |
| 586 | |
| 587 | /* Abort and leave device alone if not normal mode */ |
| 588 | if (hfs.fpt_bad || |
| 589 | hfs.working_state != ME_HFS_CWS_NORMAL || |
| 590 | hfs.operation_mode != ME_HFS_MODE_NORMAL) |
| 591 | return; |
| 592 | |
| 593 | /* Try to send EOP command so ME stops accepting other commands */ |
| 594 | mkhi_end_of_post(); |
| 595 | |
| 596 | /* Make sure IO is disabled */ |
| 597 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 598 | reg32 &= ~(PCI_COMMAND_MASTER | |
| 599 | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
| 600 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 601 | |
| 602 | /* Hide the PCI device */ |
| 603 | RCBA32_OR(FD2, PCH_DISABLE_MEI1); |
| 604 | } |
| 605 | |
| 606 | static int me_icc_set_clock_enables(u32 mask) |
| 607 | { |
| 608 | struct icc_clock_enables_msg clk = { |
| 609 | .clock_enables = 0, /* Turn off specified clocks */ |
| 610 | .clock_mask = mask, |
| 611 | .no_response = 1, /* Do not expect response */ |
| 612 | }; |
| 613 | struct icc_header icc = { |
| 614 | .api_version = ICC_API_VERSION_LYNXPOINT, |
| 615 | .icc_command = ICC_SET_CLOCK_ENABLES, |
| 616 | .length = sizeof(clk), |
| 617 | }; |
| 618 | |
| 619 | /* Send request and wait for response */ |
| 620 | if (mei_sendrecv_icc(&icc, &clk, sizeof(clk), NULL, 0) < 0) { |
| 621 | printk(BIOS_ERR, "ME: ICC SET CLOCK ENABLES message failed\n"); |
| 622 | return -1; |
| 623 | } else { |
| 624 | printk(BIOS_INFO, "ME: ICC SET CLOCK ENABLES 0x%08x\n", mask); |
| 625 | } |
| 626 | |
| 627 | return 0; |
| 628 | } |
| 629 | |
| 630 | /* Determine the path that we should take based on ME status */ |
| 631 | static me_bios_path intel_me_path(device_t dev) |
| 632 | { |
| 633 | me_bios_path path = ME_DISABLE_BIOS_PATH; |
| 634 | struct me_hfs hfs; |
| 635 | struct me_hfs2 hfs2; |
| 636 | |
| 637 | /* Check and dump status */ |
| 638 | intel_me_status(); |
| 639 | |
| 640 | pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS); |
| 641 | pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2); |
| 642 | |
| 643 | /* Check Current Working State */ |
| 644 | switch (hfs.working_state) { |
| 645 | case ME_HFS_CWS_NORMAL: |
| 646 | path = ME_NORMAL_BIOS_PATH; |
| 647 | break; |
| 648 | case ME_HFS_CWS_REC: |
| 649 | path = ME_RECOVERY_BIOS_PATH; |
| 650 | break; |
| 651 | default: |
| 652 | path = ME_DISABLE_BIOS_PATH; |
| 653 | break; |
| 654 | } |
| 655 | |
| 656 | /* Check Current Operation Mode */ |
| 657 | switch (hfs.operation_mode) { |
| 658 | case ME_HFS_MODE_NORMAL: |
| 659 | break; |
| 660 | case ME_HFS_MODE_DEBUG: |
| 661 | case ME_HFS_MODE_DIS: |
| 662 | case ME_HFS_MODE_OVER_JMPR: |
| 663 | case ME_HFS_MODE_OVER_MEI: |
| 664 | default: |
| 665 | path = ME_DISABLE_BIOS_PATH; |
| 666 | break; |
| 667 | } |
| 668 | |
| 669 | /* Check for any error code and valid firmware and MBP */ |
| 670 | if (hfs.error_code || hfs.fpt_bad) |
| 671 | path = ME_ERROR_BIOS_PATH; |
| 672 | |
| 673 | /* Check if the MBP is ready */ |
| 674 | if (!hfs2.mbp_rdy) { |
| 675 | printk(BIOS_CRIT, "%s: mbp is not ready!\n", |
| 676 | __FUNCTION__); |
| 677 | path = ME_ERROR_BIOS_PATH; |
| 678 | } |
| 679 | |
| 680 | #if CONFIG_ELOG |
| 681 | if (path != ME_NORMAL_BIOS_PATH) { |
| 682 | struct elog_event_data_me_extended data = { |
| 683 | .current_working_state = hfs.working_state, |
| 684 | .operation_state = hfs.operation_state, |
| 685 | .operation_mode = hfs.operation_mode, |
| 686 | .error_code = hfs.error_code, |
| 687 | .progress_code = hfs2.progress_code, |
| 688 | .current_pmevent = hfs2.current_pmevent, |
| 689 | .current_state = hfs2.current_state, |
| 690 | }; |
| 691 | elog_add_event_byte(ELOG_TYPE_MANAGEMENT_ENGINE, path); |
| 692 | elog_add_event_raw(ELOG_TYPE_MANAGEMENT_ENGINE_EXT, |
| 693 | &data, sizeof(data)); |
| 694 | } |
| 695 | #endif |
| 696 | |
| 697 | return path; |
| 698 | } |
| 699 | |
| 700 | /* Prepare ME for MEI messages */ |
| 701 | static int intel_mei_setup(device_t dev) |
| 702 | { |
| 703 | struct resource *res; |
| 704 | struct mei_csr host; |
| 705 | u32 reg32; |
| 706 | |
| 707 | /* Find the MMIO base for the ME interface */ |
| 708 | res = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 709 | if (!res || res->base == 0 || res->size == 0) { |
| 710 | printk(BIOS_DEBUG, "ME: MEI resource not present!\n"); |
| 711 | return -1; |
| 712 | } |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 713 | mei_base_address = res2mmio(res, 0, 0); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 714 | |
| 715 | /* Ensure Memory and Bus Master bits are set */ |
| 716 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 717 | reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; |
| 718 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 719 | |
| 720 | /* Clean up status for next message */ |
| 721 | read_host_csr(&host); |
| 722 | host.interrupt_generate = 1; |
| 723 | host.ready = 1; |
| 724 | host.reset = 0; |
| 725 | write_host_csr(&host); |
| 726 | |
| 727 | return 0; |
| 728 | } |
| 729 | |
| 730 | /* Read the Extend register hash of ME firmware */ |
| 731 | static int intel_me_extend_valid(device_t dev) |
| 732 | { |
| 733 | struct me_heres status; |
| 734 | u32 extend[8] = {0}; |
| 735 | int i, count = 0; |
| 736 | |
| 737 | pci_read_dword_ptr(dev, &status, PCI_ME_HERES); |
| 738 | if (!status.extend_feature_present) { |
| 739 | printk(BIOS_ERR, "ME: Extend Feature not present\n"); |
| 740 | return -1; |
| 741 | } |
| 742 | |
| 743 | if (!status.extend_reg_valid) { |
| 744 | printk(BIOS_ERR, "ME: Extend Register not valid\n"); |
| 745 | return -1; |
| 746 | } |
| 747 | |
| 748 | switch (status.extend_reg_algorithm) { |
| 749 | case PCI_ME_EXT_SHA1: |
| 750 | count = 5; |
| 751 | printk(BIOS_DEBUG, "ME: Extend SHA-1: "); |
| 752 | break; |
| 753 | case PCI_ME_EXT_SHA256: |
| 754 | count = 8; |
| 755 | printk(BIOS_DEBUG, "ME: Extend SHA-256: "); |
| 756 | break; |
| 757 | default: |
| 758 | printk(BIOS_ERR, "ME: Extend Algorithm %d unknown\n", |
| 759 | status.extend_reg_algorithm); |
| 760 | return -1; |
| 761 | } |
| 762 | |
| 763 | for (i = 0; i < count; ++i) { |
| 764 | extend[i] = pci_read_config32(dev, PCI_ME_HER(i)); |
| 765 | printk(BIOS_DEBUG, "%08x", extend[i]); |
| 766 | } |
| 767 | printk(BIOS_DEBUG, "\n"); |
| 768 | |
| 769 | #if CONFIG_CHROMEOS |
| 770 | /* Save hash in NVS for the OS to verify */ |
| 771 | chromeos_set_me_hash(extend, count); |
| 772 | #endif |
| 773 | |
| 774 | return 0; |
| 775 | } |
| 776 | |
| 777 | /* Check whether ME is present and do basic init */ |
| 778 | static void intel_me_init(device_t dev) |
| 779 | { |
| 780 | config_t *config = dev->chip_info; |
| 781 | me_bios_path path = intel_me_path(dev); |
| 782 | me_bios_payload mbp_data; |
| 783 | |
| 784 | /* Do initial setup and determine the BIOS path */ |
| 785 | printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_bios_path_values[path]); |
| 786 | |
| 787 | if (path == ME_NORMAL_BIOS_PATH) { |
| 788 | /* Validate the extend register */ |
| 789 | intel_me_extend_valid(dev); |
| 790 | } |
| 791 | |
| 792 | memset(&mbp_data, 0, sizeof(mbp_data)); |
| 793 | |
| 794 | /* |
| 795 | * According to the ME9 BWG, BIOS is required to fetch MBP data in |
| 796 | * all boot flows except S3 Resume. |
| 797 | */ |
| 798 | |
| 799 | /* Prepare MEI MMIO interface */ |
| 800 | if (intel_mei_setup(dev) < 0) |
| 801 | return; |
| 802 | |
| 803 | if (intel_me_read_mbp(&mbp_data, dev)) |
| 804 | return; |
| 805 | |
| 806 | #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) |
| 807 | me_print_fw_version(mbp_data.fw_version_name); |
| 808 | #if CONFIG_DEBUG_INTEL_ME |
| 809 | me_print_fwcaps(mbp_data.fw_capabilities); |
| 810 | #endif |
| 811 | |
| 812 | if (mbp_data.plat_time) { |
| 813 | printk(BIOS_DEBUG, "ME: Wake Event to ME Reset: %u ms\n", |
| 814 | mbp_data.plat_time->wake_event_mrst_time_ms); |
| 815 | printk(BIOS_DEBUG, "ME: ME Reset to Platform Reset: %u ms\n", |
| 816 | mbp_data.plat_time->mrst_pltrst_time_ms); |
| 817 | printk(BIOS_DEBUG, "ME: Platform Reset to CPU Reset: %u ms\n", |
| 818 | mbp_data.plat_time->pltrst_cpurst_time_ms); |
| 819 | } |
| 820 | #endif |
| 821 | |
| 822 | /* Set clock enables according to devicetree */ |
| 823 | if (config && config->icc_clock_disable) |
| 824 | me_icc_set_clock_enables(config->icc_clock_disable); |
| 825 | |
| 826 | /* |
| 827 | * Leave the ME unlocked. It will be locked via SMI command later. |
| 828 | */ |
| 829 | } |
| 830 | |
| 831 | static void intel_me_enable(device_t dev) |
| 832 | { |
| 833 | #if CONFIG_HAVE_ACPI_RESUME |
| 834 | /* Avoid talking to the device in S3 path */ |
| 835 | if (acpi_slp_type == 3) { |
| 836 | dev->enabled = 0; |
| 837 | pch_disable_devfn(dev); |
| 838 | } |
| 839 | #endif |
| 840 | } |
| 841 | |
| 842 | static struct device_operations device_ops = { |
| 843 | .read_resources = &pci_dev_read_resources, |
| 844 | .set_resources = &pci_dev_set_resources, |
| 845 | .enable_resources = &pci_dev_enable_resources, |
| 846 | .enable = &intel_me_enable, |
| 847 | .init = &intel_me_init, |
| 848 | .ops_pci = &broadwell_pci_ops, |
| 849 | }; |
| 850 | |
| 851 | static const unsigned short pci_device_ids[] = { |
| 852 | 0x9c3a, /* Low Power */ |
| 853 | 0x9cba, /* WildcatPoint */ |
| 854 | 0 |
| 855 | }; |
| 856 | |
| 857 | static const struct pci_driver intel_me __pci_driver = { |
| 858 | .ops = &device_ops, |
| 859 | .vendor = PCI_VENDOR_ID_INTEL, |
| 860 | .devices= pci_device_ids, |
| 861 | }; |
| 862 | |
| 863 | /****************************************************************************** |
| 864 | * */ |
| 865 | static u32 me_to_host_words_pending(void) |
| 866 | { |
| 867 | struct mei_csr me; |
| 868 | read_me_csr(&me); |
| 869 | if (!me.ready) |
| 870 | return 0; |
| 871 | return (me.buffer_write_ptr - me.buffer_read_ptr) & |
| 872 | (me.buffer_depth - 1); |
| 873 | } |
| 874 | |
| 875 | struct mbp_payload { |
| 876 | mbp_header header; |
| 877 | u32 data[0]; |
| 878 | }; |
| 879 | |
| 880 | /* |
| 881 | * mbp seems to be following its own flow, let's retrieve it in a dedicated |
| 882 | * function. |
| 883 | */ |
| 884 | static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev) |
| 885 | { |
| 886 | mbp_header mbp_hdr; |
| 887 | u32 me2host_pending; |
| 888 | struct mei_csr host; |
| 889 | struct me_hfs2 hfs2; |
| 890 | struct mbp_payload *mbp; |
| 891 | int i; |
| 892 | |
| 893 | pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2); |
| 894 | |
| 895 | if (!hfs2.mbp_rdy) { |
| 896 | printk(BIOS_ERR, "ME: MBP not ready\n"); |
| 897 | goto mbp_failure; |
| 898 | } |
| 899 | |
| 900 | me2host_pending = me_to_host_words_pending(); |
| 901 | if (!me2host_pending) { |
| 902 | printk(BIOS_ERR, "ME: no mbp data!\n"); |
| 903 | goto mbp_failure; |
| 904 | } |
| 905 | |
| 906 | /* we know for sure that at least the header is there */ |
| 907 | mei_read_dword_ptr(&mbp_hdr, MEI_ME_CB_RW); |
| 908 | |
| 909 | if ((mbp_hdr.num_entries > (mbp_hdr.mbp_size / 2)) || |
| 910 | (me2host_pending < mbp_hdr.mbp_size)) { |
| 911 | printk(BIOS_ERR, "ME: mbp of %d entries, total size %d words" |
| 912 | " buffer contains %d words\n", |
| 913 | mbp_hdr.num_entries, mbp_hdr.mbp_size, |
| 914 | me2host_pending); |
| 915 | goto mbp_failure; |
| 916 | } |
| 917 | mbp = malloc(mbp_hdr.mbp_size * sizeof(u32)); |
| 918 | if (!mbp) |
| 919 | goto mbp_failure; |
| 920 | |
| 921 | mbp->header = mbp_hdr; |
| 922 | me2host_pending--; |
| 923 | |
| 924 | i = 0; |
| 925 | while (i != me2host_pending) { |
| 926 | mei_read_dword_ptr(&mbp->data[i], MEI_ME_CB_RW); |
| 927 | i++; |
| 928 | } |
| 929 | |
| 930 | /* Signal to the ME that the host has finished reading the MBP. */ |
| 931 | read_host_csr(&host); |
| 932 | host.interrupt_generate = 1; |
| 933 | write_host_csr(&host); |
| 934 | |
| 935 | #if !CONFIG_ME_MBP_CLEAR_LATE |
| 936 | /* Wait for the mbp_cleared indicator. */ |
| 937 | intel_me_mbp_clear(dev); |
| 938 | #endif |
| 939 | |
| 940 | /* Dump out the MBP contents. */ |
| 941 | #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) |
| 942 | printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n", |
| 943 | mbp->header.num_entries, mbp->header.mbp_size); |
| 944 | #if CONFIG_DEBUG_INTEL_ME |
| 945 | for (i = 0; i < mbp->header.mbp_size - 1; i++) { |
| 946 | printk(BIOS_INFO, "ME MBP: %04x: 0x%08x\n", i, mbp->data[i]); |
| 947 | } |
| 948 | #endif |
| 949 | #endif |
| 950 | |
| 951 | #define ASSIGN_FIELD_PTR(field_,val_) \ |
| 952 | { \ |
| 953 | mbp_data->field_ = (typeof(mbp_data->field_))(void *)val_; \ |
| 954 | break; \ |
| 955 | } |
| 956 | |
| 957 | /* Setup the pointers in the me_bios_payload structure. */ |
| 958 | for (i = 0; i < mbp->header.mbp_size - 1;) { |
| 959 | mbp_item_header *item = (void *)&mbp->data[i]; |
| 960 | |
| 961 | switch(MBP_MAKE_IDENT(item->app_id, item->item_id)) { |
| 962 | case MBP_IDENT(KERNEL, FW_VER): |
| 963 | ASSIGN_FIELD_PTR(fw_version_name, &mbp->data[i+1]); |
| 964 | |
| 965 | case MBP_IDENT(ICC, PROFILE): |
| 966 | ASSIGN_FIELD_PTR(icc_profile, &mbp->data[i+1]); |
| 967 | |
| 968 | case MBP_IDENT(INTEL_AT, STATE): |
| 969 | ASSIGN_FIELD_PTR(at_state, &mbp->data[i+1]); |
| 970 | |
| 971 | case MBP_IDENT(KERNEL, FW_CAP): |
| 972 | ASSIGN_FIELD_PTR(fw_capabilities, &mbp->data[i+1]); |
| 973 | |
| 974 | case MBP_IDENT(KERNEL, ROM_BIST): |
| 975 | ASSIGN_FIELD_PTR(rom_bist_data, &mbp->data[i+1]); |
| 976 | |
| 977 | case MBP_IDENT(KERNEL, PLAT_KEY): |
| 978 | ASSIGN_FIELD_PTR(platform_key, &mbp->data[i+1]); |
| 979 | |
| 980 | case MBP_IDENT(KERNEL, FW_TYPE): |
| 981 | ASSIGN_FIELD_PTR(fw_plat_type, &mbp->data[i+1]); |
| 982 | |
| 983 | case MBP_IDENT(KERNEL, MFS_FAILURE): |
| 984 | ASSIGN_FIELD_PTR(mfsintegrity, &mbp->data[i+1]); |
| 985 | |
| 986 | case MBP_IDENT(KERNEL, PLAT_TIME): |
| 987 | ASSIGN_FIELD_PTR(plat_time, &mbp->data[i+1]); |
| 988 | |
| 989 | case MBP_IDENT(NFC, SUPPORT_DATA): |
| 990 | ASSIGN_FIELD_PTR(nfc_data, &mbp->data[i+1]); |
| 991 | |
| 992 | default: |
| 993 | printk(BIOS_ERR, "ME MBP: unknown item 0x%x @ " |
| 994 | "dw offset 0x%x\n", mbp->data[i], i); |
| 995 | break; |
| 996 | } |
| 997 | i += item->length; |
| 998 | } |
| 999 | #undef ASSIGN_FIELD_PTR |
| 1000 | |
Patrick Georgi | f3a235e | 2015-02-22 16:51:23 +0100 | [diff] [blame^] | 1001 | free(mbp); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 1002 | return 0; |
| 1003 | |
| 1004 | mbp_failure: |
| 1005 | intel_me_mbp_give_up(dev); |
| 1006 | return -1; |
| 1007 | } |