| Matt DeVillier | bb9d106 | 2022-08-22 17:27:11 -0500 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <device/device.h> |
| 5 | #include <device/dram/ddr5.h> |
| 6 | #include <memory_info.h> |
| 7 | #include <smbios.h> |
| 8 | #include <types.h> |
| 9 | |
| 10 | enum ddr5_speed_grade { |
| 11 | DDR5_1333, |
| 12 | DDR5_1600, |
| 13 | DDR5_1866, |
| 14 | DDR5_2133, |
| 15 | DDR5_2400, |
| 16 | DDR5_2667, |
| 17 | DDR5_2933, |
| 18 | DDR5_3200, |
| 19 | DDR5_3733, |
| 20 | DDR5_4267, |
| 21 | DDR5_4800, |
| 22 | DDR5_5500, |
| 23 | DDR5_6000, |
| 24 | DDR5_6400, |
| 25 | }; |
| 26 | |
| 27 | struct ddr5_speed_attr { |
| 28 | uint32_t min_clock_mhz; // inclusive |
| 29 | uint32_t max_clock_mhz; // inclusive |
| 30 | uint32_t reported_mts; |
| 31 | }; |
| 32 | |
| 33 | /** |
| 34 | * (LP)DDR5 speed attributes derived from JEDEC JESD79-5B, JESD209-5B and industry norms |
| 35 | * |
| 36 | * min_clock_mhz = previous max speed + 1 |
| 37 | * max_clock_mhz = 50% of speed grade, +/- 1 |
| 38 | * reported_mts = Standard reported DDR5 speed in MT/s |
| 39 | * May be slightly less than the actual max MT/s |
| 40 | */ |
| 41 | static const struct ddr5_speed_attr ddr5_speeds[] = { |
| 42 | [DDR5_1333] = { |
| 43 | .min_clock_mhz = 10, |
| 44 | .max_clock_mhz = 667, |
| 45 | .reported_mts = 1333, |
| 46 | }, |
| 47 | [DDR5_1600] = { |
| 48 | .min_clock_mhz = 668, |
| 49 | .max_clock_mhz = 800, |
| 50 | .reported_mts = 1600, |
| 51 | }, |
| 52 | [DDR5_1866] = { |
| 53 | .min_clock_mhz = 801, |
| 54 | .max_clock_mhz = 933, |
| 55 | .reported_mts = 1866, |
| 56 | }, |
| 57 | [DDR5_2133] = { |
| 58 | .min_clock_mhz = 934, |
| 59 | .max_clock_mhz = 1067, |
| 60 | .reported_mts = 2133, |
| 61 | }, |
| 62 | [DDR5_2400] = { |
| 63 | .min_clock_mhz = 1068, |
| 64 | .max_clock_mhz = 1200, |
| 65 | .reported_mts = 2400, |
| 66 | }, |
| 67 | [DDR5_2667] = { |
| 68 | .min_clock_mhz = 1201, |
| 69 | .max_clock_mhz = 1333, |
| 70 | .reported_mts = 2667, |
| 71 | }, |
| 72 | [DDR5_2933] = { |
| 73 | .min_clock_mhz = 1334, |
| 74 | .max_clock_mhz = 1467, |
| 75 | .reported_mts = 2933, |
| 76 | }, |
| 77 | [DDR5_3200] = { |
| 78 | .min_clock_mhz = 1468, |
| 79 | .max_clock_mhz = 1600, |
| 80 | .reported_mts = 3200, |
| 81 | }, |
| 82 | [DDR5_3733] = { |
| 83 | .min_clock_mhz = 1601, |
| 84 | .max_clock_mhz = 1866, |
| 85 | .reported_mts = 3733 |
| 86 | }, |
| 87 | [DDR5_4267] = { |
| 88 | .min_clock_mhz = 1867, |
| 89 | .max_clock_mhz = 2133, |
| 90 | .reported_mts = 4267 |
| 91 | }, |
| 92 | [DDR5_4800] = { |
| 93 | .min_clock_mhz = 2134, |
| 94 | .max_clock_mhz = 2400, |
| 95 | .reported_mts = 4800 |
| 96 | }, |
| 97 | [DDR5_5500] = { |
| 98 | .min_clock_mhz = 2401, |
| 99 | .max_clock_mhz = 2750, |
| 100 | .reported_mts = 5500 |
| 101 | }, |
| 102 | [DDR5_6000] = { |
| 103 | .min_clock_mhz = 2751, |
| 104 | .max_clock_mhz = 3000, |
| 105 | .reported_mts = 6000 |
| 106 | }, |
| 107 | [DDR5_6400] = { |
| 108 | .min_clock_mhz = 3001, |
| 109 | .max_clock_mhz = 3200, |
| 110 | .reported_mts = 6400 |
| 111 | }, |
| 112 | }; |
| 113 | |
| 114 | /** |
| 115 | * Converts DDR5 clock speed in MHz to the standard reported speed in MT/s |
| 116 | */ |
| 117 | uint16_t ddr5_speed_mhz_to_reported_mts(uint16_t speed_mhz) |
| 118 | { |
| 119 | for (enum ddr5_speed_grade speed = 0; speed < ARRAY_SIZE(ddr5_speeds); speed++) { |
| 120 | const struct ddr5_speed_attr *speed_attr = &ddr5_speeds[speed]; |
| 121 | if (speed_mhz >= speed_attr->min_clock_mhz && |
| 122 | speed_mhz <= speed_attr->max_clock_mhz) { |
| 123 | return speed_attr->reported_mts; |
| 124 | } |
| 125 | } |
| 126 | printk(BIOS_ERR, "DDR5 speed of %d MHz is out of range\n", speed_mhz); |
| 127 | return 0; |
| 128 | } |