blob: 5735fa244615a2404b5264d3644773640e9d3a35 [file] [log] [blame]
zbaoea71e812012-08-02 18:36:36 +08001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20#include <reset.h>
21#include <arch/io.h> /*inb, outb*/
22#include <arch/romcc_io.h> /*pci_read_config32, device_t, PCI_DEV*/
23
24#define HT_INIT_CONTROL 0x6C
25#define HTIC_BIOSR_Detect (1<<5)
26
27#if CONFIG_MAX_PHYSICAL_CPUS > 32
28#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
29#else
30#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
31#endif
32
33static inline void set_bios_reset(void)
34{
35 u32 nodes;
36 u32 htic;
37 device_t dev;
38 int i;
39
40 nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
41 for(i = 0; i < nodes; i++) {
42 dev = NODE_PCI(i, 0);
43 htic = pci_read_config32(dev, HT_INIT_CONTROL);
44 htic &= ~HTIC_BIOSR_Detect;
45 pci_write_config32(dev, HT_INIT_CONTROL, htic);
46 }
47}
48
49void hard_reset(void)
50{
51 set_bios_reset();
52 /* Try rebooting through port 0xcf9 */
53 /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
54 outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
55 outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
56}
57
58//SbReset();
59void soft_reset(void)
60{
61 set_bios_reset();
62 /* link reset */
63 outb(0x06, 0x0cf9);
64}