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Felix Held153f92a2020-12-08 17:27:30 +01001/* SPDX-License-Identifier: GPL-2.0-only */
2
3#include <amdblocks/acpimmio.h>
Zheng Bao91947602021-01-27 15:47:58 +08004#include <amdblocks/espi.h>
Zheng Bao3da55692021-01-26 18:30:18 +08005#include <amdblocks/lpc.h>
Felix Held153f92a2020-12-08 17:27:30 +01006#include <amdblocks/smbus.h>
Zheng Baob0f00ed2021-03-16 15:28:49 +08007#include <amdblocks/i2c.h>
Felix Held153f92a2020-12-08 17:27:30 +01008#include <console/console.h>
Zheng Baob0f00ed2021-03-16 15:28:49 +08009#include <soc/i2c.h>
Felix Held153f92a2020-12-08 17:27:30 +010010#include <soc/southbridge.h>
Felix Held8a3d4d52021-01-13 03:06:21 +010011#include <soc/uart.h>
Felix Held153f92a2020-12-08 17:27:30 +010012
Zheng Baob0f00ed2021-03-16 15:28:49 +080013#include "chip.h"
14
15/* This table is for the initial conversion of all SCL pins to input with no pull. */
16static const struct soc_i2c_scl_pin i2c_scl_pins[] = {
17 { PAD_GPI(I2C0_SCL_PIN, PULL_NONE), GPIO_I2C0_SCL },
18 { PAD_GPI(I2C1_SCL_PIN, PULL_NONE), GPIO_I2C1_SCL },
19 { PAD_GPI(I2C2_SCL_PIN, PULL_NONE), GPIO_I2C2_SCL },
20 { PAD_GPI(I2C3_SCL_PIN, PULL_NONE), GPIO_I2C3_SCL },
21};
22
23static void reset_i2c_peripherals(void)
24{
25 const struct soc_amd_cezanne_config *cfg = config_of_soc();
26 struct soc_i2c_peripheral_reset_info reset_info;
27
28 reset_info.i2c_scl_reset_mask = cfg->i2c_scl_reset & GPIO_I2C_MASK;
29 reset_info.i2c_scl = i2c_scl_pins;
30 reset_info.num_pins = ARRAY_SIZE(i2c_scl_pins);
31 sb_reset_i2c_peripherals(&reset_info);
32}
33
Felix Held153f92a2020-12-08 17:27:30 +010034/* Before console init */
35void fch_pre_init(void)
36{
Zheng Bao3da55692021-01-26 18:30:18 +080037 lpc_early_init();
38
Felix Held153f92a2020-12-08 17:27:30 +010039 enable_acpimmio_decode_pm04();
40 fch_smbus_init();
41 fch_enable_cf9_io();
42 fch_enable_legacy_io();
Raul E Rangelb825acb2021-02-24 16:21:00 -070043 fch_disable_legacy_dma_io();
Felix Held62ef88f2020-12-08 23:18:19 +010044 enable_aoac_devices();
Zheng Baob0f00ed2021-03-16 15:28:49 +080045 reset_i2c_peripherals();
Felix Held8a3d4d52021-01-13 03:06:21 +010046
47 /*
48 * On reset Range_0 defaults to enabled. We want to start with a clean
49 * slate to not have things unexpectedly enabled.
50 */
51 clear_uart_legacy_config();
52
53 if (CONFIG(AMD_SOC_CONSOLE_UART))
54 set_uart_config(CONFIG_UART_FOR_CONSOLE);
Felix Held27b295b2021-03-25 01:20:41 +010055
56 /* disable the keyboard reset function before mainboard GPIO setup */
57 if (CONFIG(DISABLE_KEYBOARD_RESET_PIN))
58 fch_disable_kb_rst();
Felix Held153f92a2020-12-08 17:27:30 +010059}
60
61/* After console init */
62void fch_early_init(void)
63{
64 fch_print_pmxc0_status();
Zheng Bao7b13e4e2021-03-16 16:13:56 +080065 i2c_soc_early_init();
Zheng Bao91947602021-01-27 15:47:58 +080066
Raul E Rangel95b3dc32021-03-24 16:53:37 -060067 if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING))
68 lpc_disable_spi_rom_sharing();
69
Zheng Bao91947602021-01-27 15:47:58 +080070 if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) {
Martin Rothf3314c22021-03-23 13:34:49 -060071 espi_clear_decodes();
Zheng Bao91947602021-01-27 15:47:58 +080072 espi_setup();
73 espi_configure_decodes();
74 }
Felix Held153f92a2020-12-08 17:27:30 +010075}