Marc Jones | 9ef6e52 | 2016-09-20 20:16:20 -0600 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * FCH IO access common routine |
| 6 | * |
| 7 | * |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: FCH |
Marshall Dawson | a040065 | 2016-10-15 09:20:43 -0600 | [diff] [blame] | 12 | * @e \$Revision$ @e \$Date$ |
Marc Jones | 9ef6e52 | 2016-09-20 20:16:20 -0600 | [diff] [blame] | 13 | * |
| 14 | */ |
| 15 | /***************************************************************************** |
| 16 | * |
Marshall Dawson | a040065 | 2016-10-15 09:20:43 -0600 | [diff] [blame] | 17 | * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. |
Marc Jones | 9ef6e52 | 2016-09-20 20:16:20 -0600 | [diff] [blame] | 18 | * All rights reserved. |
| 19 | * |
| 20 | * Redistribution and use in source and binary forms, with or without |
| 21 | * modification, are permitted provided that the following conditions are met: |
| 22 | * * Redistributions of source code must retain the above copyright |
| 23 | * notice, this list of conditions and the following disclaimer. |
| 24 | * * Redistributions in binary form must reproduce the above copyright |
| 25 | * notice, this list of conditions and the following disclaimer in the |
| 26 | * documentation and/or other materials provided with the distribution. |
| 27 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 28 | * its contributors may be used to endorse or promote products derived |
| 29 | * from this software without specific prior written permission. |
| 30 | * |
| 31 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 32 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 33 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 34 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 35 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 36 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 37 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 38 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 39 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 40 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 41 | * |
| 42 | ***************************************************************************/ |
Marshall Dawson | a040065 | 2016-10-15 09:20:43 -0600 | [diff] [blame] | 43 | |
Marc Jones | 9ef6e52 | 2016-09-20 20:16:20 -0600 | [diff] [blame] | 44 | #include "FchPlatform.h" |
Marshall Dawson | a040065 | 2016-10-15 09:20:43 -0600 | [diff] [blame] | 45 | #include "cpuFamilyTranslation.h" |
| 46 | //#include "Porting.h" |
| 47 | //#include "AMD.h" |
| 48 | //#include "amdlib.h" |
| 49 | #include "heapManager.h" |
Marc Jones | 9ef6e52 | 2016-09-20 20:16:20 -0600 | [diff] [blame] | 50 | #define FILECODE PROC_FCH_COMMON_FCHPELIB_FILECODE |
| 51 | |
| 52 | /*----------------------------------------------------------------------------------------*/ |
| 53 | /** |
| 54 | * ProgramPciByteTable - Program PCI register by table (8 bits data) |
| 55 | * |
| 56 | * |
| 57 | * |
| 58 | * @param[in] pPciByteTable - Table data pointer |
| 59 | * @param[in] dwTableSize - Table length |
| 60 | * @param[in] StdHeader |
| 61 | * |
| 62 | */ |
| 63 | VOID |
| 64 | ProgramPciByteTable ( |
| 65 | IN REG8_MASK *pPciByteTable, |
| 66 | IN UINT16 dwTableSize, |
| 67 | IN AMD_CONFIG_PARAMS *StdHeader |
| 68 | ) |
| 69 | { |
| 70 | UINT8 i; |
| 71 | UINT8 dbBusNo; |
| 72 | UINT8 dbDevFnNo; |
| 73 | UINT8 Or8; |
| 74 | UINT8 Mask8; |
| 75 | PCI_ADDR PciAddress; |
| 76 | |
| 77 | dbBusNo = pPciByteTable->RegIndex; |
| 78 | dbDevFnNo = pPciByteTable->AndMask; |
| 79 | pPciByteTable++; |
| 80 | |
| 81 | for ( i = 1; i < dwTableSize; i++ ) { |
| 82 | if ( (pPciByteTable->RegIndex == 0xFF) && (pPciByteTable->AndMask == 0xFF) && (pPciByteTable->OrMask == 0xFF) ) { |
| 83 | pPciByteTable++; |
| 84 | dbBusNo = pPciByteTable->RegIndex; |
| 85 | dbDevFnNo = pPciByteTable->AndMask; |
| 86 | pPciByteTable++; |
| 87 | i++; |
| 88 | } else { |
| 89 | PciAddress.AddressValue = (dbBusNo << 20) + (dbDevFnNo << 12) + pPciByteTable->RegIndex; |
| 90 | Or8 = pPciByteTable->OrMask; |
| 91 | Mask8 = ~pPciByteTable->AndMask; |
| 92 | LibAmdPciRMW (AccessWidth8, PciAddress, &Or8, &Mask8, StdHeader); |
| 93 | pPciByteTable++; |
| 94 | } |
| 95 | } |
| 96 | } |
| 97 | |
| 98 | /*----------------------------------------------------------------------------------------*/ |
| 99 | /** |
| 100 | * ProgramFchAcpiMmioTbl - Program FCH ACPI MMIO register by table (8 bits data) |
| 101 | * |
| 102 | * |
| 103 | * |
| 104 | * @param[in] pAcpiTbl - Table data pointer |
| 105 | * @param[in] StdHeader |
| 106 | * |
| 107 | */ |
| 108 | VOID |
| 109 | ProgramFchAcpiMmioTbl ( |
| 110 | IN ACPI_REG_WRITE *pAcpiTbl, |
| 111 | IN AMD_CONFIG_PARAMS *StdHeader |
| 112 | ) |
| 113 | { |
| 114 | UINT8 i; |
| 115 | UINT8 Or8; |
| 116 | UINT8 Mask8; |
| 117 | UINT32 ddtempVar; |
| 118 | |
| 119 | if (pAcpiTbl != NULL) { |
| 120 | if ((pAcpiTbl->MmioReg == 0) && (pAcpiTbl->MmioBase == 0) && (pAcpiTbl->DataAndMask == 0xB0) && (pAcpiTbl->DataOrMask == 0xAC)) { |
| 121 | // Signature Checking |
| 122 | pAcpiTbl++; |
| 123 | for ( i = 1; pAcpiTbl->MmioBase < 0x1D; i++ ) { |
| 124 | ddtempVar = ACPI_MMIO_BASE | (pAcpiTbl->MmioBase) << 8 | pAcpiTbl->MmioReg; |
| 125 | Or8 = pAcpiTbl->DataOrMask; |
| 126 | Mask8 = ~pAcpiTbl->DataAndMask; |
| 127 | LibAmdMemRMW (AccessWidth8, (UINT64) ddtempVar, &Or8, &Mask8, StdHeader); |
| 128 | pAcpiTbl++; |
| 129 | } |
| 130 | } |
| 131 | } |
| 132 | } |
| 133 | |
| 134 | /*----------------------------------------------------------------------------------------*/ |
| 135 | /** |
| 136 | * ProgramFchSciMapTbl - Program FCH SCI Map table (8 bits data) |
| 137 | * |
| 138 | * |
| 139 | * |
| 140 | * @param[in] pSciMapTbl - Table data pointer |
| 141 | * @param[in] FchResetDataBlock |
| 142 | * |
| 143 | */ |
| 144 | VOID |
| 145 | ProgramFchSciMapTbl ( |
| 146 | IN SCI_MAP_CONTROL *pSciMapTbl, |
| 147 | IN FCH_RESET_DATA_BLOCK *FchResetDataBlock |
| 148 | ) |
| 149 | { |
| 150 | AMD_CONFIG_PARAMS *StdHeader; |
| 151 | |
| 152 | UINT32 ddtempVar; |
| 153 | StdHeader = FchResetDataBlock->StdHeader; |
| 154 | |
| 155 | if (pSciMapTbl != NULL) { |
| 156 | while (pSciMapTbl->InputPin != 0xFF) { |
| 157 | if ((pSciMapTbl->InputPin >= 0x40) && (pSciMapTbl->InputPin < 0x80) && (pSciMapTbl->GpeMap < 0x20)) { |
| 158 | ddtempVar = ACPI_MMIO_BASE | SMI_BASE | pSciMapTbl->InputPin; |
| 159 | if (((pSciMapTbl->InputPin == FCH_SMI_xHC0Pme) && (FchResetDataBlock->FchReset.Xhci0Enable == 0)) || \ |
| 160 | ((pSciMapTbl->InputPin == FCH_SMI_xHC1Pme) && (FchResetDataBlock->FchReset.Xhci1Enable == 0))) { |
| 161 | } else { |
| 162 | LibAmdMemWrite (AccessWidth8, (UINT64) ddtempVar, &pSciMapTbl->GpeMap, StdHeader); |
| 163 | } |
| 164 | } else { |
| 165 | //Assert Warning "SCI map is invalid" |
| 166 | } |
| 167 | pSciMapTbl++; |
| 168 | } |
| 169 | } |
| 170 | } |
| 171 | |
| 172 | /*----------------------------------------------------------------------------------------*/ |
| 173 | /** |
| 174 | * ProgramFchGpioTbl - Program FCH Gpio table (8 bits data) |
| 175 | * |
| 176 | * |
| 177 | * |
| 178 | * @param[in] pGpioTbl - Table data pointer |
| 179 | * |
| 180 | */ |
| 181 | VOID |
| 182 | ProgramFchGpioTbl ( |
| 183 | IN GPIO_CONTROL *pGpioTbl |
| 184 | ) |
| 185 | { |
| 186 | if (pGpioTbl != NULL) { |
| 187 | while (pGpioTbl->GpioPin != 0xFF) { |
Marshall Dawson | a040065 | 2016-10-15 09:20:43 -0600 | [diff] [blame] | 188 | ACPIMMIO8 (ACPI_MMIO_BASE + IOMUX_BASE + pGpioTbl->GpioPin) = (UINT8) (pGpioTbl->PinFunction); |
| 189 | ACPIMMIO8 (ACPI_MMIO_BASE + GPIO_BANK0_BASE + (pGpioTbl->GpioPin << 2) + 2) = (UINT8) (pGpioTbl->CfgByte); |
Marc Jones | 9ef6e52 | 2016-09-20 20:16:20 -0600 | [diff] [blame] | 190 | pGpioTbl++; |
| 191 | } |
| 192 | } |
| 193 | } |
| 194 | |
| 195 | /*----------------------------------------------------------------------------------------*/ |
| 196 | /** |
| 197 | * ProgramSataPhyTbl - Program FCH Sata Phy table (8 bits data) |
| 198 | * |
| 199 | * |
| 200 | * |
| 201 | * @param[in] pSataPhyTbl - Table data pointer |
| 202 | * @param[in] FchResetDataBlock |
| 203 | * |
| 204 | */ |
| 205 | VOID |
| 206 | ProgramFchSataPhyTbl ( |
| 207 | IN SATA_PHY_CONTROL *pSataPhyTbl, |
| 208 | IN FCH_RESET_DATA_BLOCK *FchResetDataBlock |
| 209 | ) |
| 210 | { |
| 211 | if (pSataPhyTbl != NULL) { |
| 212 | while (pSataPhyTbl->PhyData != 0xFFFFFFFF) { |
| 213 | //to be implemented |
| 214 | pSataPhyTbl++; |
| 215 | } |
| 216 | } |
| 217 | } |
| 218 | |
| 219 | /** |
| 220 | * GetChipSysMode - Get Chip status |
| 221 | * |
| 222 | * |
| 223 | * @param[in] Value - Return Chip strap status |
| 224 | * StrapStatus [15.0] - Hudson-2 chip Strap Status |
| 225 | * @li <b>0001</b> - Not USED FWH |
| 226 | * @li <b>0002</b> - Not USED LPC ROM |
| 227 | * @li <b>0004</b> - EC enabled |
| 228 | * @li <b>0008</b> - Reserved |
| 229 | * @li <b>0010</b> - Internal Clock mode |
| 230 | * @param[in] StdHeader |
| 231 | * |
| 232 | */ |
| 233 | VOID |
| 234 | GetChipSysMode ( |
| 235 | IN VOID *Value, |
| 236 | IN AMD_CONFIG_PARAMS *StdHeader |
| 237 | ) |
| 238 | { |
| 239 | LibAmdMemRead (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG80), Value, StdHeader); |
| 240 | } |
| 241 | |
| 242 | /** |
| 243 | * IsImcEnabled - Is IMC Enabled |
| 244 | * @retval TRUE for IMC Enabled; FALSE for IMC Disabled |
| 245 | */ |
| 246 | BOOLEAN |
| 247 | IsImcEnabled ( |
| 248 | IN AMD_CONFIG_PARAMS *StdHeader |
| 249 | ) |
| 250 | { |
| 251 | UINT8 dbSysConfig; |
| 252 | GetChipSysMode (&dbSysConfig, StdHeader); |
| 253 | if (dbSysConfig & ChipSysEcEnable) { |
| 254 | return TRUE; |
| 255 | } else { |
| 256 | return FALSE; |
| 257 | } |
| 258 | } |
| 259 | |
| 260 | |
| 261 | /** |
| 262 | * GetEfuseStatue - Get Efuse status |
| 263 | * |
| 264 | * |
| 265 | * @param[in] Value - Return Chip strap status |
| 266 | * @param[in] StdHeader |
| 267 | * |
| 268 | */ |
| 269 | VOID |
| 270 | GetEfuseStatus ( |
| 271 | IN VOID *Value, |
| 272 | IN AMD_CONFIG_PARAMS *StdHeader |
| 273 | ) |
| 274 | { |
| 275 | UINT8 Or8; |
| 276 | UINT8 Mask8; |
| 277 | |
| 278 | Or8 = BIT5; |
| 279 | Mask8 = BIT5; |
| 280 | LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC8), &Or8, &Mask8, StdHeader); |
| 281 | LibAmdMemWrite (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD8), Value, StdHeader); |
| 282 | LibAmdMemRead (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD8 + 1), Value, StdHeader); |
| 283 | Or8 = 0; |
| 284 | Mask8 = BIT5; |
| 285 | LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC8), &Or8, &Mask8, StdHeader); |
| 286 | } |
| 287 | |
| 288 | /*----------------------------------------------------------------------------------------*/ |
| 289 | /** |
| 290 | * SbSleepTrapControl - SB Sleep Trap Control |
| 291 | * |
| 292 | * |
| 293 | * |
| 294 | * @param[in] SleepTrap - Whether sleep trap is enabled |
| 295 | * |
| 296 | */ |
| 297 | VOID |
| 298 | SbSleepTrapControl ( |
| 299 | IN BOOLEAN SleepTrap |
| 300 | ) |
| 301 | { |
| 302 | if (SleepTrap) { |
| 303 | ACPIMMIO32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB0) &= ~(BIT2 + BIT3); |
| 304 | ACPIMMIO32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB0) |= BIT2; |
| 305 | |
| 306 | ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGBE) &= ~ (BIT5); |
| 307 | ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xB) &= ~ (BIT0 + BIT1); |
| 308 | ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xB) |= BIT1; |
| 309 | } else { |
| 310 | ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGBE) |= BIT5; |
| 311 | ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xB) &= ~ (BIT0 + BIT1); |
| 312 | ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xB) |= BIT0; |
| 313 | |
| 314 | ACPIMMIO32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB0) &= ~(BIT2 + BIT3); |
| 315 | } |
| 316 | } |
Marshall Dawson | a040065 | 2016-10-15 09:20:43 -0600 | [diff] [blame] | 317 | |
| 318 | /** |
| 319 | * FchUsb3D3ColdCallback - Fch Usb3 D3Cold Callback |
| 320 | * |
| 321 | * |
| 322 | * @param[in] FchDataPtr |
| 323 | * |
| 324 | */ |
| 325 | VOID |
| 326 | FchUsb3D3ColdCallback ( |
| 327 | IN VOID *FchDataPtr |
| 328 | ) |
| 329 | { |
| 330 | FCH_DATA_BLOCK *LocalCfgPtr; |
| 331 | AMD_CONFIG_PARAMS *StdHeader; |
| 332 | UINT8 Value8; |
| 333 | |
| 334 | LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; |
| 335 | StdHeader = LocalCfgPtr->StdHeader; |
| 336 | //FCH_DEADLOOP (); |
| 337 | ACPIMMIO32 (FCH_AOACxA0_PwrGood_Control) |= FCH_AOACxA0_PwrGood_Control_SwUsb3SlpShutdown; |
| 338 | do { |
| 339 | } while ((ACPIMMIO32 (FCH_AOACxA0_PwrGood_Control) & FCH_AOACxA0_PwrGood_Control_SwUsb3SlpShutdown) == 0); |
| 340 | |
| 341 | ACPIMMIO32 (FCH_XHC_PMx00_Configure0) |= FCH_XHC_PMx00_Configure0_U3P_D3Cold_PWRDN; |
| 342 | |
| 343 | ACPIMMIO8 (FCH_AOACx6E_USB3_D3_CONTROL) &= ~ (AOAC_PWR_ON_DEV); |
| 344 | do { |
| 345 | } while ((ACPIMMIO8 (FCH_AOACx6F_USB3_D3_STATE) & 0x07) != 0); |
| 346 | |
| 347 | ACPIMMIO8 (FCH_AOACx6E_USB3_D3_CONTROL) |= 3; |
| 348 | |
| 349 | ACPIMMIO32 (FCH_MISCx28_ClkDrvStr2) |= FCH_MISCx28_ClkDrvStr2_USB3_RefClk_Pwdn; |
| 350 | |
| 351 | if ((ACPIMMIO8 (FCH_AOACx64_EHCI_D3_CONTROL) & 0x03) == 3) { |
| 352 | ACPIMMIO32 (FCH_AOACxA0_PwrGood_Control) &= ~ (FCH_AOACxA0_PwrGood_Control_SwUsb2S5RstB + FCH_AOACxA0_PwrGood_Control_SwUsb3SlpShutdown); |
| 353 | ACPIMMIO32 (FCH_MISCx28_ClkDrvStr2) |= FCH_MISCx28_ClkDrvStr2_USB2_RefClk_Pwdn; |
| 354 | } |
| 355 | |
| 356 | ACPIMMIO32 (FCH_AOACxA0_PwrGood_Control) &= ~ (FCH_AOACxA0_PwrGood_Control_XhcPwrGood + FCH_AOACxA0_PwrGood_Control_SwUsb3SlpShutdown); |
| 357 | Value8 = ACPIMMIO8 (0xFED803EE); |
| 358 | Value8 &= 0xFC; |
| 359 | Value8 |= 0x01; |
| 360 | ACPIMMIO8 (0xFED803EE) = Value8; |
| 361 | } |
| 362 | |
| 363 | /** |
| 364 | * FchUsb3D0Callback - Fch Usb3 D0 Callback |
| 365 | * |
| 366 | * |
| 367 | * @param[in] FchDataPtr |
| 368 | * |
| 369 | */ |
| 370 | VOID |
| 371 | FchUsb3D0Callback ( |
| 372 | IN VOID *FchDataPtr |
| 373 | ) |
| 374 | { |
| 375 | FCH_DATA_BLOCK *LocalCfgPtr; |
| 376 | AMD_CONFIG_PARAMS *StdHeader; |
| 377 | UINT32 Dword32; |
| 378 | |
| 379 | LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; |
| 380 | StdHeader = LocalCfgPtr->StdHeader; |
| 381 | |
| 382 | ACPIMMIO8 (0xFED803EE) &= 0xFC; |
| 383 | |
| 384 | ACPIMMIO8 (FCH_AOACxA0_PwrGood_Control) |= (FCH_AOACxA0_PwrGood_Control_XhcPwrGood); |
| 385 | ACPIMMIO32 (FCH_MISCx28_ClkDrvStr2) &= ~ (FCH_MISCx28_ClkDrvStr2_USB2_RefClk_Pwdn); |
| 386 | ACPIMMIO32 (FCH_MISCx28_ClkDrvStr2) &= ~ (FCH_MISCx28_ClkDrvStr2_USB3_RefClk_Pwdn); |
| 387 | Dword32 = ACPIMMIO32 (FCH_AOACxA0_PwrGood_Control); |
| 388 | Dword32 &= ~(FCH_AOACxA0_PwrGood_Control_SwUsb3SlpShutdown); |
| 389 | ACPIMMIO32 (FCH_AOACxA0_PwrGood_Control) = ((FCH_AOACxA0_PwrGood_Control_SwUsb2S5RstB | Dword32) & (~ BIT29)); |
| 390 | |
| 391 | ACPIMMIO8 (FCH_AOACx6E_USB3_D3_CONTROL) &= 0xFC; |
| 392 | ACPIMMIO8 (FCH_AOACx6E_USB3_D3_CONTROL) |= (AOAC_PWR_ON_DEV); |
| 393 | do { |
| 394 | } while ((ACPIMMIO8 (FCH_AOACx6F_USB3_D3_STATE) & 0x07) != 7); |
| 395 | |
| 396 | do { |
| 397 | } while ((ACPIMMIO32 (FCH_XHC_PMx00_Configure0) & BIT7) != BIT7); |
| 398 | |
| 399 | ACPIMMIO32 (FCH_XHC_PMx00_Configure0) &= ~ (BIT16); |
| 400 | |
| 401 | } |
| 402 | |
| 403 | /* -----------------------------------------------------------------------------*/ |
| 404 | /** |
| 405 | * |
| 406 | * |
| 407 | * This function Checks Bristol or Stoney |
| 408 | * |
| 409 | * NOTE: |
| 410 | * |
| 411 | * @param[in] StdHeader |
| 412 | * |
| 413 | */ |
| 414 | BOOLEAN |
| 415 | FchCheckBR_ST ( |
| 416 | IN AMD_CONFIG_PARAMS *StdHeader |
| 417 | ) |
| 418 | { |
| 419 | CPU_LOGICAL_ID LogicalId; |
| 420 | |
| 421 | // Only initialize on CZ processors, otherwise exit. |
| 422 | GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); |
| 423 | if ((LogicalId.Revision & AMD_F15_BR_ALL) != 0) { |
| 424 | return TRUE; |
| 425 | } |
| 426 | if ((LogicalId.Revision & AMD_F15_ST_ALL) != 0) { |
| 427 | return TRUE; |
| 428 | } |
| 429 | |
| 430 | return FALSE; |
| 431 | } |
| 432 | |
| 433 | /* -----------------------------------------------------------------------------*/ |
| 434 | /** |
| 435 | * |
| 436 | * |
| 437 | * This function Checks Bristol |
| 438 | * |
| 439 | * NOTE: |
| 440 | * |
| 441 | * @param[in] StdHeader |
| 442 | * |
| 443 | */ |
| 444 | BOOLEAN |
| 445 | FchCheckBR ( |
| 446 | IN AMD_CONFIG_PARAMS *StdHeader |
| 447 | ) |
| 448 | { |
| 449 | CPU_LOGICAL_ID LogicalId; |
| 450 | |
| 451 | // Only initialize on CZ processors, otherwise exit. |
| 452 | GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); |
| 453 | if ((LogicalId.Revision & AMD_F15_BR_ALL) != 0) { |
| 454 | return TRUE; |
| 455 | } |
| 456 | |
| 457 | return FALSE; |
| 458 | } |
| 459 | |
| 460 | /* -----------------------------------------------------------------------------*/ |
| 461 | /** |
| 462 | * |
| 463 | * |
| 464 | * This function Checks Stoney |
| 465 | * |
| 466 | * NOTE: |
| 467 | * |
| 468 | * @param[in] StdHeader |
| 469 | * |
| 470 | */ |
| 471 | BOOLEAN |
| 472 | FchCheckST ( |
| 473 | IN AMD_CONFIG_PARAMS *StdHeader |
| 474 | ) |
| 475 | { |
| 476 | CPU_LOGICAL_ID LogicalId; |
| 477 | |
| 478 | // Only initialize on CZ processors, otherwise exit. |
| 479 | GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); |
| 480 | if ((LogicalId.Revision & AMD_F15_ST_ALL) != 0) { |
| 481 | return TRUE; |
| 482 | } |
| 483 | |
| 484 | return FALSE; |
| 485 | } |
| 486 | |
| 487 | /* -----------------------------------------------------------------------------*/ |
| 488 | /** |
| 489 | * |
| 490 | * |
| 491 | * This function Checks Carrizo |
| 492 | * |
| 493 | * NOTE: |
| 494 | * |
| 495 | * @param[in] StdHeader |
| 496 | * |
| 497 | */ |
| 498 | BOOLEAN |
| 499 | FchCheckCZ ( |
| 500 | IN AMD_CONFIG_PARAMS *StdHeader |
| 501 | ) |
| 502 | { |
| 503 | CPU_LOGICAL_ID LogicalId; |
| 504 | |
| 505 | // Only initialize on CZ processors, otherwise exit. |
| 506 | GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); |
| 507 | if ((LogicalId.Revision & AMD_F15_CZ_ALL) != 0) { |
| 508 | return TRUE; |
| 509 | } |
| 510 | |
| 511 | return FALSE; |
| 512 | } |
| 513 | |
| 514 | /* -----------------------------------------------------------------------------*/ |
| 515 | /** |
| 516 | * |
| 517 | * |
| 518 | * This function Checks Package AM4 |
| 519 | * |
| 520 | * NOTE: |
| 521 | * |
| 522 | * @param[in] StdHeader |
| 523 | * |
| 524 | */ |
| 525 | BOOLEAN |
| 526 | FchCheckPackageAM4 ( |
| 527 | IN AMD_CONFIG_PARAMS *StdHeader |
| 528 | ) |
| 529 | { |
| 530 | CPUID_DATA CpuId; |
| 531 | UINT8 RegValue; |
| 532 | |
| 533 | LibAmdCpuidRead (AMD_CPUID_FMF, &CpuId, StdHeader); |
| 534 | RegValue = (UINT8) (CpuId.EBX_Reg >> 28) & 0xF; // bit 31:28 |
| 535 | ///@todo - update the PkgType once it is reflected in BKDG |
| 536 | if (RegValue == 2) { |
| 537 | return TRUE; |
| 538 | } else { |
| 539 | return FALSE; |
| 540 | } |
| 541 | } |
| 542 | |
| 543 | /* -----------------------------------------------------------------------------*/ |
| 544 | /** |
| 545 | * |
| 546 | * |
| 547 | * This function Get Scratch Fuse |
| 548 | * |
| 549 | * NOTE: |
| 550 | * |
| 551 | * @param[in] StdHeader |
| 552 | * |
| 553 | */ |
| 554 | UINT64 |
| 555 | FchGetScratchFuse ( |
| 556 | IN AMD_CONFIG_PARAMS *StdHeader |
| 557 | ) |
| 558 | { |
| 559 | PCI_ADDR D0F0xB8_SMU_Index_Address; |
| 560 | PCI_ADDR D0F0xBC_SMU_Index_Data; |
| 561 | UINT64 TempData64; |
| 562 | UINT32 TempData32; |
| 563 | |
| 564 | D0F0xB8_SMU_Index_Address.AddressValue = (MAKE_SBDFO (0, 0, 0, 0, 0xB8)); |
| 565 | D0F0xBC_SMU_Index_Data.AddressValue = (MAKE_SBDFO (0, 0, 0, 0, 0xBC)); |
| 566 | TempData64 = 0; |
| 567 | TempData32 = 0xC0016028; |
| 568 | LibAmdPciWrite (AccessWidth32, D0F0xB8_SMU_Index_Address, &TempData32, StdHeader); |
| 569 | LibAmdPciRead (AccessWidth32, D0F0xBC_SMU_Index_Data, &TempData32, StdHeader); |
| 570 | TempData64 |= (((UINT64) TempData32) & 0xFFFFFFFF) >> 9; |
| 571 | TempData32 = 0xC001602C; |
| 572 | LibAmdPciWrite (AccessWidth32, D0F0xB8_SMU_Index_Address, &TempData32, StdHeader); |
| 573 | LibAmdPciRead (AccessWidth32, D0F0xBC_SMU_Index_Data, &TempData32, StdHeader); |
| 574 | TempData64 |= (((UINT64) TempData32) & 0xFFFFFFFF) << (32 - 9); |
| 575 | TempData32 = 0xC0016030; |
| 576 | LibAmdPciWrite (AccessWidth32, D0F0xB8_SMU_Index_Address, &TempData32, StdHeader); |
| 577 | LibAmdPciRead (AccessWidth32, D0F0xBC_SMU_Index_Data, &TempData32, StdHeader); |
| 578 | TempData64 |= (((UINT64) TempData32) & 0xFFFFFFFF) << (64 - 9); |
| 579 | |
| 580 | return TempData64; |
| 581 | } |