Marc Jones | 9ef6e52 | 2016-09-20 20:16:20 -0600 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * FCH IO access common routine |
| 6 | * |
| 7 | * |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: FCH |
Marshall Dawson | a040065 | 2016-10-15 09:20:43 -0600 | [diff] [blame] | 12 | * @e \$Revision$ @e \$Date$ |
Marc Jones | 9ef6e52 | 2016-09-20 20:16:20 -0600 | [diff] [blame] | 13 | * |
| 14 | */ |
| 15 | /***************************************************************************** |
| 16 | * |
Marshall Dawson | a040065 | 2016-10-15 09:20:43 -0600 | [diff] [blame] | 17 | * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. |
Marc Jones | 9ef6e52 | 2016-09-20 20:16:20 -0600 | [diff] [blame] | 18 | * All rights reserved. |
| 19 | * |
| 20 | * Redistribution and use in source and binary forms, with or without |
| 21 | * modification, are permitted provided that the following conditions are met: |
| 22 | * * Redistributions of source code must retain the above copyright |
| 23 | * notice, this list of conditions and the following disclaimer. |
| 24 | * * Redistributions in binary form must reproduce the above copyright |
| 25 | * notice, this list of conditions and the following disclaimer in the |
| 26 | * documentation and/or other materials provided with the distribution. |
| 27 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 28 | * its contributors may be used to endorse or promote products derived |
| 29 | * from this software without specific prior written permission. |
| 30 | * |
| 31 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 32 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 33 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 34 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 35 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 36 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 37 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 38 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 39 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 40 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 41 | * |
| 42 | ***************************************************************************/ |
| 43 | #include "FchPlatform.h" |
| 44 | #define FILECODE PROC_FCH_COMMON_FCHLIB_FILECODE |
| 45 | |
| 46 | /**< FchStall - Reserved */ |
| 47 | VOID |
| 48 | FchStall ( |
| 49 | IN UINT32 uSec, |
| 50 | IN AMD_CONFIG_PARAMS *StdHeader |
| 51 | ) |
| 52 | { |
| 53 | UINT16 timerAddr; |
| 54 | UINT32 startTime; |
| 55 | UINT32 elapsedTime; |
| 56 | |
| 57 | LibAmdMemRead (AccessWidth16, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG64), &timerAddr, StdHeader); |
| 58 | if ( timerAddr == 0 ) { |
| 59 | uSec = uSec / 2; |
| 60 | while ( uSec != 0 ) { |
| 61 | LibAmdIoRead (AccessWidth8, FCHOEM_IO_DELAY_PORT, (UINT8 *) (&startTime), StdHeader); |
| 62 | uSec--; |
| 63 | } |
| 64 | } else { |
| 65 | LibAmdIoRead (AccessWidth32, timerAddr, &startTime, StdHeader); |
| 66 | for ( ;; ) { |
| 67 | LibAmdIoRead (AccessWidth32, timerAddr, &elapsedTime, StdHeader); |
| 68 | if ( elapsedTime < startTime ) { |
| 69 | elapsedTime = elapsedTime + FCH_MAX_TIMER - startTime; |
| 70 | } else { |
| 71 | elapsedTime = elapsedTime - startTime; |
| 72 | } |
| 73 | if ( (elapsedTime * FCHOEM_ELAPSED_TIME_UNIT / FCHOEM_ELAPSED_TIME_DIVIDER) > uSec ) { |
| 74 | break; |
| 75 | } |
| 76 | } |
| 77 | } |
| 78 | } |
| 79 | |
| 80 | /**< cimFchStall - Reserved */ |
| 81 | VOID |
| 82 | CimFchStall ( |
| 83 | IN UINT32 uSec, |
| 84 | IN AMD_CONFIG_PARAMS *StdHeader |
| 85 | ) |
| 86 | { |
| 87 | UINT16 timerAddr; |
| 88 | UINT32 startTime; |
| 89 | UINT32 elapsedTime; |
| 90 | |
| 91 | LibAmdMemRead (AccessWidth16, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG64), &timerAddr, StdHeader); |
| 92 | if ( timerAddr == 0 ) { |
| 93 | uSec = uSec / 2; |
| 94 | while ( uSec != 0 ) { |
| 95 | LibAmdIoRead (AccessWidth8, FCHOEM_IO_DELAY_PORT, (UINT8*)&elapsedTime, StdHeader); |
| 96 | uSec--; |
| 97 | } |
| 98 | } else { |
| 99 | LibAmdIoRead (AccessWidth32, timerAddr, &startTime, StdHeader); |
| 100 | for ( ;; ) { |
| 101 | LibAmdIoRead (AccessWidth32, timerAddr, &elapsedTime, StdHeader); |
| 102 | if ( elapsedTime < startTime ) { |
| 103 | elapsedTime = elapsedTime + FCH_MAX_TIMER - startTime; |
| 104 | } else { |
| 105 | elapsedTime = elapsedTime - startTime; |
| 106 | } |
| 107 | if ( (elapsedTime * FCHOEM_ELAPSED_TIME_UNIT / FCHOEM_ELAPSED_TIME_DIVIDER) > uSec ) { |
| 108 | break; |
| 109 | } |
| 110 | } |
| 111 | } |
| 112 | } |
| 113 | |
| 114 | /**< FchReset - Reserved */ |
| 115 | VOID |
| 116 | FchPciReset ( |
| 117 | IN AMD_CONFIG_PARAMS *StdHeader |
| 118 | ) |
| 119 | { |
| 120 | UINT8 PciRstValue; |
| 121 | |
| 122 | PciRstValue = 0x06; |
| 123 | LibAmdIoWrite (AccessWidth8, FCH_PCIRST_BASE_IO, &PciRstValue, StdHeader); |
| 124 | } |
| 125 | |
| 126 | /**< outPort80 - Reserved */ |
| 127 | VOID |
| 128 | OutPort80 ( |
| 129 | IN UINT32 pcode, |
| 130 | IN AMD_CONFIG_PARAMS *StdHeader |
| 131 | ) |
| 132 | { |
| 133 | LibAmdIoWrite (AccessWidth8, FCHOEM_OUTPUT_DEBUG_PORT, &pcode, StdHeader); |
| 134 | return; |
| 135 | } |
| 136 | |
| 137 | /**< outPort1080 - Reserved */ |
| 138 | VOID |
| 139 | OutPort1080 ( |
| 140 | IN UINT32 pcode, |
| 141 | IN AMD_CONFIG_PARAMS *StdHeader |
| 142 | ) |
| 143 | { |
| 144 | LibAmdIoWrite (AccessWidth32, 0x1080, &pcode, StdHeader); |
| 145 | return; |
| 146 | } |
| 147 | |
| 148 | /**< FchCopyMem - Reserved */ |
| 149 | VOID |
| 150 | FchCopyMem ( |
| 151 | IN VOID* pDest, |
| 152 | IN VOID* pSource, |
| 153 | IN UINTN Length |
| 154 | ) |
| 155 | { |
| 156 | UINTN i; |
| 157 | UINT8 *Ptr; |
| 158 | UINT8 *Source; |
| 159 | Ptr = (UINT8*)pDest; |
| 160 | Source = (UINT8*)pSource; |
| 161 | for (i = 0; i < Length; i++) { |
| 162 | *Ptr = *Source; |
| 163 | Source++; |
| 164 | Ptr++; |
| 165 | } |
| 166 | } |
| 167 | |
| 168 | /** GetRomSigPtr - Reserved **/ |
| 169 | VOID* |
| 170 | GetRomSigPtr ( |
| 171 | IN UINTN *RomSigPtr, |
| 172 | IN AMD_CONFIG_PARAMS *StdHeader |
| 173 | ) |
| 174 | { |
| 175 | UINT32 RomPtr; |
| 176 | UINT32 RomSig; |
| 177 | UINT16 MswAddr; |
| 178 | |
| 179 | *RomSigPtr = 0; |
| 180 | MswAddr = 0xFF00; |
| 181 | do { |
| 182 | RomPtr = (MswAddr << 16) + FCH_ROMSIG_BASE_IO; |
| 183 | LibAmdMemRead (AccessWidth32, (UINT64) RomPtr, &RomSig, StdHeader); |
| 184 | if (RomSig == FCH_ROMSIG_SIGNATURE) { |
| 185 | *RomSigPtr = RomPtr; |
| 186 | break; |
| 187 | } |
| 188 | MswAddr >>= 1; |
| 189 | MswAddr |= BIT15; |
| 190 | } while (MswAddr != 0xFFF8); |
| 191 | return RomSigPtr; |
| 192 | } |
| 193 | |
| 194 | /** RwXhciIndReg - Reserved **/ |
| 195 | VOID |
| 196 | RwXhciIndReg ( |
| 197 | IN UINT32 Index, |
| 198 | IN UINT32 AndMask, |
| 199 | IN UINT32 OrMask, |
| 200 | IN AMD_CONFIG_PARAMS *StdHeader |
| 201 | ) |
| 202 | { |
| 203 | UINT32 RevReg; |
| 204 | PCI_ADDR PciAddress; |
| 205 | |
| 206 | PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x48; |
| 207 | LibAmdPciWrite (AccessWidth32, PciAddress, &Index, StdHeader); |
| 208 | PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x4C; |
| 209 | RevReg = ~AndMask; |
| 210 | LibAmdPciRMW (AccessWidth32, PciAddress, &OrMask, &RevReg, StdHeader); |
| 211 | |
| 212 | PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x48; |
| 213 | LibAmdPciWrite (AccessWidth32, PciAddress, &Index, StdHeader); |
| 214 | PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x4C; |
| 215 | RevReg = ~AndMask; |
| 216 | LibAmdPciRMW (AccessWidth32, PciAddress, &OrMask, &RevReg, StdHeader); |
| 217 | } |
| 218 | |
| 219 | /** RwXhci0IndReg - Reserved **/ |
| 220 | VOID |
| 221 | RwXhci0IndReg ( |
| 222 | IN UINT32 Index, |
| 223 | IN UINT32 AndMask, |
| 224 | IN UINT32 OrMask, |
| 225 | IN AMD_CONFIG_PARAMS *StdHeader |
| 226 | ) |
| 227 | { |
| 228 | UINT32 RevReg; |
| 229 | PCI_ADDR PciAddress; |
| 230 | |
| 231 | PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x48; |
| 232 | LibAmdPciWrite (AccessWidth32, PciAddress, &Index, StdHeader); |
| 233 | PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x4C; |
| 234 | RevReg = ~AndMask; |
| 235 | LibAmdPciRMW (AccessWidth32, PciAddress, &OrMask, &RevReg, StdHeader); |
| 236 | } |
| 237 | |
| 238 | /** RwXhci1IndReg - Reserved **/ |
| 239 | VOID |
| 240 | RwXhci1IndReg ( |
| 241 | IN UINT32 Index, |
| 242 | IN UINT32 AndMask, |
| 243 | IN UINT32 OrMask, |
| 244 | IN AMD_CONFIG_PARAMS *StdHeader |
| 245 | ) |
| 246 | { |
| 247 | UINT32 RevReg; |
| 248 | PCI_ADDR PciAddress; |
| 249 | |
| 250 | PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x48; |
| 251 | LibAmdPciWrite (AccessWidth32, PciAddress, &Index, StdHeader); |
| 252 | PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x4C; |
| 253 | RevReg = ~AndMask; |
| 254 | LibAmdPciRMW (AccessWidth32, PciAddress, &OrMask, &RevReg, StdHeader); |
| 255 | } |
| 256 | |
| 257 | /** ReadXhci0Phy - Reserved **/ |
| 258 | VOID |
| 259 | ReadXhci0Phy ( |
| 260 | IN UINT32 Port, |
| 261 | IN UINT32 Address, |
| 262 | IN UINT32 *Value, |
| 263 | IN AMD_CONFIG_PARAMS *StdHeader |
| 264 | ) |
| 265 | { |
| 266 | UINT32 RegIndex; |
| 267 | UINT32 RegValue; |
| 268 | PCI_ADDR PciAddress; |
| 269 | |
| 270 | RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + Address, StdHeader); |
| 271 | |
| 272 | RegIndex = FCH_XHCI_IND60_REG04; |
| 273 | PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x48; |
| 274 | LibAmdPciWrite (AccessWidth32, PciAddress, &RegIndex, StdHeader); |
| 275 | PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x4C; |
| 276 | LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader); |
| 277 | |
| 278 | (*Value) = ( RegValue >> (Port * 8)) & 0x000000FF; |
| 279 | } |
| 280 | |
| 281 | /** ReadXhci1Phy - Reserved **/ |
| 282 | VOID |
| 283 | ReadXhci1Phy ( |
| 284 | IN UINT32 Port, |
| 285 | IN UINT32 Address, |
| 286 | IN UINT32 *Value, |
| 287 | IN AMD_CONFIG_PARAMS *StdHeader |
| 288 | ) |
| 289 | { |
| 290 | UINT32 RegIndex; |
| 291 | UINT32 RegValue; |
| 292 | PCI_ADDR PciAddress; |
| 293 | |
| 294 | RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + Address, StdHeader); |
| 295 | |
| 296 | RegIndex = FCH_XHCI_IND60_REG04; |
| 297 | PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x48; |
| 298 | LibAmdPciWrite (AccessWidth32, PciAddress, &RegIndex, StdHeader); |
| 299 | PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x4C; |
| 300 | LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader); |
| 301 | |
| 302 | (*Value) = ( RegValue >> (Port * 8)) & 0x000000FF; |
| 303 | } |
| 304 | |
| 305 | /** AcLossControl - Reserved **/ |
| 306 | VOID |
| 307 | AcLossControl ( |
| 308 | IN UINT8 AcLossControlValue |
| 309 | ) |
| 310 | { |
| 311 | AcLossControlValue &= 0x03; |
| 312 | AcLossControlValue |= BIT2; |
| 313 | RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG5B, AccessWidth8, 0xF0, AcLossControlValue); |
| 314 | } |
| 315 | |
| 316 | /** RecordFchConfigPtr - Reserved **/ |
| 317 | VOID |
| 318 | RecordFchConfigPtr ( |
| 319 | IN UINT32 FchConfigPtr |
| 320 | ) |
| 321 | { |
| 322 | RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x08, AccessWidth8, 0, (UINT8) ((FchConfigPtr >> 0) & 0xFF) ); |
| 323 | RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x09, AccessWidth8, 0, (UINT8) ((FchConfigPtr >> 8) & 0xFF) ); |
| 324 | RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0A, AccessWidth8, 0, (UINT8) ((FchConfigPtr >> 16) & 0xFF) ); |
| 325 | RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0B, AccessWidth8, 0, (UINT8) ((FchConfigPtr >> 24) & 0xFF) ); |
| 326 | } |
| 327 | |
| 328 | /** ReadAlink - Reserved **/ |
| 329 | UINT32 |
| 330 | ReadAlink ( |
| 331 | IN UINT32 Index, |
| 332 | IN AMD_CONFIG_PARAMS *StdHeader |
| 333 | ) |
| 334 | { |
| 335 | UINT32 Data; |
| 336 | LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &Index, StdHeader); |
| 337 | LibAmdIoRead (AccessWidth32, ALINK_ACCESS_DATA, &Data, StdHeader); |
| 338 | //Clear Index |
| 339 | Index = 0; |
| 340 | LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &Index, StdHeader); |
| 341 | return Data; |
| 342 | } |
| 343 | |
| 344 | /** WriteAlink - Reserved **/ |
| 345 | VOID |
| 346 | WriteAlink ( |
| 347 | IN UINT32 Index, |
| 348 | IN UINT32 Data, |
| 349 | IN AMD_CONFIG_PARAMS *StdHeader |
| 350 | ) |
| 351 | { |
| 352 | LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &Index, StdHeader); |
| 353 | LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_DATA, &Data, StdHeader); |
| 354 | //Clear Index |
| 355 | Index = 0; |
| 356 | LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &Index, StdHeader); |
| 357 | } |
| 358 | |
| 359 | /** RwAlink - Reserved **/ |
| 360 | VOID |
| 361 | RwAlink ( |
| 362 | IN UINT32 Index, |
| 363 | IN UINT32 AndMask, |
| 364 | IN UINT32 OrMask, |
| 365 | IN AMD_CONFIG_PARAMS *StdHeader |
| 366 | ) |
| 367 | { |
| 368 | UINT32 AccessType; |
| 369 | |
| 370 | AccessType = Index & 0xE0000000; |
| 371 | if (AccessType == (AXINDC << 29)) { |
| 372 | WriteAlink ((FCH_AX_INDXC_REG30 | AccessType), Index & 0x1FFFFFFF, StdHeader); |
| 373 | Index = FCH_AX_DATAC_REG34 | AccessType; |
| 374 | } else if (AccessType == (AXINDP << 29)) { |
| 375 | WriteAlink ((FCH_AX_INDXP_REG38 | AccessType), Index & 0x1FFFFFFF, StdHeader); |
| 376 | Index = FCH_AX_DATAP_REG3C | AccessType; |
| 377 | } |
Marshall Dawson | f309388 | 2016-10-15 09:45:44 -0600 | [diff] [blame^] | 378 | WriteAlink (Index, (ReadAlink (Index, StdHeader) & AndMask) | OrMask, StdHeader); |
Marc Jones | 9ef6e52 | 2016-09-20 20:16:20 -0600 | [diff] [blame] | 379 | } |
| 380 | |
| 381 | |
| 382 | /*----------------------------------------------------------------------------------------*/ |
| 383 | /** |
| 384 | * Read PMIO |
| 385 | * |
| 386 | * |
| 387 | * |
| 388 | * @param[in] Address - PMIO Offset value |
| 389 | * @param[in] OpFlag - Access sizes |
| 390 | * @param[in] Value - Read Data Buffer |
| 391 | * @param[in] StdHeader |
| 392 | * |
| 393 | */ |
| 394 | VOID |
| 395 | ReadPmio ( |
| 396 | IN UINT8 Address, |
| 397 | IN UINT8 OpFlag, |
| 398 | IN VOID *Value, |
| 399 | IN AMD_CONFIG_PARAMS *StdHeader |
| 400 | ) |
| 401 | { |
| 402 | UINT8 i; |
| 403 | |
| 404 | OpFlag = OpFlag & 0x7f; |
| 405 | OpFlag = 1 << (OpFlag - 1); |
| 406 | for (i = 0; i < OpFlag; i++) { |
| 407 | LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD6, &Address, StdHeader); |
| 408 | Address++; |
| 409 | LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGCD7, (UINT8 *)Value + i, StdHeader); |
| 410 | } |
| 411 | } |
| 412 | |
| 413 | /*----------------------------------------------------------------------------------------*/ |
| 414 | /** |
| 415 | * Write PMIO |
| 416 | * |
| 417 | * |
| 418 | * |
| 419 | * @param[in] Address - PMIO Offset value |
| 420 | * @param[in] OpFlag - Access sizes |
| 421 | * @param[in] Value - Write Data Buffer |
| 422 | * @param[in] StdHeader |
| 423 | * |
| 424 | */ |
| 425 | VOID |
| 426 | WritePmio ( |
| 427 | IN UINT8 Address, |
| 428 | IN UINT8 OpFlag, |
| 429 | IN VOID *Value, |
| 430 | IN AMD_CONFIG_PARAMS *StdHeader |
| 431 | ) |
| 432 | { |
| 433 | UINT8 i; |
| 434 | |
| 435 | OpFlag = OpFlag & 0x7f; |
| 436 | OpFlag = 1 << (OpFlag - 1); |
| 437 | for (i = 0; i < OpFlag; i++) { |
| 438 | LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD6, &Address, StdHeader); |
| 439 | Address++; |
| 440 | LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD7, (UINT8 *)Value + i, StdHeader); |
| 441 | } |
| 442 | } |
| 443 | |
| 444 | /*----------------------------------------------------------------------------------------*/ |
| 445 | /** |
| 446 | * RwPmio - Read/Write PMIO |
| 447 | * |
| 448 | * |
| 449 | * |
| 450 | * @param[in] Address - PMIO Offset value |
| 451 | * @param[in] OpFlag - Access sizes |
| 452 | * @param[in] AndMask - Data And Mask 32 bits |
| 453 | * @param[in] OrMask - Data OR Mask 32 bits |
| 454 | * @param[in] StdHeader |
| 455 | * |
| 456 | */ |
| 457 | VOID |
| 458 | RwPmio ( |
| 459 | IN UINT8 Address, |
| 460 | IN UINT8 OpFlag, |
| 461 | IN UINT32 AndMask, |
| 462 | IN UINT32 OrMask, |
| 463 | IN AMD_CONFIG_PARAMS *StdHeader |
| 464 | ) |
| 465 | { |
| 466 | UINT32 Result; |
| 467 | |
| 468 | ReadPmio (Address, OpFlag, &Result, StdHeader); |
| 469 | Result = (Result & AndMask) | OrMask; |
| 470 | WritePmio (Address, OpFlag, &Result, StdHeader); |
| 471 | } |
| 472 | |
| 473 | |
| 474 | /*----------------------------------------------------------------------------------------*/ |
| 475 | /** |
| 476 | * Read PMIO2 |
| 477 | * |
| 478 | * |
| 479 | * |
| 480 | * @param[in] Address - PMIO2 Offset value |
| 481 | * @param[in] OpFlag - Access sizes |
| 482 | * @param[in] Value - Read Data Buffer |
| 483 | * @param[in] StdHeader |
| 484 | * |
| 485 | */ |
| 486 | VOID |
| 487 | ReadPmio2 ( |
| 488 | IN UINT8 Address, |
| 489 | IN UINT8 OpFlag, |
| 490 | IN VOID *Value, |
| 491 | IN AMD_CONFIG_PARAMS *StdHeader |
| 492 | ) |
| 493 | { |
| 494 | UINT8 i; |
| 495 | |
| 496 | OpFlag = OpFlag & 0x7f; |
| 497 | OpFlag = 1 << (OpFlag - 1); |
| 498 | for ( i = 0; i < OpFlag; i++ ) { |
| 499 | LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD0, &Address, StdHeader); |
| 500 | Address++; |
| 501 | LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGCD1, (UINT8 *) Value + i, StdHeader); |
| 502 | } |
| 503 | } |
| 504 | |
| 505 | |
| 506 | /*----------------------------------------------------------------------------------------*/ |
| 507 | /** |
| 508 | * Write PMIO 2 |
| 509 | * |
| 510 | * |
| 511 | * |
| 512 | * @param[in] Address - PMIO2 Offset value |
| 513 | * @param[in] OpFlag - Access sizes |
| 514 | * @param[in] Value - Write Data Buffer |
| 515 | * @param[in] StdHeader |
| 516 | * |
| 517 | */ |
| 518 | VOID |
| 519 | WritePmio2 ( |
| 520 | IN UINT8 Address, |
| 521 | IN UINT8 OpFlag, |
| 522 | IN VOID *Value, |
| 523 | IN AMD_CONFIG_PARAMS *StdHeader |
| 524 | ) |
| 525 | { |
| 526 | UINT8 i; |
| 527 | |
| 528 | OpFlag = OpFlag & 0x7f; |
| 529 | OpFlag = 1 << (OpFlag - 1); |
| 530 | |
| 531 | for ( i = 0; i < OpFlag; i++ ) { |
| 532 | LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD0, &Address, StdHeader); |
| 533 | Address++; |
| 534 | LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD1, (UINT8 *) Value + i, StdHeader); |
| 535 | } |
| 536 | } |
| 537 | |
| 538 | /*----------------------------------------------------------------------------------------*/ |
| 539 | /** |
| 540 | * RwPmio2 - Read/Write PMIO2 |
| 541 | * |
| 542 | * |
| 543 | * |
| 544 | * @param[in] Address - PMIO2 Offset value |
| 545 | * @param[in] OpFlag - Access sizes |
| 546 | * @param[in] AndMask - Data And Mask 32 bits |
| 547 | * @param[in] OrMask - Data OR Mask 32 bits |
| 548 | * @param[in] StdHeader |
| 549 | * |
| 550 | */ |
| 551 | VOID |
| 552 | RwPmio2 ( |
| 553 | IN UINT8 Address, |
| 554 | IN UINT8 OpFlag, |
| 555 | IN UINT32 AndMask, |
| 556 | IN UINT32 OrMask, |
| 557 | IN AMD_CONFIG_PARAMS *StdHeader |
| 558 | ) |
| 559 | { |
| 560 | UINT32 Result; |
| 561 | |
| 562 | ReadPmio2 (Address, OpFlag, &Result, StdHeader); |
| 563 | Result = (Result & AndMask) | OrMask; |
| 564 | WritePmio2 (Address, OpFlag, &Result, StdHeader); |
| 565 | } |
| 566 | |
| 567 | |
| 568 | /*----------------------------------------------------------------------------------------*/ |
| 569 | /** |
| 570 | * Read BIOSRAM |
| 571 | * |
| 572 | * |
| 573 | * |
| 574 | * @param[in] Address - BIOSRAM Offset value |
| 575 | * @param[in] OpFlag - Access sizes |
| 576 | * @param[in] Value - Read Data Buffer |
| 577 | * @param[in] StdHeader |
| 578 | * |
| 579 | */ |
| 580 | VOID |
| 581 | ReadBiosram ( |
| 582 | IN UINT8 Address, |
| 583 | IN UINT8 OpFlag, |
| 584 | IN VOID *Value, |
| 585 | IN AMD_CONFIG_PARAMS *StdHeader |
| 586 | ) |
| 587 | { |
| 588 | UINT8 i; |
| 589 | |
| 590 | OpFlag = OpFlag & 0x7f; |
| 591 | OpFlag = 1 << (OpFlag - 1); |
| 592 | for (i = 0; i < OpFlag; i++) { |
| 593 | LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD4, &Address, StdHeader); |
| 594 | Address++; |
| 595 | LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGCD5, (UINT8 *)Value + i, StdHeader); |
| 596 | } |
| 597 | } |
| 598 | |
| 599 | /*----------------------------------------------------------------------------------------*/ |
| 600 | /** |
| 601 | * Write BIOSRAM |
| 602 | * |
| 603 | * |
| 604 | * |
| 605 | * @param[in] Address - BIOSRAM Offset value |
| 606 | * @param[in] OpFlag - Access sizes |
| 607 | * @param[in] Value - Write Data Buffer |
| 608 | * @param[in] StdHeader |
| 609 | * |
| 610 | */ |
| 611 | VOID |
| 612 | WriteBiosram ( |
| 613 | IN UINT8 Address, |
| 614 | IN UINT8 OpFlag, |
| 615 | IN VOID *Value, |
| 616 | IN AMD_CONFIG_PARAMS *StdHeader |
| 617 | ) |
| 618 | { |
| 619 | UINT8 i; |
| 620 | |
| 621 | OpFlag = OpFlag & 0x7f; |
| 622 | OpFlag = 1 << (OpFlag - 1); |
| 623 | for (i = 0; i < OpFlag; i++) { |
| 624 | LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD4, &Address, StdHeader); |
| 625 | Address++; |
| 626 | LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD5, (UINT8 *)Value + i, StdHeader); |
| 627 | } |
| 628 | } |
| 629 | |
| 630 | /*----------------------------------------------------------------------------------------*/ |
| 631 | /** |
| 632 | * Record SMI Status |
| 633 | * |
| 634 | * |
| 635 | * @param[in] StdHeader |
| 636 | * |
| 637 | */ |
| 638 | VOID |
| 639 | RecordSmiStatus ( |
| 640 | IN AMD_CONFIG_PARAMS *StdHeader |
| 641 | ) |
| 642 | { |
| 643 | UINTN Index; |
| 644 | UINT8 SwSmiValue; |
| 645 | |
| 646 | ACPIMMIO8 (0xfed80320) |= 0x01; |
| 647 | for ( Index = 0; Index < 20; Index++ ) { |
| 648 | ACPIMMIO8 (0xfed10020 + Index) = ACPIMMIO8 (0xfed80280 + Index); |
| 649 | } |
| 650 | LibAmdIoRead (AccessWidth8, 0xB0, &SwSmiValue, StdHeader); |
| 651 | ACPIMMIO8 (0xfed10040) = SwSmiValue; |
| 652 | } |
| 653 | |
| 654 | /*----------------------------------------------------------------------------------------*/ |
| 655 | /** |
| 656 | * Clear All SMI Status |
| 657 | * |
| 658 | * |
| 659 | * @param[in] StdHeader |
| 660 | * |
| 661 | */ |
| 662 | VOID |
| 663 | ClearAllSmiStatus ( |
| 664 | IN AMD_CONFIG_PARAMS *StdHeader |
| 665 | ) |
| 666 | { |
| 667 | UINTN Index; |
| 668 | |
| 669 | for ( Index = 0; Index < 20; Index++ ) { |
| 670 | ACPIMMIO8 (0xfed80280 + Index) |= 0; |
| 671 | } |
Marshall Dawson | f309388 | 2016-10-15 09:45:44 -0600 | [diff] [blame^] | 672 | } |