Marshall Dawson | f309388 | 2016-10-15 09:45:44 -0600 | [diff] [blame^] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * AMD CPU Services |
| 6 | * |
| 7 | * Related to the General Services API's, but for the CPU component. |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: CPU |
| 12 | * @e \$Revision$ @e \$Date$ |
| 13 | * |
| 14 | */ |
| 15 | /***************************************************************************** |
| 16 | * |
| 17 | * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc. |
| 18 | * All rights reserved. |
| 19 | * |
| 20 | * Redistribution and use in source and binary forms, with or without |
| 21 | * modification, are permitted provided that the following conditions are met: |
| 22 | * * Redistributions of source code must retain the above copyright |
| 23 | * notice, this list of conditions and the following disclaimer. |
| 24 | * * Redistributions in binary form must reproduce the above copyright |
| 25 | * notice, this list of conditions and the following disclaimer in the |
| 26 | * documentation and/or other materials provided with the distribution. |
| 27 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 28 | * its contributors may be used to endorse or promote products derived |
| 29 | * from this software without specific prior written permission. |
| 30 | * |
| 31 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 32 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 33 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 34 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 35 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 36 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 37 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 38 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 39 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 40 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 41 | * |
| 42 | ***************************************************************************/ |
| 43 | |
| 44 | #ifndef _CPU_SERVICES_H_ |
| 45 | #define _CPU_SERVICES_H_ |
| 46 | |
| 47 | #include "Topology.h" |
| 48 | |
| 49 | /*---------------------------------------------------------------------------------------- |
| 50 | * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) |
| 51 | *---------------------------------------------------------------------------------------- |
| 52 | */ |
| 53 | |
| 54 | /*---------------------------------------------------------------------------------------- |
| 55 | * D E F I N I T I O N S A N D M A C R O S |
| 56 | *---------------------------------------------------------------------------------------- |
| 57 | */ |
| 58 | /// WARM RESET STATE_BITS |
| 59 | #define WR_STATE_COLD 00 |
| 60 | #define WR_STATE_RESET 01 |
| 61 | #define WR_STATE_EARLY 02 |
| 62 | #define WR_STATE_POST 03 |
| 63 | |
| 64 | /*---------------------------------------------------------------------------------------- |
| 65 | * T Y P E D E F S, S T R U C T U R E S, E N U M S |
| 66 | *---------------------------------------------------------------------------------------- |
| 67 | */ |
| 68 | |
| 69 | /** |
| 70 | * The role of primary core for each compute unit can be relative to the cores' launch order. |
| 71 | * |
| 72 | * One core of a compute unit is always given the role as primary. In different feature algorithms |
| 73 | * the core performing the primary core role can be designated relative to compute order. In most cases, |
| 74 | * the primary core is the first core of a compute unit to execute. However, in some cases the primary core |
| 75 | * role is associated with the last core to execute. |
| 76 | * |
| 77 | * If the launch order is strictly ascending, then first core is the lowest number and last core is highest. |
| 78 | * But if the launch order is not ascending, the first and last core follow the launch order, not the numbering order. |
| 79 | * |
| 80 | * Note that for compute units with only one core (AllCoresMapping), that core is primary for both orderings. |
| 81 | * (This includes processors without hardware compute units.) |
| 82 | * |
| 83 | */ |
| 84 | typedef enum { |
| 85 | FirstCoreIsComputeUnitPrimary, ///< the primary core role associates with the first core. |
| 86 | LastCoreIsComputeUnitPrimary, ///< the primary core role associates with the last core. |
| 87 | MaxComputeUnitPrimarySelector, ///< limit check. |
| 88 | } COMPUTE_UNIT_PRIMARY_SELECTOR; |
| 89 | |
| 90 | /** |
| 91 | * The supported Core to Compute unit mappings. |
| 92 | */ |
| 93 | typedef enum { |
| 94 | AllCoresMapping, ///< All Cores are primary cores |
| 95 | EvenCoresMapping, ///< Compute units are even/odd core pairs. |
| 96 | TripleCoresMapping, ///< Compute units has three cores enabled. |
| 97 | QuadCoresMapping, ///< Compute units has four cores enabled. |
| 98 | BitMapMapping, ///< Currently not supported by any family, arbitrary core |
| 99 | ///< to compute unit mapping. |
| 100 | MaxComputeUnitMapping ///< Not a mapping, use for limit check. |
| 101 | } COMPUTE_UNIT_MAPPING; |
| 102 | |
| 103 | /** |
| 104 | * Compute unit status register. |
| 105 | */ |
| 106 | |
| 107 | /** |
| 108 | * Compute Unit Map entry. |
| 109 | * Provide for interpreting the core pairing for the processor's compute units. |
| 110 | * |
| 111 | * HT_LIST_TERMINAL as an Enabled value means the end of a list of map structs. |
| 112 | * Zero as an Enabled value implies Compute Units are not supported by the processor |
| 113 | * and the mapping is assumed to be AllCoresMapping. |
| 114 | * |
| 115 | */ |
| 116 | typedef struct { |
| 117 | UINT8 Enabled; ///< The value of the Enabled Compute Units |
| 118 | UINT8 DualCore; ///< The value of the Dual Core Compute Units |
| 119 | UINT8 TripleCore; ///< the value of the Triple Core Compute Units |
| 120 | UINT8 QuadCore; ///< the value of the Quad Core Compute Units |
| 121 | COMPUTE_UNIT_MAPPING Mapping; ///< When the processor module matches these values, use this mapping method. |
| 122 | } COMPUTE_UNIT_MAP; |
| 123 | |
| 124 | //---------------------------------------------------------------------------- |
| 125 | // CPU SYSTEM INFO TYPEDEFS, STRUCTURES, ENUMS |
| 126 | // |
| 127 | //---------------------------------------------------------------------------- |
| 128 | /// SYSTEM INFO |
| 129 | typedef struct _SYSTEM_INFO { |
| 130 | UINT32 TotalNumberOfSockets; ///< Total Number of Sockets |
| 131 | UINT32 TotalNumberOfCores; ///< Total Number Of Cores |
| 132 | UINT32 CurrentSocketNum; ///< Current Socket Number |
| 133 | UINT32 CurrentCoreNum; ///< Current Core Number |
| 134 | UINT32 CurrentCoreApicId; ///< Current Core Apic ID |
| 135 | UINT32 CurrentLogicalCpuId; ///< Current Logical CPU ID |
| 136 | } SYSTEM_INFO; |
| 137 | |
| 138 | /// WARM_RESET_REQUEST |
| 139 | typedef struct _WARM_RESET_REQUEST { |
| 140 | UINT8 RequestBit:1; ///< Request Bit |
| 141 | UINT8 StateBits:2; ///< State Bits |
| 142 | UINT8 PostStage:2; ///< Post Stage |
| 143 | UINT8 Reserved:(8 - 5); ///< Reserved |
| 144 | } WARM_RESET_REQUEST; |
| 145 | /*---------------------------------------------------------------------------------------- |
| 146 | * F U N C T I O N P R O T O T Y P E |
| 147 | *---------------------------------------------------------------------------------------- |
| 148 | */ |
| 149 | |
| 150 | /** |
| 151 | * Get the current Platform's number of Sockets, regardless of how many are populated. |
| 152 | * |
| 153 | */ |
| 154 | UINT32 |
| 155 | GetPlatformNumberOfSockets ( VOID ); |
| 156 | |
| 157 | /** |
| 158 | * Get the number of Modules to check presence in each Processor. |
| 159 | * |
| 160 | */ |
| 161 | UINT32 |
| 162 | GetPlatformNumberOfModules ( VOID ); |
| 163 | |
| 164 | BOOLEAN |
| 165 | IsProcessorPresent ( |
| 166 | IN UINT32 Socket, |
| 167 | IN AMD_CONFIG_PARAMS *StdHeader |
| 168 | ); |
| 169 | |
| 170 | /** |
| 171 | * For a specific Node, get its Socket and Module ids. |
| 172 | * |
| 173 | */ |
| 174 | BOOLEAN |
| 175 | GetSocketModuleOfNode ( |
| 176 | IN UINT32 Node, |
| 177 | OUT UINT32 *Socket, |
| 178 | OUT UINT32 *Module, |
| 179 | IN AMD_CONFIG_PARAMS *StdHeader |
| 180 | ); |
| 181 | |
| 182 | /** |
| 183 | * Get the current core's Processor APIC Index. |
| 184 | */ |
| 185 | UINT32 |
| 186 | GetProcessorApicIndex ( |
| 187 | IN UINT32 Node, |
| 188 | IN AMD_CONFIG_PARAMS *StdHeader |
| 189 | ); |
| 190 | |
| 191 | /** |
| 192 | * Provide the number of installed processors (not Nodes! and not Sockets!) |
| 193 | */ |
| 194 | UINT32 |
| 195 | GetNumberOfProcessors ( |
| 196 | IN AMD_CONFIG_PARAMS *StdHeader |
| 197 | ); |
| 198 | |
| 199 | VOID |
| 200 | GetActiveCoresInCurrentSocket ( |
| 201 | OUT UINT32 *CoreCount, |
| 202 | IN AMD_CONFIG_PARAMS *StdHeader |
| 203 | ); |
| 204 | |
| 205 | UINTN |
| 206 | GetActiveCoresInCurrentModule ( |
| 207 | IN AMD_CONFIG_PARAMS *StdHeader |
| 208 | ); |
| 209 | |
| 210 | UINTN |
| 211 | GetNumberOfCompUnitsInCurrentModule ( |
| 212 | IN AMD_CONFIG_PARAMS *StdHeader |
| 213 | ); |
| 214 | |
| 215 | BOOLEAN |
| 216 | GetGivenModuleCoreRange ( |
| 217 | IN UINT32 Socket, |
| 218 | IN UINT32 Module, |
| 219 | OUT UINT32 *LowCore, |
| 220 | OUT UINT32 *HighCore, |
| 221 | IN AMD_CONFIG_PARAMS *StdHeader |
| 222 | ); |
| 223 | |
| 224 | VOID |
| 225 | GetCurrentCore ( |
| 226 | OUT UINT32 *Core, |
| 227 | IN AMD_CONFIG_PARAMS *StdHeader |
| 228 | ); |
| 229 | |
| 230 | VOID |
| 231 | GetCurrentNodeAndCore ( |
| 232 | OUT UINT32 *Node, |
| 233 | OUT UINT32 *Core, |
| 234 | IN AMD_CONFIG_PARAMS *StdHeader |
| 235 | ); |
| 236 | |
| 237 | BOOLEAN |
| 238 | IsCurrentCorePrimary ( |
| 239 | IN AMD_CONFIG_PARAMS *StdHeader |
| 240 | ); |
| 241 | |
| 242 | |
| 243 | BOOLEAN |
| 244 | GetNodeId ( |
| 245 | IN UINT32 SocketId, |
| 246 | IN UINT32 ModuleId, |
| 247 | OUT UINT8 *NodeId, |
| 248 | IN AMD_CONFIG_PARAMS *StdHeader |
| 249 | ); |
| 250 | |
| 251 | VOID |
| 252 | WaitMicroseconds ( |
| 253 | IN UINT32 Microseconds, |
| 254 | IN AMD_CONFIG_PARAMS *StdHeader |
| 255 | ); |
| 256 | |
| 257 | /** |
| 258 | * Get the compute unit mapping algorithm. |
| 259 | */ |
| 260 | COMPUTE_UNIT_MAPPING |
| 261 | GetComputeUnitMapping ( |
| 262 | IN AMD_CONFIG_PARAMS *StdHeader |
| 263 | ); |
| 264 | |
| 265 | /** |
| 266 | * Does the current core have the role of primary core for the compute unit? |
| 267 | */ |
| 268 | BOOLEAN |
| 269 | IsCoreComputeUnitPrimary ( |
| 270 | IN COMPUTE_UNIT_PRIMARY_SELECTOR Selector, |
| 271 | IN AMD_CONFIG_PARAMS *StdHeader |
| 272 | ); |
| 273 | |
| 274 | VOID |
| 275 | SetWarmResetFlag ( |
| 276 | IN AMD_CONFIG_PARAMS *StdHeader, |
| 277 | IN WARM_RESET_REQUEST *Request |
| 278 | ); |
| 279 | |
| 280 | VOID |
| 281 | GetWarmResetFlag ( |
| 282 | IN AMD_CONFIG_PARAMS *StdHeader, |
| 283 | OUT WARM_RESET_REQUEST *Request |
| 284 | ); |
| 285 | |
| 286 | BOOLEAN |
| 287 | IsWarmReset ( |
| 288 | IN AMD_CONFIG_PARAMS *StdHeader |
| 289 | ); |
| 290 | |
| 291 | AGESA_STATUS |
| 292 | CheckBistStatus ( |
| 293 | IN AMD_CONFIG_PARAMS *StdHeader |
| 294 | ); |
| 295 | |
| 296 | VOID |
| 297 | SetWarmResetAtEarly ( |
| 298 | IN UINT32 Data, |
| 299 | IN AMD_CONFIG_PARAMS *StdHeader |
| 300 | ); |
| 301 | |
| 302 | #ifndef CPU_DEADLOOP |
| 303 | #define CPU_DEADLOOP() { volatile UINTN __i; __i = 1; while (__i); } |
| 304 | #endif |
| 305 | |
| 306 | #endif // _CPU_SERVICES_H_ |