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review.coreboot.org / coreboot / f3093883f7336054f344072c5b086998dc5f72c2 / . / src / vendorcode / amd / pi / 00670F00 / AMD.h
blob: 003ac0e19a122af509c8031bb769e58b22aa7d20 [file] [log] [blame]
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]1/* $NoKeywords:$ */
2/**
3 * @file
4 *
5 * Agesa structures and definitions
6 *
7 * Contains AMD AGESA core interface
8 *
9 * @xrefitem bom "File Content Label" "Release Content"
10 * @e project: AGESA
11 * @e sub-project: Include
Marshall Dawsona0400652016-10-15 09:20:43 -0600[diff] [blame]12 * @e \$Revision$ @e \$Date$
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]13 */
14 /*****************************************************************************
15 *
Marshall Dawsona0400652016-10-15 09:20:43 -0600[diff] [blame]16 * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are met:
21 * * Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer.
23 * * Redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution.
26 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
27 * its contributors may be used to endorse or promote products derived
28 * from this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
32 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
34 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
35 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
36 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
37 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
39 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 ***************************************************************************/
42
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]43#ifndef _AMD_H_
44#define _AMD_H_
45
Marshall Dawsonf3093882016-10-15 09:45:44 -0600[diff] [blame^]46#define Int16FromChar(a,b) (UINT16)((a) << 0 | (b) << 8)
47#define Int32FromChar(a,b,c,d) (UINT32)((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24)
48#define Int64FromChar(a,b,c,d,e,f,g,h) ((UINT64)(Int32FromChar(a,b,c,d)<<32) | (UINT64)Int32FromChar(e,f,g,h))
49
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]50#define AGESA_REVISION "Arch2008"
Marshall Dawsonf3093882016-10-15 09:45:44 -0600[diff] [blame^]51#define AGESA_ID {'A', 'G', 'E', 'S', 'A', 0x00, 0x00, 0x00}
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]52
53//
54//
55// AGESA Types and Definitions
56//
57//
58#define LAST_ENTRY 0xFFFFFFFFul
Marshall Dawsonf3093882016-10-15 09:45:44 -0600[diff] [blame^]59#define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D')
60#define MODULE_SIGNATURE Int32FromChar ('$', 'M', 'O', 'D')
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]61#define IOCF8 0xCF8
62#define IOCFC 0xCFC
63
64/// The return status for all AGESA public services.
65///
66/// Services return the most severe status of any logged event. Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
67/// will have log entries with more detail.
68///
69typedef enum {
70 AGESA_SUCCESS = 0, ///< The service completed normally. Info may be logged.
71 AGESA_UNSUPPORTED, ///< The dispatcher or create struct had an unimplemented function requested.
72 ///< Not logged.
73 AGESA_BOUNDS_CHK, ///< A dynamic parameter was out of range and the service was not provided.
74 ///< Example, memory address not installed, heap buffer handle not found.
75 ///< Not Logged.
76 // AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
77 AGESA_ALERT, ///< An observed condition, but no loss of function. See Log.
78 AGESA_WARNING, ///< Possible or minor loss of function. See Log.
79 AGESA_ERROR, ///< Significant loss of function, boot may be possible. See Log.
80 AGESA_CRITICAL, ///< Continue boot only to notify user. See Log.
81 AGESA_FATAL, ///< Halt booting. See Log, however Fatal errors pertaining to heap problems
82 ///< may not be able to reliably produce log events.
83 AgesaStatusMax ///< Not a status, for limit checking.
84} AGESA_STATUS;
85
86/// For checking whether a status is at or above the mandatory log level.
87#define AGESA_STATUS_LOG_LEVEL AGESA_ALERT
88
89/**
90 * Callout method to the host environment.
91 *
92 * Callout using a dispatch with appropriate thunk layer, which is determined by the host environment.
93 *
94 * @param[in] Function The specific callout function being invoked.
95 * @param[in] FcnData Function specific data item.
96 * @param[in,out] ConfigPtr Reference to Callout params.
97 */
98typedef AGESA_STATUS (*CALLOUT_ENTRY) (
99 IN UINT32 Function,
100 IN UINTN FcnData,
101 IN OUT VOID *ConfigPtr
102 );
103
104typedef AGESA_STATUS (*IMAGE_ENTRY) (VOID *ConfigPtr);
105typedef AGESA_STATUS (*MODULE_ENTRY) (VOID *ConfigPtr);
106
107///This allocation type is used by the AmdCreateStruct entry point
108typedef enum {
109 PreMemHeap = 0, ///< Create heap in cache.
110 PostMemDram, ///< Create heap in memory.
111 ByHost ///< Create heap by Host.
112} ALLOCATION_METHOD;
113
114/// These width descriptors are used by the library function, and others, to specify the data size
115typedef enum ACCESS_WIDTH {
116 AccessWidthNone = 0, ///< dummy access width
117 AccessWidth8 = 1, ///< Access width is 8 bits.
118 AccessWidth16, ///< Access width is 16 bits.
119 AccessWidth32, ///< Access width is 32 bits.
120 AccessWidth64, ///< Access width is 64 bits.
121
122 AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data.
123 AccessS3SaveWidth16, ///< Save 16 bits data.
124 AccessS3SaveWidth32, ///< Save 32 bits data.
125 AccessS3SaveWidth64, ///< Save 64 bits data.
126} ACCESS_WIDTH;
127
128/// AGESA struct name
129typedef enum {
130 // AGESA BASIC FUNCTIONS
Marshall Dawsonf3093882016-10-15 09:45:44 -0600[diff] [blame^]131 AMD_INIT_RECOVERY = 0x00021000, ///< AmdInitRecovery entry point handle
132 AMD_CREATE_STRUCT = 0x00022000, ///< AmdCreateStruct handle
133 AMD_INIT_EARLY = 0x00023000, ///< AmdInitEarly entry point handle
134 AMD_INIT_ENV = 0x00024000, ///< AmdInitEnv entry point handle
135 AMD_INIT_LATE = 0x00025000, ///< AmdInitLate entry point handle
136 AMD_INIT_MID = 0x00026000, ///< AmdInitMid entry point handle
137 AMD_INIT_POST = 0x00027000, ///< AmdInitPost entry point handle
138 AMD_INIT_RESET = 0x00028000, ///< AmdInitReset entry point handle
139 AMD_INIT_RESUME = 0x00029000, ///< AmdInitResume entry point handle
140 AMD_RELEASE_STRUCT = 0x0002A000, ///< AmdReleaseStruct handle
141 AMD_S3LATE_RESTORE = 0x0002B000, ///< AmdS3LateRestore entry point handle
142 AMD_GET_APIC_ID = 0x0002C000, ///< AmdGetApicId entry point handle
143 AMD_GET_PCI_ADDRESS = 0x0002D000, ///< AmdGetPciAddress entry point handle
144 AMD_IDENTIFY_CORE = 0x0002E000, ///< AmdIdentifyCore general service handle
145 AMD_READ_EVENT_LOG = 0x0002F000, ///< AmdReadEventLog general service handle
146 AMD_GET_EXECACHE_SIZE = 0x00030000, ///< AmdGetAvailableExeCacheSize general service handle
147 AMD_LATE_RUN_AP_TASK = 0x00031000, ///< AmdLateRunApTask entry point handle
148 AMD_IDENTIFY_DIMMS = 0x00032000, ///< AmdIdentifyDimm general service handle
149 AMD_GET_2D_DATA_EYE = 0x00033000, ///< AmdGet2DDataEye general service handle
150 AMD_S3FINAL_RESTORE = 0x00034000, ///< AmdS3FinalRestore entry point handle
151 AMD_INIT_RTB = 0x00035000, ///< AmdInitRtb entry point handle
152 AMD_HEAP_ALLOCATE_BUFFER = 0x00038000,
153 AMD_HEAP_DEALLOCATE_BUFFER = 0x00039000,
154 FCH_INIT_RESET = 0x00040000,
155 FCH_INIT_ENV = 0x00041000,
156 FCH_INIT_MID = 0x00042000,
157 FCH_INIT_LATE = 0x00043000,
158 FCH_INIT_S3_EARLY_RESTORE = 0x00044000,
159 FCH_INIT_S3_LATE_RESTORE = 0x00045000,
160 AMD_SET_VALUE = 0x00081000,
161 AMD_GET_VALUE = 0x00082000
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]162} AGESA_STRUCT_NAME;
163
164 /* ResetType constant values */
165#define WARM_RESET_WHENEVER 1
166#define COLD_RESET_WHENEVER 2
167#define WARM_RESET_IMMEDIATELY 3
168#define COLD_RESET_IMMEDIATELY 4
169
170
171// AGESA Structures
172
173/// The standard header for all AGESA services.
174/// For internal AGESA naming conventions, see @ref amdconfigparamname .
175typedef struct {
Marshall Dawsonf3093882016-10-15 09:45:44 -0600[diff] [blame^]176 IN VOID * ImageBasePtr; ///< The AGESA Image base address.
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]177 IN UINT32 Func; ///< The service desired
Marshall Dawsonf3093882016-10-15 09:45:44 -0600[diff] [blame^]178 IN VOID * AltImageBasePtr; ///< Alternate Image location
Marc Jones9ef6e522016-09-20 20:16:20 -0600[diff] [blame]179 IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA
180 IN UINT8 HeapStatus; ///< For heap status from boot time slide.
181 IN UINT64 HeapBasePtr; ///< Location of the heap
182 IN OUT UINT8 Reserved[7]; ///< This space is reserved for future use.
183} AMD_CONFIG_PARAMS;
184
185
186/// Create Struct Interface.
187typedef struct {
188 IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
189 IN AGESA_STRUCT_NAME AgesaFunctionName; ///< The service to init
190 IN ALLOCATION_METHOD AllocationMethod; ///< How to handle buffer allocation
191 IN OUT UINT32 NewStructSize; ///< The size of the allocated data, in for ByHost, else out only.
192 IN OUT VOID *NewStructPtr; ///< The struct for the service.
193 ///< The struct to init for ByHost allocation,
194 ///< the initialized struct on return.
195} AMD_INTERFACE_PARAMS;
196
197#define FUNC_0 0 // bit-placed for PCI address creation
198#define FUNC_1 1
199#define FUNC_2 2
200#define FUNC_3 3
201#define FUNC_4 4
202#define FUNC_5 5
203#define FUNC_6 6
204#define FUNC_7 7
205
206/// AGESA Binary module header structure
207typedef struct {
208 IN UINT32 Signature; ///< Binary Signature
209 IN CHAR8 CreatorID[8]; ///< 8 characters ID
210 IN CHAR8 Version[12]; ///< 12 characters version
211 IN UINT32 ModuleInfoOffset; ///< Offset of module
212 IN UINT32 EntryPointAddress; ///< Entry address
213 IN UINT32 ImageBase; ///< Image base
214 IN UINT32 RelocTableOffset; ///< Relocate Table offset
215 IN UINT32 ImageSize; ///< Size
216 IN UINT16 Checksum; ///< Checksum
217 IN UINT8 ImageType; ///< Type
218 IN UINT8 V_Reserved; ///< Reserved
219} AMD_IMAGE_HEADER;
220/// AGESA Binary module header structure
221typedef struct _AMD_MODULE_HEADER {
222 IN UINT32 ModuleHeaderSignature; ///< Module signature
223 IN CHAR8 ModuleIdentifier[8]; ///< 8 characters ID
224 IN CHAR8 ModuleVersion[12]; ///< 12 characters version
225 IN VOID *ModuleDispatcher; ///< A pointer point to dispatcher
226 IN struct _AMD_MODULE_HEADER *NextBlock; ///< Next module header link
227} AMD_MODULE_HEADER;
228
229// AMD_CODE_HEADER Signatures.
230#define AGESA_CODE_SIGNATURE {'!', '!', '!', 'A', 'G', 'E', 'S', 'A'}
231#define CIMXNB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'}
232#define CIMXSB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'}
233
234/// AGESA_CODE_SIGNATURE
235typedef struct {
236 IN CHAR8 Signature[8]; ///< code header Signature
237 IN CHAR8 ComponentName[16]; ///< 16 character name of the code module
238 IN CHAR8 Version[12]; ///< 12 character version string
239 IN CHAR8 TerminatorNull; ///< null terminated string
240 IN CHAR8 VerReserved[7]; ///< reserved space
241} AMD_CODE_HEADER;
242
243/// Extended PCI address format
244typedef struct {
245 IN OUT UINT32 Register:12; ///< Register offset
246 IN OUT UINT32 Function:3; ///< Function number
247 IN OUT UINT32 Device:5; ///< Device number
248 IN OUT UINT32 Bus:8; ///< Bus number
249 IN OUT UINT32 Segment:4; ///< Segment
250} EXT_PCI_ADDR;
251
252/// Union type for PCI address
253typedef union _PCI_ADDR {
254 IN UINT32 AddressValue; ///< Formal address
255 IN EXT_PCI_ADDR Address; ///< Extended address
256} PCI_ADDR;
257
258// SBDFO - Segment Bus Device Function Offset
259// 31:28 Segment (4-bits)
260// 27:20 Bus (8-bits)
261// 19:15 Device (5-bits)
262// 14:12 Function(3-bits)
263// 11:00 Offset (12-bits)
264
265#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \
266 (((UINT32)(Dev)) << 15) | (((UINT32)(Fun)) << 12) | ((UINT32)(Off)))
267#define ILLEGAL_SBDFO 0xFFFFFFFFul
268
269/// CPUID data received registers format
270typedef struct {
271 OUT UINT32 EAX_Reg; ///< CPUID instruction result in EAX
272 OUT UINT32 EBX_Reg; ///< CPUID instruction result in EBX
273 OUT UINT32 ECX_Reg; ///< CPUID instruction result in ECX
274 OUT UINT32 EDX_Reg; ///< CPUID instruction result in EDX
275} CPUID_DATA;
276
277// Topology Services definitions and macros
278#define TOPOLOGY_LIST_TERMINAL 0xFF ///< End of list.
279
280
281#ifndef BIT0
282 #define BIT0 0x0000000000000001ull
283#endif
284#ifndef BIT1
285 #define BIT1 0x0000000000000002ull
286#endif
287#ifndef BIT2
288 #define BIT2 0x0000000000000004ull
289#endif
290#ifndef BIT3
291 #define BIT3 0x0000000000000008ull
292#endif
293#ifndef BIT4
294 #define BIT4 0x0000000000000010ull
295#endif
296#ifndef BIT5
297 #define BIT5 0x0000000000000020ull
298#endif
299#ifndef BIT6
300 #define BIT6 0x0000000000000040ull
301#endif
302#ifndef BIT7
303 #define BIT7 0x0000000000000080ull
304#endif
305#ifndef BIT8
306 #define BIT8 0x0000000000000100ull
307#endif
308#ifndef BIT9
309 #define BIT9 0x0000000000000200ull
310#endif
311#ifndef BIT10
312 #define BIT10 0x0000000000000400ull
313#endif
314#ifndef BIT11
315 #define BIT11 0x0000000000000800ull
316#endif
317#ifndef BIT12
318 #define BIT12 0x0000000000001000ull
319#endif
320#ifndef BIT13
321 #define BIT13 0x0000000000002000ull
322#endif
323#ifndef BIT14
324 #define BIT14 0x0000000000004000ull
325#endif
326#ifndef BIT15
327 #define BIT15 0x0000000000008000ull
328#endif
329#ifndef BIT16
330 #define BIT16 0x0000000000010000ull
331#endif
332#ifndef BIT17
333 #define BIT17 0x0000000000020000ull
334#endif
335#ifndef BIT18
336 #define BIT18 0x0000000000040000ull
337#endif
338#ifndef BIT19
339 #define BIT19 0x0000000000080000ull
340#endif
341#ifndef BIT20
342 #define BIT20 0x0000000000100000ull
343#endif
344#ifndef BIT21
345 #define BIT21 0x0000000000200000ull
346#endif
347#ifndef BIT22
348 #define BIT22 0x0000000000400000ull
349#endif
350#ifndef BIT23
351 #define BIT23 0x0000000000800000ull
352#endif
353#ifndef BIT24
354 #define BIT24 0x0000000001000000ull
355#endif
356#ifndef BIT25
357 #define BIT25 0x0000000002000000ull
358#endif
359#ifndef BIT26
360 #define BIT26 0x0000000004000000ull
361#endif
362#ifndef BIT27
363 #define BIT27 0x0000000008000000ull
364#endif
365#ifndef BIT28
366 #define BIT28 0x0000000010000000ull
367#endif
368#ifndef BIT29
369 #define BIT29 0x0000000020000000ull
370#endif
371#ifndef BIT30
372 #define BIT30 0x0000000040000000ull
373#endif
374#ifndef BIT31
375 #define BIT31 0x0000000080000000ull
376#endif
377#ifndef BIT32
378 #define BIT32 0x0000000100000000ull
379#endif
380#ifndef BIT33
381 #define BIT33 0x0000000200000000ull
382#endif
383#ifndef BIT34
384 #define BIT34 0x0000000400000000ull
385#endif
386#ifndef BIT35
387 #define BIT35 0x0000000800000000ull
388#endif
389#ifndef BIT36
390 #define BIT36 0x0000001000000000ull
391#endif
392#ifndef BIT37
393 #define BIT37 0x0000002000000000ull
394#endif
395#ifndef BIT38
396 #define BIT38 0x0000004000000000ull
397#endif
398#ifndef BIT39
399 #define BIT39 0x0000008000000000ull
400#endif
401#ifndef BIT40
402 #define BIT40 0x0000010000000000ull
403#endif
404#ifndef BIT41
405 #define BIT41 0x0000020000000000ull
406#endif
407#ifndef BIT42
408 #define BIT42 0x0000040000000000ull
409#endif
410#ifndef BIT43
411 #define BIT43 0x0000080000000000ull
412#endif
413#ifndef BIT44
414 #define BIT44 0x0000100000000000ull
415#endif
416#ifndef BIT45
417 #define BIT45 0x0000200000000000ull
418#endif
419#ifndef BIT46
420 #define BIT46 0x0000400000000000ull
421#endif
422#ifndef BIT47
423 #define BIT47 0x0000800000000000ull
424#endif
425#ifndef BIT48
426 #define BIT48 0x0001000000000000ull
427#endif
428#ifndef BIT49
429 #define BIT49 0x0002000000000000ull
430#endif
431#ifndef BIT50
432 #define BIT50 0x0004000000000000ull
433#endif
434#ifndef BIT51
435 #define BIT51 0x0008000000000000ull
436#endif
437#ifndef BIT52
438 #define BIT52 0x0010000000000000ull
439#endif
440#ifndef BIT53
441 #define BIT53 0x0020000000000000ull
442#endif
443#ifndef BIT54
444 #define BIT54 0x0040000000000000ull
445#endif
446#ifndef BIT55
447 #define BIT55 0x0080000000000000ull
448#endif
449#ifndef BIT56
450 #define BIT56 0x0100000000000000ull
451#endif
452#ifndef BIT57
453 #define BIT57 0x0200000000000000ull
454#endif
455#ifndef BIT58
456 #define BIT58 0x0400000000000000ull
457#endif
458#ifndef BIT59
459 #define BIT59 0x0800000000000000ull
460#endif
461#ifndef BIT60
462 #define BIT60 0x1000000000000000ull
463#endif
464#ifndef BIT61
465 #define BIT61 0x2000000000000000ull
466#endif
467#ifndef BIT62
468 #define BIT62 0x4000000000000000ull
469#endif
470#ifndef BIT63
471 #define BIT63 0x8000000000000000ull
472#endif
473
474#endif // _AMD_H_