Edward O'Callaghan | a81be27d | 2020-05-29 14:13:08 +1000 | [diff] [blame] | 1 | chip soc/intel/cannonlake |
| 2 | # Enable heci communication |
| 3 | register "HeciEnabled" = "1" |
| 4 | |
| 5 | # Auto-switch between X4 NVMe and X2 NVMe. |
| 6 | register "TetonGlacierMode" = "1" |
| 7 | |
| 8 | register "SerialIoDevMode" = "{ |
| 9 | [PchSerialIoIndexI2C0] = PchSerialIoDisabled, |
| 10 | [PchSerialIoIndexI2C1] = PchSerialIoDisabled, |
| 11 | [PchSerialIoIndexI2C2] = PchSerialIoPci, |
| 12 | [PchSerialIoIndexI2C3] = PchSerialIoPci, |
| 13 | [PchSerialIoIndexI2C4] = PchSerialIoPci, |
| 14 | [PchSerialIoIndexI2C5] = PchSerialIoPci, |
| 15 | [PchSerialIoIndexSPI0] = PchSerialIoPci, |
| 16 | [PchSerialIoIndexSPI1] = PchSerialIoPci, |
| 17 | [PchSerialIoIndexSPI2] = PchSerialIoDisabled, |
| 18 | [PchSerialIoIndexUART0] = PchSerialIoSkipInit, |
| 19 | [PchSerialIoIndexUART1] = PchSerialIoDisabled, |
| 20 | [PchSerialIoIndexUART2] = PchSerialIoDisabled, |
| 21 | }" |
| 22 | |
| 23 | # USB configuration |
| 24 | # NOTE: This only applies to Puff, |
| 25 | # usb2_ports[1] and usb2_ports[3] were swapped on |
| 26 | # reference schematics after Puff has been built. |
| 27 | register "usb2_ports[0]" = "{ |
| 28 | .enable = 1, |
| 29 | .ocpin = OC2, |
| 30 | .tx_bias = USB2_BIAS_0MV, |
| 31 | .tx_emp_enable = USB2_PRE_EMP_ON, |
| 32 | .pre_emp_bias = USB2_BIAS_11P25MV, |
| 33 | .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, |
| 34 | }" # Type-A Port 2 |
| 35 | register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port |
| 36 | register "usb2_ports[2]" = "{ |
| 37 | .enable = 1, |
| 38 | .ocpin = OC3, |
| 39 | .tx_bias = USB2_BIAS_0MV, |
| 40 | .tx_emp_enable = USB2_PRE_EMP_ON, |
| 41 | .pre_emp_bias = USB2_BIAS_28P15MV, |
| 42 | .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, |
| 43 | }" # Type-A Port 3 |
| 44 | register "usb2_ports[3]" = "{ |
| 45 | .enable = 1, |
| 46 | .ocpin = OC1, |
| 47 | .tx_bias = USB2_BIAS_0MV, |
| 48 | .tx_emp_enable = USB2_PRE_EMP_ON, |
| 49 | .pre_emp_bias = USB2_BIAS_28P15MV, |
| 50 | .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, |
| 51 | }" # Type-A Port 1 |
Edward O'Callaghan | f2ccd07 | 2020-06-11 11:29:21 +1000 | [diff] [blame^] | 52 | register "usb2_ports[4]" = "USB2_PORT_EMPTY" |
Edward O'Callaghan | a81be27d | 2020-05-29 14:13:08 +1000 | [diff] [blame] | 53 | register "usb2_ports[5]" = "{ |
| 54 | .enable = 1, |
| 55 | .ocpin = OC0, |
| 56 | .tx_bias = USB2_BIAS_0MV, |
| 57 | .tx_emp_enable = USB2_PRE_EMP_ON, |
| 58 | .pre_emp_bias = USB2_BIAS_28P15MV, |
| 59 | .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, |
| 60 | }" # Type-A port 0 |
| 61 | register "usb2_ports[6]" = "USB2_PORT_EMPTY" |
| 62 | register "usb2_ports[7]" = "USB2_PORT_EMPTY" |
| 63 | register "usb2_ports[8]" = "USB2_PORT_EMPTY" |
| 64 | register "usb2_ports[9]" = "{ |
| 65 | .enable = 1, |
| 66 | .ocpin = OC_SKIP, |
| 67 | .tx_bias = USB2_BIAS_0MV, |
| 68 | .tx_emp_enable = USB2_PRE_EMP_ON, |
| 69 | .pre_emp_bias = USB2_BIAS_28P15MV, |
| 70 | .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, |
| 71 | }" # BT |
| 72 | |
| 73 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port 2 |
| 74 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 3 |
| 75 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1 |
| 76 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C |
| 77 | register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0 |
Edward O'Callaghan | f2ccd07 | 2020-06-11 11:29:21 +1000 | [diff] [blame^] | 78 | register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Type-A Port 4 |
Edward O'Callaghan | a81be27d | 2020-05-29 14:13:08 +1000 | [diff] [blame] | 79 | |
| 80 | # Enable eMMC HS400 |
| 81 | register "ScsEmmcHs400Enabled" = "1" |
| 82 | |
| 83 | # EMMC Tx CMD Delay |
| 84 | # Refer to EDS-Vol2-14.3.7. |
| 85 | # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. |
| 86 | # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. |
| 87 | register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" |
| 88 | |
| 89 | # EMMC TX DATA Delay 1 |
| 90 | # Refer to EDS-Vol2-14.3.8. |
| 91 | # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. |
| 92 | # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. |
| 93 | register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911" |
| 94 | |
| 95 | # EMMC TX DATA Delay 2 |
| 96 | # Refer to EDS-Vol2-14.3.9. |
| 97 | # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. |
| 98 | # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. |
| 99 | # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. |
| 100 | # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. |
| 101 | register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828" |
| 102 | |
| 103 | # EMMC RX CMD/DATA Delay 1 |
| 104 | # Refer to EDS-Vol2-14.3.10. |
| 105 | # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. |
| 106 | # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. |
| 107 | # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. |
| 108 | # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. |
| 109 | register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b" |
| 110 | |
| 111 | # EMMC RX CMD/DATA Delay 2 |
| 112 | # Refer to EDS-Vol2-14.3.12. |
| 113 | # [17:16] stands for Rx Clock before Output Buffer, |
| 114 | # 00: Rx clock after output buffer, |
| 115 | # 01: Rx clock before output buffer, |
| 116 | # 10: Automatic selection based on working mode. |
| 117 | # 11: Reserved |
| 118 | # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. |
| 119 | # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. |
| 120 | register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D" |
| 121 | |
| 122 | # EMMC Rx Strobe Delay |
| 123 | # Refer to EDS-Vol2-14.3.11. |
| 124 | # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. |
| 125 | # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. |
| 126 | register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" |
| 127 | |
| 128 | # Intel HDA - disable I2S Audio SSP1 and DMIC0 as puff variant does not have them. |
| 129 | register "PchHdaAudioLinkSsp1" = "0" |
| 130 | register "PchHdaAudioLinkDmic0" = "0" |
| 131 | |
| 132 | # Intel Common SoC Config |
| 133 | #+-------------------+---------------------------+ |
| 134 | #| Field | Value | |
| 135 | #+-------------------+---------------------------+ |
| 136 | #| GSPI0 | cr50 TPM. Early init is | |
| 137 | #| | required to set up a BAR | |
| 138 | #| | for TPM communication | |
| 139 | #| | before memory is up | |
| 140 | #| I2C0 | RFU | |
| 141 | #| I2C2 | PS175 | |
| 142 | #| I2C3 | MST | |
| 143 | #| I2C4 | Audio | |
| 144 | #+-------------------+---------------------------+ |
| 145 | register "common_soc_config" = "{ |
| 146 | .gspi[0] = { |
| 147 | .speed_mhz = 1, |
| 148 | .early_init = 1, |
| 149 | }, |
| 150 | .i2c[0] = { |
| 151 | .speed = I2C_SPEED_FAST, |
| 152 | .rise_time_ns = 0, |
| 153 | .fall_time_ns = 0, |
| 154 | }, |
| 155 | .i2c[2] = { |
| 156 | .speed = I2C_SPEED_FAST, |
Sam McNally | e36733b | 2020-06-11 16:18:20 +1000 | [diff] [blame] | 157 | .rise_time_ns = 60, |
| 158 | .fall_time_ns = 60, |
Edward O'Callaghan | a81be27d | 2020-05-29 14:13:08 +1000 | [diff] [blame] | 159 | }, |
| 160 | .i2c[3] = { |
| 161 | .speed = I2C_SPEED_FAST, |
Sam McNally | e36733b | 2020-06-11 16:18:20 +1000 | [diff] [blame] | 162 | .rise_time_ns = 60, |
| 163 | .fall_time_ns = 60, |
Edward O'Callaghan | a81be27d | 2020-05-29 14:13:08 +1000 | [diff] [blame] | 164 | }, |
| 165 | .i2c[4] = { |
| 166 | .speed = I2C_SPEED_FAST, |
| 167 | .rise_time_ns = 60, |
| 168 | .fall_time_ns = 60, |
| 169 | }, |
| 170 | }" |
| 171 | |
| 172 | # PCIe port 7 for LAN |
| 173 | register "PcieRpEnable[6]" = "1" |
| 174 | register "PcieRpLtrEnable[6]" = "1" |
| 175 | # PCIe port 11 (x2) for NVMe hybrid storage devices |
| 176 | register "PcieRpEnable[10]" = "1" |
| 177 | register "PcieRpLtrEnable[10]" = "1" |
| 178 | # Uses CLK SRC 0 |
| 179 | register "PcieClkSrcUsage[0]" = "6" |
| 180 | register "PcieClkSrcClkReq[0]" = "0" |
| 181 | |
| 182 | # GPIO for SD card detect |
| 183 | register "sdcard_cd_gpio" = "vSD3_CD_B" |
| 184 | |
| 185 | # SATA port 1 Gen3 Strength |
| 186 | # Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB |
| 187 | register "sata_port[1].TxGen3DeEmphEnable" = "1" |
| 188 | register "sata_port[1].TxGen3DeEmph" = "0x20" |
| 189 | |
| 190 | device domain 0 on |
| 191 | device pci 14.0 on |
| 192 | chip drivers/usb/acpi |
| 193 | device usb 0.0 on |
| 194 | chip drivers/usb/acpi |
| 195 | register "desc" = ""USB2 Type-A Front Left"" |
| 196 | register "type" = "UPC_TYPE_A" |
| 197 | register "group" = "ACPI_PLD_GROUP(0, 0)" |
| 198 | device usb 2.0 on end |
| 199 | end |
| 200 | chip drivers/usb/acpi |
| 201 | register "desc" = ""USB2 Type-C Port Rear"" |
| 202 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 203 | register "group" = "ACPI_PLD_GROUP(1, 3)" |
| 204 | device usb 2.1 on end |
| 205 | end |
| 206 | chip drivers/usb/acpi |
| 207 | register "desc" = ""USB2 Type-A Front Right"" |
| 208 | register "type" = "UPC_TYPE_A" |
| 209 | register "group" = "ACPI_PLD_GROUP(0, 1)" |
| 210 | device usb 2.2 on end |
| 211 | end |
| 212 | chip drivers/usb/acpi |
| 213 | register "desc" = ""USB2 Type-A Rear Right"" |
| 214 | register "type" = "UPC_TYPE_A" |
| 215 | register "group" = "ACPI_PLD_GROUP(1, 2)" |
| 216 | device usb 2.3 on end |
| 217 | end |
| 218 | chip drivers/usb/acpi |
Edward O'Callaghan | a81be27d | 2020-05-29 14:13:08 +1000 | [diff] [blame] | 219 | register "desc" = ""USB2 Type-A Rear Left"" |
| 220 | register "type" = "UPC_TYPE_A" |
| 221 | register "group" = "ACPI_PLD_GROUP(1, 0)" |
| 222 | device usb 2.5 on end |
| 223 | end |
| 224 | chip drivers/usb/acpi |
| 225 | device usb 2.6 off end |
| 226 | end |
| 227 | chip drivers/usb/acpi |
| 228 | register "desc" = ""USB3 Type-A Front Left"" |
| 229 | register "type" = "UPC_TYPE_USB3_A" |
| 230 | register "group" = "ACPI_PLD_GROUP(0, 0)" |
| 231 | device usb 3.0 on end |
| 232 | end |
| 233 | chip drivers/usb/acpi |
| 234 | register "desc" = ""USB3 Type-A Front Right"" |
| 235 | register "type" = "UPC_TYPE_USB3_A" |
| 236 | register "group" = "ACPI_PLD_GROUP(0, 1)" |
| 237 | device usb 3.1 on end |
| 238 | end |
| 239 | chip drivers/usb/acpi |
| 240 | register "desc" = ""USB3 Type-A Rear Right"" |
| 241 | register "type" = "UPC_TYPE_USB3_A" |
| 242 | register "group" = "ACPI_PLD_GROUP(1, 2)" |
| 243 | device usb 3.2 on end |
| 244 | end |
| 245 | chip drivers/usb/acpi |
| 246 | register "desc" = ""USB3 Type-C Rear"" |
| 247 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 248 | register "group" = "ACPI_PLD_GROUP(1, 3)" |
| 249 | device usb 3.3 on end |
| 250 | end |
| 251 | chip drivers/usb/acpi |
| 252 | register "desc" = ""USB3 Type-A Rear Left"" |
| 253 | register "type" = "UPC_TYPE_USB3_A" |
| 254 | register "group" = "ACPI_PLD_GROUP(1, 0)" |
| 255 | device usb 3.4 on end |
| 256 | end |
Edward O'Callaghan | a81be27d | 2020-05-29 14:13:08 +1000 | [diff] [blame] | 257 | end |
| 258 | end |
| 259 | end # USB xHCI |
| 260 | device pci 15.0 off |
| 261 | # RFU - Reserved for Future Use. |
| 262 | end # I2C #0 |
| 263 | device pci 15.1 off end # I2C #1 |
| 264 | device pci 15.2 on end # I2C #2, PCON PS175. |
| 265 | device pci 15.3 on end # I2C #3, Realtek RTD2142. |
| 266 | device pci 19.0 on |
| 267 | chip drivers/i2c/generic |
| 268 | register "hid" = ""10EC5682"" |
| 269 | register "name" = ""RT58"" |
| 270 | register "desc" = ""Realtek RT5682"" |
| 271 | register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" |
| 272 | register "property_count" = "1" |
| 273 | # Set the jd_src to RT5668_JD1 for jack detection |
| 274 | register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" |
| 275 | register "property_list[0].name" = ""realtek,jd-src"" |
| 276 | register "property_list[0].integer" = "1" |
| 277 | device i2c 1a on end |
| 278 | end |
| 279 | end #I2C #4 |
| 280 | device pci 1a.0 on end # eMMC |
| 281 | device pci 1c.6 on |
| 282 | chip drivers/net |
| 283 | register "customized_leds" = "0x05af" |
| 284 | register "wake" = "GPE0_DW1_07" # GPP_C7 |
| 285 | register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A18)" |
| 286 | register "stop_delay_ms" = "12" # NIC needs time to quiesce |
| 287 | register "stop_off_delay_ms" = "1" |
| 288 | register "has_power_resource" = "1" |
| 289 | register "device_index" = "0" |
| 290 | device pci 00.0 on end |
| 291 | end |
| 292 | end # RTL8111H Ethernet NIC |
| 293 | device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) |
| 294 | device pci 1e.3 off end # GSPI #1 |
| 295 | end |
| 296 | |
| 297 | # VR Settings Configuration for 4 Domains |
| 298 | #+----------------+-------+-------+-------+-------+ |
| 299 | #| Domain/Setting | SA | IA | GTUS | GTS | |
| 300 | #+----------------+-------+-------+-------+-------+ |
| 301 | #| Psi1Threshold | 20A | 20A | 20A | 20A | |
| 302 | #| Psi2Threshold | 5A | 5A | 5A | 5A | |
| 303 | #| Psi3Threshold | 1A | 1A | 1A | 1A | |
| 304 | #| Psi3Enable | 1 | 1 | 1 | 1 | |
| 305 | #| Psi4Enable | 1 | 1 | 1 | 1 | |
| 306 | #| ImonSlope | 0 | 0 | 0 | 0 | |
| 307 | #| ImonOffset | 0 | 0 | 0 | 0 | |
| 308 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | |
| 309 | #| AcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | |
| 310 | #| DcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | |
| 311 | #+----------------+-------+-------+-------+-------+ |
| 312 | #Note: IccMax settings are moved to SoC code |
| 313 | register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
| 314 | .vr_config_enable = 1, |
| 315 | .psi1threshold = VR_CFG_AMP(20), |
| 316 | .psi2threshold = VR_CFG_AMP(5), |
| 317 | .psi3threshold = VR_CFG_AMP(1), |
| 318 | .psi3enable = 1, |
| 319 | .psi4enable = 1, |
| 320 | .imon_slope = 0x0, |
| 321 | .imon_offset = 0x0, |
| 322 | .icc_max = 0, |
| 323 | .voltage_limit = 1520, |
| 324 | .ac_loadline = 1004, |
| 325 | .dc_loadline = 1004, |
| 326 | }" |
| 327 | |
| 328 | register "domain_vr_config[VR_IA_CORE]" = "{ |
| 329 | .vr_config_enable = 1, |
| 330 | .psi1threshold = VR_CFG_AMP(20), |
| 331 | .psi2threshold = VR_CFG_AMP(5), |
| 332 | .psi3threshold = VR_CFG_AMP(1), |
| 333 | .psi3enable = 1, |
| 334 | .psi4enable = 1, |
| 335 | .imon_slope = 0x0, |
| 336 | .imon_offset = 0x0, |
| 337 | .icc_max = 0, |
| 338 | .voltage_limit = 1520, |
| 339 | .ac_loadline = 181, |
| 340 | .dc_loadline = 181, |
| 341 | }" |
| 342 | |
| 343 | register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
| 344 | .vr_config_enable = 1, |
| 345 | .psi1threshold = VR_CFG_AMP(20), |
| 346 | .psi2threshold = VR_CFG_AMP(5), |
| 347 | .psi3threshold = VR_CFG_AMP(1), |
| 348 | .psi3enable = 1, |
| 349 | .psi4enable = 1, |
| 350 | .imon_slope = 0x0, |
| 351 | .imon_offset = 0x0, |
| 352 | .icc_max = 0, |
| 353 | .voltage_limit = 1520, |
| 354 | .ac_loadline = 319, |
| 355 | .dc_loadline = 319, |
| 356 | }" |
| 357 | |
| 358 | register "domain_vr_config[VR_GT_SLICED]" = "{ |
| 359 | .vr_config_enable = 1, |
| 360 | .psi1threshold = VR_CFG_AMP(20), |
| 361 | .psi2threshold = VR_CFG_AMP(5), |
| 362 | .psi3threshold = VR_CFG_AMP(1), |
| 363 | .psi3enable = 1, |
| 364 | .psi4enable = 1, |
| 365 | .imon_slope = 0x0, |
| 366 | .imon_offset = 0x0, |
| 367 | .icc_max = 0, |
| 368 | .voltage_limit = 1520, |
| 369 | .ac_loadline = 319, |
| 370 | .dc_loadline = 319, |
| 371 | }" |
| 372 | |
| 373 | end |