blob: a416ab8358b8361e127604d3c9682a190a3acdfb [file] [log] [blame]
Kerry Shehc94940c2012-02-07 20:31:40 +08001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Kerry Shehc94940c2012-02-07 20:31:40 +080014 */
15
16
Stefan Reinauer24d1d4b2013-03-21 11:51:41 -070017#include <arch/io.h>
Kyösti Mälkki3855c012019-03-03 08:45:19 +020018#include <device/pnp_ops.h>
Edward O'Callaghand2da65e2014-08-06 21:32:50 +100019#include <device/pnp.h>
20#include <stdint.h>
21
Kerry Shehc94940c2012-02-07 20:31:40 +080022#include "sch4037.h"
23
Edward O'Callaghan85836c22014-07-09 20:26:25 +100024static void pnp_enter_conf_state(pnp_devfn_t dev)
Kerry Shehc94940c2012-02-07 20:31:40 +080025{
Edward O'Callaghand2da65e2014-08-06 21:32:50 +100026 unsigned port = dev >> 8;
Kerry Shehc94940c2012-02-07 20:31:40 +080027 outb(0x55, port);
28}
29
Edward O'Callaghan85836c22014-07-09 20:26:25 +100030static void pnp_exit_conf_state(pnp_devfn_t dev)
Kerry Shehc94940c2012-02-07 20:31:40 +080031{
Edward O'Callaghand2da65e2014-08-06 21:32:50 +100032 unsigned port = dev >> 8;
Kerry Shehc94940c2012-02-07 20:31:40 +080033 outb(0xaa, port);
34}
35
Edward O'Callaghand2da65e2014-08-06 21:32:50 +100036void sch4037_early_init(unsigned port)
Kerry Shehc94940c2012-02-07 20:31:40 +080037{
Edward O'Callaghan85836c22014-07-09 20:26:25 +100038 pnp_devfn_t dev;
Kerry Shehc94940c2012-02-07 20:31:40 +080039
40 dev = PNP_DEV(port, SMSCSUPERIO_SP1);
41 pnp_enter_conf_state(dev);
42
43 /* Auto power management */
44 pnp_write_config(dev, 0x22, 0x38); /* BIT3+BIT4+BIT5 */
Elyes HAOUASa342f392018-10-17 10:56:26 +020045 pnp_write_config(dev, 0x23, 0);
Kerry Shehc94940c2012-02-07 20:31:40 +080046
47 /* Enable SMSC UART 0 */
48 dev = PNP_DEV(port, SMSCSUPERIO_SP1);
49 pnp_set_logical_device(dev);
50 pnp_set_enable(dev, 0);
51
52 pnp_set_iobase(dev, PNP_IDX_IO0, CONFIG_TTYS0_BASE);
53 pnp_set_irq(dev, PNP_IDX_IRQ0, 0x4);
54
55 /* Enabled High speed, disabled MIDI support. */
56 pnp_write_config(dev, 0xF0, 0x02);
57 pnp_set_enable(dev, 1);
58
59 /* Enable keyboard */
60 dev = PNP_DEV(port, SCH4037_KBC);
61 pnp_set_logical_device(dev);
62 pnp_set_enable(dev, 0);
63 pnp_set_irq(dev, 0x70, 1); /* IRQ 1 */
64 pnp_set_irq(dev, 0x72, 12); /* IRQ 12 */
65 pnp_set_enable(dev, 1);
66
67 pnp_exit_conf_state(dev);
68}