| Tim Chu | 5c19640 | 2022-12-13 12:09:44 +0000 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
| Patrick Rudolph | f25d58c | 2024-01-31 11:31:55 +0100 | [diff] [blame^] | 3 | #include <device/pci_ops.h> |
| Tim Chu | 5c19640 | 2022-12-13 12:09:44 +0000 | [diff] [blame] | 4 | #include <soc/acpi.h> |
| 5 | #include <soc/numa.h> |
| 6 | #include <soc/util.h> |
| 7 | |
| 8 | unsigned long cxl_fill_srat(unsigned long current) |
| 9 | { |
| 10 | /* |
| 11 | * Create Generic Initiator Affinity structure |
| 12 | * and Memory Affinity structure for CXL memory. |
| 13 | * In the pds (Proximity Domains structure), Generic Initiator domains |
| 14 | * are after processor domains. |
| 15 | */ |
| 16 | uint16_t seg = 0; |
| 17 | uint8_t bus, dev, func; |
| 18 | uint32_t base, size; |
| 19 | for (uint8_t i = soc_get_num_cpus(); i < pds.num_pds; i++) { |
| Patrick Rudolph | f25d58c | 2024-01-31 11:31:55 +0100 | [diff] [blame^] | 20 | bus = PCI_BDF(pds.pds[i].dev) >> 20; |
| 21 | dev = (PCI_BDF(pds.pds[i].dev) >> 15) & 0x1f; |
| 22 | func = (PCI_BDF(pds.pds[i].dev) >> 12) & 0x07; |
| Tim Chu | 5c19640 | 2022-12-13 12:09:44 +0000 | [diff] [blame] | 23 | printk(BIOS_DEBUG, |
| 24 | "adding srat GIA ID: %d, seg: 0x%x, bus: 0x%x, dev: 0x%x, func: 0x%x\n", |
| 25 | i, seg, bus, dev, func); |
| 26 | /* flags: 1 (enabled) */ |
| 27 | current += acpi_create_srat_gia_pci((acpi_srat_gia_t *)current, i, seg, bus, |
| 28 | dev, func, 1); |
| 29 | base = pds.pds[i].base << 16; |
| 30 | size = pds.pds[i].size << 16; |
| 31 | printk(BIOS_DEBUG, |
| 32 | "adding srat MEM affinity domain: %d, base: 0x%x, size: 0x%x\n", i, base, |
| 33 | size); |
| 34 | current += |
| 35 | acpi_create_srat_mem((acpi_srat_mem_t *)current, i, |
| 36 | pds.pds[i].base << 16, pds.pds[i].size << 16, 1); |
| 37 | } |
| 38 | |
| 39 | return current; |
| 40 | } |
| 41 | |
| 42 | /* |
| 43 | * The current kernel does not use HMAT table. |
| 44 | */ |
| 45 | unsigned long acpi_fill_hmat(unsigned long current) |
| 46 | { |
| 47 | uint32_t pd_initiator = 0; |
| 48 | uint32_t pd_memory = 0; |
| 49 | |
| 50 | /* In CXL2.0, CXL memories attached to different sockets could be ganged |
| 51 | * to form a single CXL memory region. |
| 52 | * For now, we do not consider this case, and assume socket_bitmap has |
| 53 | * only one bit set, eg. a CXL memory region is attached to one socket. |
| 54 | */ |
| 55 | uint8_t j; |
| 56 | for (uint8_t i = soc_get_num_cpus(); i < pds.num_pds; i++) { |
| 57 | pd_memory = i; |
| 58 | /* check socket_bitmap which is type uint8_t */ |
| 59 | for (j = 0; j < 8; j++) |
| 60 | if ((pds.pds[i].socket_bitmap >> j) == 0) |
| 61 | break; |
| 62 | pd_initiator = j - 1; |
| 63 | printk(BIOS_DEBUG, "HMAT: pd_initiator = %d, pd_memory = %d\n", pd_initiator, |
| 64 | pd_memory); |
| 65 | current += acpi_create_hmat_mpda((acpi_hmat_mpda_t *)current, pd_initiator, |
| 66 | pd_memory); |
| 67 | } |
| 68 | |
| 69 | /* |
| 70 | * We created only MPDA structure. In future, we could create |
| 71 | * SLLBI structure to describe latency/bandwidth info when such info |
| 72 | * is available. |
| 73 | */ |
| 74 | |
| 75 | return current; |
| 76 | } |