Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 4 | * This program is free software; you can redistribute it and/or |
| 5 | * modify it under the terms of the GNU General Public License as |
| 6 | * published by the Free Software Foundation; version 2 of |
| 7 | * the License. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 13 | */ |
| 14 | |
| 15 | #ifndef _CPU_INTEL_MODEL_206AX_H |
| 16 | #define _CPU_INTEL_MODEL_206AX_H |
| 17 | |
Elyes HAOUAS | dfbe6bd | 2018-10-29 06:56:52 +0100 | [diff] [blame] | 18 | #include <stdint.h> |
| 19 | |
Stefan Reinauer | c0f2cfb | 2012-07-10 17:16:10 -0700 | [diff] [blame] | 20 | /* SandyBridge/IvyBridge bus clock is fixed at 100MHz */ |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 21 | #define SANDYBRIDGE_BCLK 100 |
| 22 | |
Elyes HAOUAS | a6a396d | 2019-05-26 13:25:30 +0200 | [diff] [blame] | 23 | #define MSR_CORE_THREAD_COUNT 0x35 |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 24 | #define MSR_FEATURE_CONFIG 0x13c |
Duncan Laurie | 22935e1 | 2012-07-09 09:58:35 -0700 | [diff] [blame] | 25 | #define MSR_FLEX_RATIO 0x194 |
| 26 | #define FLEX_RATIO_LOCK (1 << 20) |
| 27 | #define FLEX_RATIO_EN (1 << 16) |
Duncan Laurie | 5563211 | 2012-07-16 12:19:00 -0700 | [diff] [blame] | 28 | #define MSR_TEMPERATURE_TARGET 0x1a2 |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 29 | #define MSR_LT_LOCK_MEMORY 0x2e7 |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 30 | #define MSR_PIC_MSG_CONTROL 0x2e |
| 31 | #define MSR_PLATFORM_INFO 0xce |
| 32 | #define PLATFORM_INFO_SET_TDP (1 << 29) |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 33 | |
| 34 | #define MSR_MISC_PWR_MGMT 0x1aa |
| 35 | #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) |
| 36 | #define MSR_TURBO_RATIO_LIMIT 0x1ad |
| 37 | #define MSR_POWER_CTL 0x1fc |
| 38 | |
| 39 | #define MSR_PKGC3_IRTL 0x60a |
| 40 | #define MSR_PKGC6_IRTL 0x60b |
| 41 | #define MSR_PKGC7_IRTL 0x60c |
| 42 | #define IRTL_VALID (1 << 15) |
| 43 | #define IRTL_1_NS (0 << 10) |
| 44 | #define IRTL_32_NS (1 << 10) |
| 45 | #define IRTL_1024_NS (2 << 10) |
| 46 | #define IRTL_32768_NS (3 << 10) |
| 47 | #define IRTL_1048576_NS (4 << 10) |
| 48 | #define IRTL_33554432_NS (5 << 10) |
| 49 | #define IRTL_RESPONSE_MASK (0x3ff) |
| 50 | |
| 51 | /* long duration in low dword, short duration in high dword */ |
| 52 | #define MSR_PKG_POWER_LIMIT 0x610 |
| 53 | #define PKG_POWER_LIMIT_MASK 0x7fff |
| 54 | #define PKG_POWER_LIMIT_EN (1 << 15) |
| 55 | #define PKG_POWER_LIMIT_CLAMP (1 << 16) |
| 56 | #define PKG_POWER_LIMIT_TIME_SHIFT 17 |
| 57 | #define PKG_POWER_LIMIT_TIME_MASK 0x7f |
| 58 | |
| 59 | #define MSR_PP0_CURRENT_CONFIG 0x601 |
| 60 | #define PP0_CURRENT_LIMIT (112 << 3) /* 112 A */ |
| 61 | #define MSR_PP1_CURRENT_CONFIG 0x602 |
Duncan Laurie | 4e4320f | 2012-06-25 09:53:58 -0700 | [diff] [blame] | 62 | #define PP1_CURRENT_LIMIT_SNB (35 << 3) /* 35 A */ |
| 63 | #define PP1_CURRENT_LIMIT_IVB (50 << 3) /* 50 A */ |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 64 | #define MSR_PKG_POWER_SKU_UNIT 0x606 |
| 65 | #define MSR_PKG_POWER_SKU 0x614 |
| 66 | #define MSR_PP0_POWER_LIMIT 0x638 |
| 67 | #define MSR_PP1_POWER_LIMIT 0x640 |
| 68 | |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 69 | #define IVB_CONFIG_TDP_MIN_CPUID 0x306a2 |
| 70 | #define MSR_CONFIG_TDP_NOMINAL 0x648 |
| 71 | #define MSR_CONFIG_TDP_LEVEL1 0x649 |
| 72 | #define MSR_CONFIG_TDP_LEVEL2 0x64a |
| 73 | #define MSR_CONFIG_TDP_CONTROL 0x64b |
| 74 | #define MSR_TURBO_ACTIVATION_RATIO 0x64c |
| 75 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 76 | /* P-state configuration */ |
| 77 | #define PSS_MAX_ENTRIES 8 |
| 78 | #define PSS_RATIO_STEP 2 |
| 79 | #define PSS_LATENCY_TRANSITION 10 |
| 80 | #define PSS_LATENCY_BUSMASTER 10 |
| 81 | |
Arthur Heymans | 67031a5 | 2018-02-05 19:08:03 +0100 | [diff] [blame] | 82 | /* Sanity check config options. */ |
Kyösti Mälkki | f6c2068 | 2019-08-02 06:14:50 +0300 | [diff] [blame] | 83 | #if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)) |
| 84 | # error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)" |
Arthur Heymans | 67031a5 | 2018-02-05 19:08:03 +0100 | [diff] [blame] | 85 | #endif |
| 86 | #if (CONFIG_SMM_TSEG_SIZE < 0x800000) |
| 87 | # error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB" |
| 88 | #endif |
| 89 | #if ((CONFIG_SMM_TSEG_SIZE & (CONFIG_SMM_TSEG_SIZE - 1)) != 0) |
| 90 | # error "CONFIG_SMM_TSEG_SIZE is not a power of 2" |
| 91 | #endif |
| 92 | #if ((CONFIG_IED_REGION_SIZE & (CONFIG_IED_REGION_SIZE - 1)) != 0) |
| 93 | # error "CONFIG_IED_REGION_SIZE is not a power of 2" |
| 94 | #endif |
| 95 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 96 | /* Lock MSRs */ |
| 97 | void intel_model_206ax_finalize_smm(void); |
Kyösti Mälkki | 82c0e7e | 2019-11-05 19:06:56 +0200 | [diff] [blame] | 98 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 99 | /* Configure power limits for turbo mode */ |
| 100 | void set_power_limits(u8 power_limit_1_time); |
Duncan Laurie | 77dbbac | 2012-06-25 09:51:59 -0700 | [diff] [blame] | 101 | int cpu_config_tdp_levels(void); |
Patrick Rudolph | 74203de | 2017-11-20 11:57:01 +0100 | [diff] [blame] | 102 | int get_platform_id(void); |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 103 | |
| 104 | #endif |