| commit | dfbe6bd5c38d5feb6aa2778b2351cb13e0b1ecc8 | [log] [tgz] |
|---|---|---|
| author | Elyes HAOUAS <ehaouas@noos.fr> | Mon Oct 29 06:56:52 2018 +0100 |
| committer | Nico Huber <nico.h@gmx.de> | Tue Oct 30 09:41:08 2018 +0000 |
| tree | bb12699462930eb270314a1db317a454cd7ff4c6 | |
| parent | b06f8ddfe8c0e18f962f8b5507a40f4ef430ffc1 [diff] [blame] |
src: Add missing include <stdint.h> Change-Id: I6a9d71e69ed9230b92f0f330875515a5df29fc06 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29312 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index f4d469c..2bf9d32 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h
@@ -17,6 +17,8 @@ #ifndef _CPU_INTEL_MODEL_206AX_H #define _CPU_INTEL_MODEL_206AX_H +#include <stdint.h> + /* SandyBridge/IvyBridge bus clock is fixed at 100MHz */ #define SANDYBRIDGE_BCLK 100