blob: 046cc1da07f8de96db96f9004a3185f9aa6607e4 [file] [log] [blame]
Duncan Lauriec88c54c2014-04-30 16:36:13 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2014 Google Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20#include <arch/io.h>
21#include <cbmem.h>
22#include <device/pci.h>
23#include <broadwell/pci_devs.h>
24#include <broadwell/systemagent.h>
25
Kyösti Mälkki13a845a2014-11-10 19:12:53 +020026unsigned long get_top_of_ram(void)
Duncan Lauriec88c54c2014-04-30 16:36:13 -070027{
28 /*
Duncan Laurie61680272014-05-05 12:42:35 -050029 * Base of DPR is top of usable DRAM below 4GiB. The register has
30 * 1 MiB alignment and reports the TOP of the range, the base
31 * must be calculated from the size in MiB in bits 11:4.
Duncan Lauriec88c54c2014-04-30 16:36:13 -070032 */
Duncan Laurie61680272014-05-05 12:42:35 -050033 u32 dpr = pci_read_config32(SA_DEV_ROOT, DPR);
34 u32 tom = dpr & ~((1 << 20) - 1);
35
36 /* Subtract DMA Protected Range size if enabled */
37 if (dpr & DPR_EPM)
38 tom -= (dpr & DPR_SIZE_MASK) << 16;
39
40 return (unsigned long)tom;
Duncan Lauriec88c54c2014-04-30 16:36:13 -070041}