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Stefan Reinauerdebb11f2008-10-29 04:46:52 +00001/*
2 * This file is part of the coreboot project.
3 *
Stefan Reinauera8e11682009-03-11 14:54:18 +00004 * Copyright (C) 2008-2009 coresystems GmbH
Stefan Reinauerdebb11f2008-10-29 04:46:52 +00005 *
Stefan Reinauera8e11682009-03-11 14:54:18 +00006 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
9 * the License.
Stefan Reinauerdebb11f2008-10-29 04:46:52 +000010 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Stefan Reinauerdebb11f2008-10-29 04:46:52 +000015 */
16
Patrick Georgid0835952010-10-05 09:07:10 +000017#include <arch/io.h>
Kyösti Mälkkif1b58b72019-03-01 13:43:02 +020018#include <device/pci_ops.h>
Patrick Georgid0835952010-10-05 09:07:10 +000019#include <console/console.h>
Patrick Georgid0835952010-10-05 09:07:10 +000020#include <device/pci_def.h>
Arthur Heymans16fe7902017-04-12 17:01:31 +020021#include <southbridge/intel/common/smbus.h>
Stefan Reinauerdebb11f2008-10-29 04:46:52 +000022#include "i82801gx.h"
Stefan Reinauerdebb11f2008-10-29 04:46:52 +000023
Patrick Georgid0835952010-10-05 09:07:10 +000024void enable_smbus(void)
Stefan Reinauerdebb11f2008-10-29 04:46:52 +000025{
Antonello Dettori061d7812016-08-30 22:05:32 +020026 pci_devfn_t dev;
Stefan Reinauerdebb11f2008-10-29 04:46:52 +000027
28 /* Set the SMBus device statically. */
29 dev = PCI_DEV(0x0, 0x1f, 0x3);
30
31 /* Check to make sure we've got the right device. */
Arthur Heymans3f111b02017-03-09 12:02:52 +010032 if (pci_read_config16(dev, 0x2) != 0x27da)
Stefan Reinauerdebb11f2008-10-29 04:46:52 +000033 die("SMBus controller not found!");
Stefan Reinauerdebb11f2008-10-29 04:46:52 +000034
35 /* Set SMBus I/O base. */
36 pci_write_config32(dev, SMB_BASE,
37 SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
38
39 /* Set SMBus enable. */
40 pci_write_config8(dev, HOSTC, HST_EN);
41
42 /* Set SMBus I/O space enable. */
43 pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
44
45 /* Disable interrupt generation. */
46 outb(0, SMBUS_IO_BASE + SMBHSTCTL);
47
48 /* Clear any lingering errors, so transactions can run. */
49 outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
Stefan Reinauer5ab52dd2015-01-05 13:01:01 -080050 printk(BIOS_DEBUG, "SMBus controller enabled.\n");
Stefan Reinauerdebb11f2008-10-29 04:46:52 +000051}
52
Arthur Heymans3f111b02017-03-09 12:02:52 +010053int smbus_read_byte(unsigned int device, unsigned int address)
Stefan Reinauerdebb11f2008-10-29 04:46:52 +000054{
Stefan Reinauera8e11682009-03-11 14:54:18 +000055 return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
Stefan Reinauerdebb11f2008-10-29 04:46:52 +000056}
Arthur Heymans2a7c5192017-03-20 22:32:02 +010057
Kyösti Mälkkic01a5052019-01-30 09:39:23 +020058int i2c_eeprom_read(unsigned int device, unsigned int offset, u32 bytes, u8 *buf)
Arthur Heymans2a7c5192017-03-20 22:32:02 +010059{
Kyösti Mälkkic01a5052019-01-30 09:39:23 +020060 return do_i2c_eeprom_read(SMBUS_IO_BASE, device, offset, bytes, buf);
Arthur Heymans2a7c5192017-03-20 22:32:02 +010061}
Arthur Heymansad29ec32017-05-05 21:08:00 +020062
63int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf)
64{
65 return do_smbus_block_read(SMBUS_IO_BASE, device, cmd, bytes, buf);
66}
67
68int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes,
69 const u8 *buf)
70{
71 return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf);
72}