zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <stdint.h> |
| 17 | #include <arch/io.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame^] | 18 | #include <device/pci_ops.h> |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 19 | |
| 20 | /* |
| 21 | * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. |
| 22 | * |
| 23 | * Hardware should enable LPC ROM by pin straps. This function does not |
| 24 | * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations. |
| 25 | * |
| 26 | * The HUDSON power-on default is to map 512K ROM space. |
| 27 | * |
| 28 | */ |
| 29 | static void hudson_enable_rom(void) |
| 30 | { |
| 31 | u8 reg8; |
Edward O'Callaghan | 9a817ef | 2014-10-26 10:12:15 +1100 | [diff] [blame] | 32 | pci_devfn_t dev; |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 33 | |
| 34 | dev = PCI_DEV(0, 0x14, 3); |
| 35 | |
| 36 | /* Decode variable LPC ROM address ranges 1 and 2. */ |
Kyösti Mälkki | 7d09cfc | 2016-11-20 08:24:12 +0200 | [diff] [blame] | 37 | reg8 = pci_io_read_config8(dev, 0x48); |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 38 | reg8 |= (1 << 3) | (1 << 4); |
Kyösti Mälkki | 7d09cfc | 2016-11-20 08:24:12 +0200 | [diff] [blame] | 39 | pci_io_write_config8(dev, 0x48, reg8); |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 40 | |
| 41 | /* LPC ROM address range 1: */ |
| 42 | /* Enable LPC ROM range mirroring start at 0x000e(0000). */ |
Kyösti Mälkki | 7d09cfc | 2016-11-20 08:24:12 +0200 | [diff] [blame] | 43 | pci_io_write_config16(dev, 0x68, 0x000e); |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 44 | /* Enable LPC ROM range mirroring end at 0x000f(ffff). */ |
Kyösti Mälkki | 7d09cfc | 2016-11-20 08:24:12 +0200 | [diff] [blame] | 45 | pci_io_write_config16(dev, 0x6a, 0x000f); |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 46 | |
| 47 | /* LPC ROM address range 2: */ |
| 48 | /* |
| 49 | * Enable LPC ROM range start at: |
| 50 | * 0xfff8(0000): 512KB |
| 51 | * 0xfff0(0000): 1MB |
| 52 | * 0xffe0(0000): 2MB |
| 53 | * 0xffc0(0000): 4MB |
| 54 | */ |
Kyösti Mälkki | 7d09cfc | 2016-11-20 08:24:12 +0200 | [diff] [blame] | 55 | pci_io_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 56 | /* Enable LPC ROM range end at 0xffff(ffff). */ |
Kyösti Mälkki | 7d09cfc | 2016-11-20 08:24:12 +0200 | [diff] [blame] | 57 | pci_io_write_config16(dev, 0x6e, 0xffff); |
zbao | 246e84b | 2012-07-13 18:47:03 +0800 | [diff] [blame] | 58 | } |
| 59 | |
| 60 | static void bootblock_southbridge_init(void) |
| 61 | { |
| 62 | hudson_enable_rom(); |
| 63 | } |