blob: 6aefc9b141dbaa0c4190c07eb242604cf7e1b5fc [file] [log] [blame]
Martin Roth5474eb12018-05-26 19:22:33 -06001/*
2 * This file is part of the coreboot project.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
Vladimir Serbinenko0f9aa1c2015-05-29 16:52:50 +020014#define __SIMPLE_DEVICE__
15
16#include <types.h>
17#include <string.h>
18#include <device/device.h>
19#include <device/pci.h>
Kyösti Mälkkif1b58b72019-03-01 13:43:02 +020020#include <device/pci_ops.h>
Vladimir Serbinenko0f9aa1c2015-05-29 16:52:50 +020021#include "nehalem.h"
22
23#include <cpu/intel/smm/gen1/smi.h>
24
25void northbridge_write_smram(u8 smram)
26{
Kyösti Mälkkid45114f2013-07-26 08:53:59 +030027 pci_write_config8(PCI_DEV(QUICKPATH_BUS, 0, 1), QPD0F1_SMRAM, smram);
Vladimir Serbinenko0f9aa1c2015-05-29 16:52:50 +020028}