Andrey Korolyov | 60d9ce3 | 2017-08-16 17:53:40 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; version 2 of |
| 10 | * the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
| 18 | // __PRE_RAM__ means: use "unsigned" for device, not a struct. |
| 19 | |
| 20 | #include <stdint.h> |
| 21 | #include <string.h> |
| 22 | #include <arch/io.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame^] | 23 | #include <device/pci_ops.h> |
Andrey Korolyov | 60d9ce3 | 2017-08-16 17:53:40 +0200 | [diff] [blame] | 24 | #include <device/pci_def.h> |
| 25 | #include <device/pnp_def.h> |
| 26 | #include <cpu/x86/lapic.h> |
Andrey Korolyov | 60d9ce3 | 2017-08-16 17:53:40 +0200 | [diff] [blame] | 27 | #include <arch/acpi.h> |
Andrey Korolyov | 60d9ce3 | 2017-08-16 17:53:40 +0200 | [diff] [blame] | 28 | #include <console/console.h> |
| 29 | #include <cpu/x86/bist.h> |
| 30 | #include <cpu/intel/romstage.h> |
| 31 | #include <halt.h> |
| 32 | #include <northbridge/intel/i945/i945.h> |
| 33 | #include <northbridge/intel/i945/raminit.h> |
| 34 | #include <southbridge/intel/i82801gx/i82801gx.h> |
| 35 | #include <southbridge/intel/common/gpio.h> |
| 36 | #include "dock.h" |
| 37 | |
| 38 | static void ich7_enable_lpc(void) |
| 39 | { |
| 40 | // Enable Serial IRQ |
| 41 | pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); |
| 42 | // decode range |
| 43 | pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0210); |
| 44 | // decode range |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 45 | pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN |
| 46 | | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN |
| 47 | | FDD_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); |
Andrey Korolyov | 60d9ce3 | 2017-08-16 17:53:40 +0200 | [diff] [blame] | 48 | |
| 49 | /* range 0x1600 - 0x167f */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 50 | pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x007c1601); |
Andrey Korolyov | 60d9ce3 | 2017-08-16 17:53:40 +0200 | [diff] [blame] | 51 | |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 52 | /* range 0x15e0 - 0x15ef */ |
| 53 | pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x000c15e1); |
Andrey Korolyov | 60d9ce3 | 2017-08-16 17:53:40 +0200 | [diff] [blame] | 54 | |
| 55 | /* range 0x1680 - 0x169f */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 56 | pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x001c1681); |
Andrey Korolyov | 60d9ce3 | 2017-08-16 17:53:40 +0200 | [diff] [blame] | 57 | } |
| 58 | |
| 59 | static void early_superio_config(void) |
| 60 | { |
| 61 | int timeout = 100000; |
| 62 | pnp_devfn_t dev = PNP_DEV(0x2e, 3); |
| 63 | |
| 64 | pnp_write_config(dev, 0x29, 0xa0); |
| 65 | |
| 66 | while(!(pnp_read_config(dev, 0x29) & 0x10) && timeout--) |
| 67 | udelay(1000); |
| 68 | |
| 69 | /* Enable COM1 */ |
| 70 | pnp_set_logical_device(dev); |
| 71 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); |
| 72 | pnp_set_enable(dev, 1); |
| 73 | } |
| 74 | |
| 75 | static void rcba_config(void) |
| 76 | { |
| 77 | /* Set up virtual channel 0 */ |
| 78 | RCBA32(V0CTL) = 0x80000001; |
| 79 | RCBA32(V1CAP) = 0x03128010; |
| 80 | |
| 81 | /* Device 1f interrupt pin register */ |
| 82 | RCBA32(D31IP) = 0x00001230; |
| 83 | RCBA32(D29IP) = 0x40004321; |
| 84 | |
| 85 | /* PCIe Interrupts */ |
| 86 | RCBA32(D28IP) = 0x00004321; |
| 87 | /* HD Audio Interrupt */ |
| 88 | RCBA32(D27IP) = 0x00000002; |
| 89 | |
| 90 | /* dev irq route register */ |
| 91 | RCBA16(D31IR) = 0x1007; |
| 92 | RCBA16(D30IR) = 0x0076; |
| 93 | RCBA16(D29IR) = 0x3210; |
| 94 | RCBA16(D28IR) = 0x7654; |
| 95 | RCBA16(D27IR) = 0x0010; |
| 96 | |
| 97 | /* Enable IOAPIC */ |
| 98 | RCBA8(OIC) = 0x03; |
| 99 | |
| 100 | /* Disable unused devices */ |
Arthur Heymans | 6267f5d | 2018-12-15 23:46:48 +0100 | [diff] [blame] | 101 | RCBA32(FD) |= FD_INTLAN; |
Andrey Korolyov | 60d9ce3 | 2017-08-16 17:53:40 +0200 | [diff] [blame] | 102 | |
| 103 | /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ |
Peter Lemenkov | 522a1b5 | 2019-01-10 12:19:01 +0100 | [diff] [blame] | 104 | RCBA64(IOTR0) = 0x000200010000fe01ULL; |
Andrey Korolyov | 60d9ce3 | 2017-08-16 17:53:40 +0200 | [diff] [blame] | 105 | |
| 106 | /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ |
Peter Lemenkov | 522a1b5 | 2019-01-10 12:19:01 +0100 | [diff] [blame] | 107 | RCBA64(IOTR3) = 0x000200f0000c0801ULL; |
Andrey Korolyov | 60d9ce3 | 2017-08-16 17:53:40 +0200 | [diff] [blame] | 108 | } |
| 109 | |
| 110 | static void early_ich7_init(void) |
| 111 | { |
| 112 | uint8_t reg8; |
| 113 | uint32_t reg32; |
| 114 | |
| 115 | // program secondary mlt XXX byte? |
| 116 | pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); |
| 117 | |
| 118 | // reset rtc power status |
| 119 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); |
| 120 | reg8 &= ~(1 << 2); |
| 121 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); |
| 122 | |
| 123 | // usb transient disconnect |
| 124 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); |
| 125 | reg8 |= (3 << 0); |
| 126 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); |
| 127 | |
| 128 | reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); |
| 129 | reg32 |= (1 << 29) | (1 << 17); |
| 130 | pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); |
| 131 | |
| 132 | reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); |
| 133 | reg32 |= (1 << 31) | (1 << 27); |
| 134 | pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); |
| 135 | |
| 136 | RCBA32(0x0088) = 0x0011d000; |
| 137 | RCBA16(0x01fc) = 0x060f; |
| 138 | RCBA32(0x01f4) = 0x86000040; |
| 139 | RCBA32(0x0214) = 0x10030549; |
| 140 | RCBA32(0x0218) = 0x00020504; |
| 141 | RCBA8(0x0220) = 0xc5; |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 142 | reg32 = RCBA32(GCS); |
Andrey Korolyov | 60d9ce3 | 2017-08-16 17:53:40 +0200 | [diff] [blame] | 143 | reg32 |= (1 << 6); |
| 144 | RCBA32(GCS) = reg32; |
| 145 | reg32 = RCBA32(0x3430); |
| 146 | reg32 &= ~(3 << 0); |
| 147 | reg32 |= (1 << 0); |
| 148 | RCBA32(0x3430) = reg32; |
Andrey Korolyov | 60d9ce3 | 2017-08-16 17:53:40 +0200 | [diff] [blame] | 149 | RCBA16(0x0200) = 0x2008; |
| 150 | RCBA8(0x2027) = 0x0d; |
| 151 | RCBA16(0x3e08) |= (1 << 7); |
| 152 | RCBA16(0x3e48) |= (1 << 7); |
| 153 | RCBA32(0x3e0e) |= (1 << 7); |
| 154 | RCBA32(0x3e4e) |= (1 << 7); |
| 155 | |
| 156 | // next step only on ich7m b0 and later: |
| 157 | reg32 = RCBA32(0x2034); |
| 158 | reg32 &= ~(0x0f << 16); |
| 159 | reg32 |= (5 << 16); |
| 160 | RCBA32(0x2034) = reg32; |
| 161 | } |
| 162 | |
| 163 | void mainboard_romstage_entry(unsigned long bist) |
| 164 | { |
| 165 | int s3resume = 0; |
| 166 | int dock_err; |
| 167 | const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 }; |
| 168 | |
Andrey Korolyov | 60d9ce3 | 2017-08-16 17:53:40 +0200 | [diff] [blame] | 169 | if (bist == 0) |
| 170 | enable_lapic(); |
| 171 | |
| 172 | ich7_enable_lpc(); |
| 173 | |
| 174 | /* We want early GPIO setup, to be able to detect legacy I/O module */ |
| 175 | pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); |
| 176 | /* Enable GPIOs */ |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 177 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */, 0x10); |
Andrey Korolyov | 60d9ce3 | 2017-08-16 17:53:40 +0200 | [diff] [blame] | 178 | setup_pch_gpios(&mainboard_gpio_map); |
| 179 | |
| 180 | dock_err = dlpc_init(); |
| 181 | |
| 182 | /* We prefer Legacy I/O module over docking */ |
| 183 | if (legacy_io_present()) { |
| 184 | legacy_io_init(); |
| 185 | early_superio_config(); |
| 186 | } else if (!dock_err && dock_present()) { |
| 187 | dock_connect(); |
| 188 | early_superio_config(); |
| 189 | } |
| 190 | |
| 191 | /* Setup the console */ |
| 192 | console_init(); |
| 193 | |
| 194 | /* Halt if there was a built in self test failure */ |
| 195 | report_bist_failure(bist); |
| 196 | |
| 197 | if (MCHBAR16(SSKPD) == 0xCAFE) { |
| 198 | printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); |
| 199 | outb(0x6, 0xcf9); |
| 200 | halt(); |
| 201 | } |
| 202 | |
| 203 | /* Perform some early chipset initialization required |
| 204 | * before RAM initialization can work |
| 205 | */ |
| 206 | i945_early_initialization(); |
| 207 | |
| 208 | s3resume = southbridge_detect_s3_resume(); |
| 209 | |
| 210 | /* Enable SPD ROMs and DDR-II DRAM */ |
| 211 | enable_smbus(); |
| 212 | |
| 213 | #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 |
| 214 | dump_spd_registers(); |
| 215 | #endif |
| 216 | |
Andrey Korolyov | 60d9ce3 | 2017-08-16 17:53:40 +0200 | [diff] [blame] | 217 | sdram_initialize(s3resume ? 2 : 0, spd_addrmap); |
Andrey Korolyov | 60d9ce3 | 2017-08-16 17:53:40 +0200 | [diff] [blame] | 218 | |
| 219 | /* Perform some initialization that must run before stage2 */ |
| 220 | early_ich7_init(); |
| 221 | |
| 222 | /* This should probably go away. Until now it is required |
| 223 | * and mainboard specific |
| 224 | */ |
| 225 | rcba_config(); |
| 226 | |
| 227 | /* Chipset Errata! */ |
| 228 | fixup_i945_errata(); |
| 229 | |
| 230 | /* Initialize the internal PCIe links before we go into stage2 */ |
| 231 | i945_late_initialization(s3resume); |
| 232 | } |