Timothy Pearson | 8057285 | 2015-01-23 20:35:48 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering |
| 5 | * |
| 6 | * Copyright (C) 2007 AMD |
| 7 | * Written by Yinghai Lu <yinghailu@amd.com> for AMD. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
Timothy Pearson | 8057285 | 2015-01-23 20:35:48 -0600 | [diff] [blame] | 18 | */ |
| 19 | |
Timothy Pearson | 8057285 | 2015-01-23 20:35:48 -0600 | [diff] [blame] | 20 | #include <stdint.h> |
| 21 | #include <string.h> |
Timothy Pearson | 8057285 | 2015-01-23 20:35:48 -0600 | [diff] [blame] | 22 | #include <device/pci_def.h> |
| 23 | #include <device/pci_ids.h> |
| 24 | #include <arch/io.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame^] | 25 | #include <device/pci_ops.h> |
Elyes HAOUAS | d2b9ec1 | 2018-10-27 09:41:02 +0200 | [diff] [blame] | 26 | #include <arch/cpu.h> |
Timothy Pearson | 8057285 | 2015-01-23 20:35:48 -0600 | [diff] [blame] | 27 | #include <cpu/x86/lapic.h> |
| 28 | #include <console/console.h> |
Timothy Pearson | 91e9f67 | 2015-03-19 16:44:46 -0500 | [diff] [blame] | 29 | #include <timestamp.h> |
Timothy Pearson | 8057285 | 2015-01-23 20:35:48 -0600 | [diff] [blame] | 30 | #include <spd.h> |
Damien Zammit | 75a3d1f | 2016-11-28 00:29:10 +1100 | [diff] [blame] | 31 | #include <cbmem.h> |
Timothy Pearson | 8057285 | 2015-01-23 20:35:48 -0600 | [diff] [blame] | 32 | #include <cpu/amd/model_10xxx_rev.h> |
Damien Zammit | 75a3d1f | 2016-11-28 00:29:10 +1100 | [diff] [blame] | 33 | #include <cpu/amd/car.h> |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 34 | #include <cpu/amd/msr.h> |
Nico Huber | 718c6fa | 2018-10-11 22:54:25 +0200 | [diff] [blame] | 35 | #include <southbridge/amd/common/reset.h> |
Damien Zammit | 75a3d1f | 2016-11-28 00:29:10 +1100 | [diff] [blame] | 36 | #include <southbridge/nvidia/ck804/early_smbus.h> |
Patrick Georgi | 82d9a31 | 2016-01-21 12:46:10 +0100 | [diff] [blame] | 37 | #include <delay.h> |
Timothy Pearson | 8057285 | 2015-01-23 20:35:48 -0600 | [diff] [blame] | 38 | #include <superio/winbond/common/winbond.h> |
| 39 | #include <superio/winbond/w83627thg/w83627thg.h> |
| 40 | #include <cpu/x86/bist.h> |
Damien Zammit | 75a3d1f | 2016-11-28 00:29:10 +1100 | [diff] [blame] | 41 | #include <northbridge/amd/amdht/ht_wrapper.h> |
| 42 | #include <northbridge/amd/amdfam10/raminit.h> |
| 43 | #include <cpu/amd/family_10h-family_15h/init_cpus.h> |
Timothy Pearson | 8057285 | 2015-01-23 20:35:48 -0600 | [diff] [blame] | 44 | |
Timothy Pearson | 8057285 | 2015-01-23 20:35:48 -0600 | [diff] [blame] | 45 | #include "cpu/amd/quadcore/quadcore.c" |
| 46 | |
Damien Zammit | 75a3d1f | 2016-11-28 00:29:10 +1100 | [diff] [blame] | 47 | #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) |
| 48 | |
Timothy Pearson | 8057285 | 2015-01-23 20:35:48 -0600 | [diff] [blame] | 49 | #define CK804_MB_SETUP \ |
| 50 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+33, ~(0x0f),(0x04 | 0x01), /* -ENOINFO Proprietary BIOS sets this register; "When in Rome..."*/ |
| 51 | |
| 52 | #include <southbridge/nvidia/ck804/early_setup_ss.h> |
| 53 | #include "southbridge/nvidia/ck804/early_setup_car.c" |
Timothy Pearson | 8057285 | 2015-01-23 20:35:48 -0600 | [diff] [blame] | 54 | |
| 55 | #define GPIO3_DEV PNP_DEV(0x2e, W83627THG_GPIO3) |
| 56 | |
Damien Zammit | 75a3d1f | 2016-11-28 00:29:10 +1100 | [diff] [blame] | 57 | void activate_spd_rom(const struct mem_controller *ctrl); |
Elyes HAOUAS | dd35e2c | 2018-09-20 17:33:50 +0200 | [diff] [blame] | 58 | int spd_read_byte(unsigned int device, unsigned int address); |
Damien Zammit | 75a3d1f | 2016-11-28 00:29:10 +1100 | [diff] [blame] | 59 | extern struct sys_info sysinfo_car; |
| 60 | |
Elyes HAOUAS | dd35e2c | 2018-09-20 17:33:50 +0200 | [diff] [blame] | 61 | int spd_read_byte(unsigned int device, unsigned int address) |
Damien Zammit | 75a3d1f | 2016-11-28 00:29:10 +1100 | [diff] [blame] | 62 | { |
| 63 | return smbus_read_byte(device, address); |
| 64 | } |
| 65 | |
Timothy Pearson | 8057285 | 2015-01-23 20:35:48 -0600 | [diff] [blame] | 66 | /** |
| 67 | * @brief Get SouthBridge device number |
| 68 | * @param[in] bus target bus number |
| 69 | * @return southbridge device number |
| 70 | */ |
| 71 | unsigned int get_sbdn(unsigned bus) |
| 72 | { |
Antonello Dettori | 837618b | 2016-09-03 10:47:40 +0200 | [diff] [blame] | 73 | pci_devfn_t dev; |
Timothy Pearson | 8057285 | 2015-01-23 20:35:48 -0600 | [diff] [blame] | 74 | |
| 75 | dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, |
| 76 | PCI_DEVICE_ID_NVIDIA_CK804_PRO), bus); |
| 77 | return (dev >> 15) & 0x1f; |
| 78 | } |
| 79 | |
| 80 | /* |
| 81 | * ASUS KFSN4-DRE specific SPD enable/disable magic. |
| 82 | * |
| 83 | * Setting CK804 GPIO43 and GPIO44 to 0 and 0 respectively will make the |
| 84 | * board DIMMs accessible at SMBus/SPD offsets 0x50-0x53. Per default the SPD |
| 85 | * offsets 0x50-0x53 are _not_ readable (all SPD reads will return 0xff) which |
| 86 | * will make RAM init fail. |
| 87 | * |
| 88 | * Disable SPD access after RAM init to allow access to standard SMBus/I2C offsets |
| 89 | * which is required e.g. by lm-sensors. |
| 90 | */ |
| 91 | |
| 92 | #define CK804_BOARD_BOOT_BASE_UNIT_UID 1 |
| 93 | |
| 94 | static const unsigned int ctrl_conf_enable_spd_node0[] = { |
| 95 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+42, ~(0x0f),(0x04 | 0x00),/* W2,GPIO43, U6 input S0*/ |
| 96 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+43, ~(0x0f),(0x04 | 0x00),/* W3,GPIO44, U6 input S1*/ |
| 97 | }; |
| 98 | |
| 99 | static const unsigned int ctrl_conf_enable_spd_node1[] = { |
| 100 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+42, ~(0x0f),(0x04 | 0x00),/* W2,GPIO43, U6 input S0*/ |
| 101 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+43, ~(0x0f),(0x04 | 0x01),/* W3,GPIO44, U6 input S1*/ |
| 102 | }; |
| 103 | |
| 104 | static const unsigned int ctrl_conf_disable_spd[] = { |
| 105 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+42, ~(0x0f),(0x04 | 0x01),/* W2,GPIO43, U6 input S0*/ |
| 106 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+43, ~(0x0f),(0x04 | 0x00),/* W3,GPIO44, U6 input S1*/ |
| 107 | }; |
| 108 | |
| 109 | static const unsigned int ctrl_conf_fix_pci_numbering[] = { |
| 110 | RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x44), ~(0x00010000), 0x00000000, /* Force CK804 to start its internal device numbering (Base Unit ID) at 0 instead of the power-on default of 1 */ |
| 111 | }; |
| 112 | |
| 113 | static const unsigned int ctrl_conf_enable_msi_mapping[] = { |
| 114 | RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xe0), ~(0x00000000), 0x00010000, /* Enable MSI mapping on host bridge -- without this Linux cannot use the network device MSI interrupts! */ |
| 115 | }; |
| 116 | |
Elyes HAOUAS | 448d9fb | 2018-05-22 12:51:27 +0200 | [diff] [blame] | 117 | static void ck804_control(const unsigned int *values, u32 size, |
| 118 | uint8_t bus_unit_id) |
Timothy Pearson | 8057285 | 2015-01-23 20:35:48 -0600 | [diff] [blame] | 119 | { |
| 120 | unsigned busn[4], io_base[4]; |
| 121 | int i, ck804_num = 0; |
| 122 | |
| 123 | for (i = 0; i < 4; i++) { |
| 124 | u32 id; |
Antonello Dettori | 837618b | 2016-09-03 10:47:40 +0200 | [diff] [blame] | 125 | pci_devfn_t dev; |
Timothy Pearson | 8057285 | 2015-01-23 20:35:48 -0600 | [diff] [blame] | 126 | if (i == 0) /* SB chain */ |
| 127 | dev = PCI_DEV(i * 0x40, bus_unit_id, 0); |
| 128 | else |
| 129 | dev = 0; |
| 130 | id = pci_read_config32(dev, PCI_VENDOR_ID); |
| 131 | if (id == 0x005e10de) { |
| 132 | busn[ck804_num] = i * 0x40; |
| 133 | io_base[ck804_num] = i * 0x4000; |
| 134 | ck804_num++; |
| 135 | } |
| 136 | } |
| 137 | |
| 138 | if (ck804_num < 1) |
| 139 | printk(BIOS_WARNING, "CK804 not found at device base unit id %02x!\n", bus_unit_id); |
| 140 | |
| 141 | ck804_early_set_port(ck804_num, busn, io_base); |
| 142 | |
| 143 | setup_resource_map_x_offset(values, |
| 144 | size, |
| 145 | PCI_DEV(0, bus_unit_id, 0), io_base[0]); |
| 146 | |
| 147 | ck804_early_clear_port(ck804_num, busn, io_base); |
| 148 | } |
| 149 | |
| 150 | static void sio_setup(void) |
| 151 | { |
| 152 | u32 dword; |
| 153 | u8 byte; |
| 154 | |
| 155 | /* Subject decoding */ |
| 156 | byte = pci_read_config8(PCI_DEV(0, CK804_BOARD_BOOT_BASE_UNIT_UID + 1, 0), 0x7b); |
| 157 | byte |= 0x20; |
| 158 | pci_write_config8(PCI_DEV(0, CK804_BOARD_BOOT_BASE_UNIT_UID + 1, 0), 0x7b, byte); |
| 159 | |
| 160 | /* LPC Positive Decode 0 */ |
| 161 | dword = pci_read_config32(PCI_DEV(0, CK804_BOARD_BOOT_BASE_UNIT_UID + 1, 0), 0xa0); |
| 162 | /* Serial 0, Serial 1 */ |
| 163 | dword |= (1 << 0) | (1 << 1); |
| 164 | pci_write_config32(PCI_DEV(0, CK804_BOARD_BOOT_BASE_UNIT_UID + 1, 0), 0xa0, dword); |
| 165 | } |
| 166 | |
| 167 | static const uint8_t spd_addr[] = { |
| 168 | // Node 0 |
| 169 | RC00, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7, |
| 170 | // Node 1 |
| 171 | RC01, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7, |
| 172 | }; |
| 173 | |
Damien Zammit | 75a3d1f | 2016-11-28 00:29:10 +1100 | [diff] [blame] | 174 | void activate_spd_rom(const struct mem_controller *ctrl) { |
Timothy Pearson | 8057285 | 2015-01-23 20:35:48 -0600 | [diff] [blame] | 175 | printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id); |
| 176 | if (ctrl->node_id == 0) { |
| 177 | printk(BIOS_DEBUG, "enable_spd_node0()\n"); |
| 178 | ck804_control(ctrl_conf_enable_spd_node0, ARRAY_SIZE(ctrl_conf_enable_spd_node0), CK804_DEVN_BASE); |
| 179 | } |
| 180 | else if (ctrl->node_id == 1) { |
| 181 | printk(BIOS_DEBUG, "enable_spd_node1()\n"); |
| 182 | ck804_control(ctrl_conf_enable_spd_node1, ARRAY_SIZE(ctrl_conf_enable_spd_node1), CK804_DEVN_BASE); |
| 183 | } |
| 184 | } |
| 185 | |
| 186 | void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |
| 187 | { |
| 188 | struct sys_info *sysinfo = &sysinfo_car; |
| 189 | |
| 190 | u32 bsp_apicid = 0, val, wants_reset; |
| 191 | msr_t msr; |
| 192 | |
Timothy Pearson | 91e9f67 | 2015-03-19 16:44:46 -0500 | [diff] [blame] | 193 | timestamp_init(timestamp_get()); |
| 194 | timestamp_add_now(TS_START_ROMSTAGE); |
| 195 | |
Timothy Pearson | 8057285 | 2015-01-23 20:35:48 -0600 | [diff] [blame] | 196 | if (!cpu_init_detectedx && boot_cpu()) { |
| 197 | /* Nothing special needs to be done to find bus 0 */ |
| 198 | /* Allow the HT devices to be found */ |
| 199 | set_bsp_node_CHtExtNodeCfgEn(); |
| 200 | enumerate_ht_chain(); |
| 201 | sio_setup(); |
| 202 | } |
| 203 | |
| 204 | post_code(0x30); |
| 205 | |
| 206 | if (bist == 0) |
| 207 | bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); |
| 208 | |
| 209 | post_code(0x32); |
| 210 | |
| 211 | winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
| 212 | console_init(); |
| 213 | |
| 214 | if (CONFIG_MAX_PHYSICAL_CPUS != 2) |
| 215 | printk(BIOS_WARNING, "CONFIG_MAX_PHYSICAL_CPUS is %d, but this is a dual socket board!\n", CONFIG_MAX_PHYSICAL_CPUS); |
| 216 | |
| 217 | /* Halt if there was a built in self test failure */ |
| 218 | report_bist_failure(bist); |
| 219 | |
| 220 | val = cpuid_eax(1); |
| 221 | printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); |
| 222 | printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); |
| 223 | printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); |
| 224 | printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); |
| 225 | |
| 226 | /* Setup sysinfo defaults */ |
| 227 | set_sysinfo_in_ram(0); |
| 228 | |
| 229 | update_microcode(val); |
| 230 | |
| 231 | post_code(0x33); |
| 232 | |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 233 | cpuSetAMDMSR(0); |
Timothy Pearson | 8057285 | 2015-01-23 20:35:48 -0600 | [diff] [blame] | 234 | post_code(0x34); |
| 235 | |
| 236 | amd_ht_init(sysinfo); |
| 237 | post_code(0x35); |
| 238 | |
| 239 | /* Setup nodes PCI space and start core 0 AP init. */ |
| 240 | finalize_node_setup(sysinfo); |
| 241 | |
| 242 | /* Setup any mainboard PCI settings etc. */ |
| 243 | setup_mb_resource_map(); |
| 244 | post_code(0x36); |
| 245 | |
| 246 | /* wait for all the APs core0 started by finalize_node_setup. */ |
| 247 | /* FIXME: A bunch of cores are going to start output to serial at once. |
| 248 | * It would be nice to fix up prink spinlocks for ROM XIP mode. |
| 249 | * I think it could be done by putting the spinlock flag in the cache |
| 250 | * of the BSP located right after sysinfo. |
| 251 | */ |
| 252 | wait_all_core0_started(); |
| 253 | |
Timothy Pearson | 8057285 | 2015-01-23 20:35:48 -0600 | [diff] [blame] | 254 | if (IS_ENABLED(CONFIG_SET_FIDVID)) { |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 255 | msr = rdmsr(MSR_COFVID_STS); |
Timothy Pearson | 8057285 | 2015-01-23 20:35:48 -0600 | [diff] [blame] | 256 | printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); |
| 257 | |
| 258 | post_code(0x39); |
| 259 | |
| 260 | if (!warm_reset_detect(0)) { // BSP is node 0 |
| 261 | init_fidvid_bsp(bsp_apicid, sysinfo->nodes); |
| 262 | } else { |
| 263 | init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 |
| 264 | } |
| 265 | |
| 266 | post_code(0x3A); |
| 267 | |
| 268 | /* show final fid and vid */ |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 269 | msr = rdmsr(MSR_COFVID_STS); |
Timothy Pearson | 8057285 | 2015-01-23 20:35:48 -0600 | [diff] [blame] | 270 | printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); |
| 271 | } |
| 272 | |
Timothy Pearson | f73179d | 2015-02-10 00:37:21 -0600 | [diff] [blame] | 273 | if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) { |
| 274 | /* Core0 on each node is configured. Now setup any additional cores. */ |
| 275 | printk(BIOS_DEBUG, "start_other_cores()\n"); |
Timothy Pearson | 0122afb | 2015-07-30 14:07:15 -0500 | [diff] [blame] | 276 | start_other_cores(bsp_apicid); |
Timothy Pearson | f73179d | 2015-02-10 00:37:21 -0600 | [diff] [blame] | 277 | post_code(0x37); |
| 278 | wait_all_other_cores_started(bsp_apicid); |
| 279 | } |
| 280 | |
| 281 | printk(BIOS_DEBUG, "set_ck804_base_unit_id()\n"); |
| 282 | ck804_control(ctrl_conf_fix_pci_numbering, ARRAY_SIZE(ctrl_conf_fix_pci_numbering), CK804_BOARD_BOOT_BASE_UNIT_UID); |
| 283 | |
| 284 | post_code(0x38); |
| 285 | |
Timothy Pearson | 8057285 | 2015-01-23 20:35:48 -0600 | [diff] [blame] | 286 | init_timer(); // Need to use TMICT to synconize FID/VID |
| 287 | |
| 288 | wants_reset = ck804_early_setup_x(); |
| 289 | |
| 290 | /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ |
| 291 | if (!warm_reset_detect(0)) { |
| 292 | printk(BIOS_INFO, "...WARM RESET...\n\n\n"); |
| 293 | soft_reset(); |
Jonathan Neuschäfer | ec48c74 | 2017-09-29 02:45:31 +0200 | [diff] [blame] | 294 | die("After soft_reset - shouldn't see this message!!!\n"); |
Timothy Pearson | 8057285 | 2015-01-23 20:35:48 -0600 | [diff] [blame] | 295 | } |
| 296 | |
| 297 | if (wants_reset) { |
| 298 | printk(BIOS_DEBUG, "ck804_early_setup_x wanted additional reset!\n"); |
| 299 | } |
| 300 | |
| 301 | post_code(0x3B); |
| 302 | |
| 303 | /* It's the time to set ctrl in sysinfo now; */ |
| 304 | printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); |
| 305 | fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); |
| 306 | post_code(0x3D); |
| 307 | |
| 308 | printk(BIOS_DEBUG, "enable_smbus()\n"); |
| 309 | enable_smbus(); |
| 310 | |
| 311 | #if 0 |
| 312 | /* FIXME |
| 313 | * After the AMD K10 code has been converted to use |
| 314 | * IS_ENABLED(CONFIG_DEBUG_SMBUS) uncomment this block |
| 315 | */ |
| 316 | if (IS_ENABLED(CONFIG_DEBUG_SMBUS)) { |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 317 | dump_spd_registers(&cpu[0]); |
| 318 | dump_smbus_registers(); |
Timothy Pearson | 8057285 | 2015-01-23 20:35:48 -0600 | [diff] [blame] | 319 | } |
| 320 | #endif |
| 321 | |
| 322 | post_code(0x40); |
| 323 | |
Timothy Pearson | 8057285 | 2015-01-23 20:35:48 -0600 | [diff] [blame] | 324 | raminit_amdmct(sysinfo); |
Timothy Pearson | 91e9f67 | 2015-03-19 16:44:46 -0500 | [diff] [blame] | 325 | |
Timothy Pearson | 86f4ca5 | 2015-03-13 13:27:58 -0500 | [diff] [blame] | 326 | cbmem_initialize_empty(); |
Timothy Pearson | 8057285 | 2015-01-23 20:35:48 -0600 | [diff] [blame] | 327 | post_code(0x41); |
| 328 | |
Timothy Pearson | 2256408 | 2015-03-27 22:49:18 -0500 | [diff] [blame] | 329 | amdmct_cbmem_store_info(sysinfo); |
| 330 | |
Timothy Pearson | 8057285 | 2015-01-23 20:35:48 -0600 | [diff] [blame] | 331 | printk(BIOS_DEBUG, "disable_spd()\n"); |
| 332 | ck804_control(ctrl_conf_disable_spd, ARRAY_SIZE(ctrl_conf_disable_spd), CK804_DEVN_BASE); |
| 333 | |
| 334 | printk(BIOS_DEBUG, "enable_msi_mapping()\n"); |
| 335 | ck804_control(ctrl_conf_enable_msi_mapping, ARRAY_SIZE(ctrl_conf_enable_msi_mapping), CK804_DEVN_BASE); |
| 336 | |
| 337 | /* Initialize GPIO */ |
| 338 | /* Access SuperIO GPI03 logical device */ |
Elyes HAOUAS | ddcf5a0 | 2018-08-06 10:40:07 +0200 | [diff] [blame] | 339 | pnp_enter_conf_state(GPIO3_DEV); |
Timothy Pearson | 8057285 | 2015-01-23 20:35:48 -0600 | [diff] [blame] | 340 | pnp_set_logical_device(GPIO3_DEV); |
| 341 | /* Set GP37 (power LED) to output */ |
| 342 | pnp_write_config(GPIO3_DEV, 0xf0, 0x7f); |
| 343 | /* Set GP37 (power LED) on */ |
| 344 | pnp_write_config(GPIO3_DEV, 0xf1, 0x80); |
| 345 | /* Set pin 64 multiplex to GP37 */ |
| 346 | uint8_t cr2c = pnp_read_config(GPIO3_DEV, 0x2c); |
| 347 | pnp_write_config(GPIO3_DEV, 0x2c, (cr2c & 0xf3) | 0x04); |
| 348 | /* Restore default SuperIO access */ |
Elyes HAOUAS | ddcf5a0 | 2018-08-06 10:40:07 +0200 | [diff] [blame] | 349 | pnp_exit_conf_state(GPIO3_DEV); |
Timothy Pearson | 8057285 | 2015-01-23 20:35:48 -0600 | [diff] [blame] | 350 | } |
| 351 | |
| 352 | /** |
| 353 | * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) |
| 354 | * Description: |
| 355 | * This routine is called every time a non-coherent chain is processed. |
| 356 | * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a |
| 357 | * swap list. The first part of the list controls the BUID assignment and the |
| 358 | * second part of the list provides the device to device linking. Device orientation |
| 359 | * can be detected automatically, or explicitly. See documentation for more details. |
| 360 | * |
| 361 | * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially |
| 362 | * based on each device's unit count. |
| 363 | * |
| 364 | * Parameters: |
| 365 | * @param[in] node = The node on which this chain is located |
| 366 | * @param[in] link = The link on the host for this chain |
| 367 | * @param[out] List = supply a pointer to a list |
| 368 | */ |
| 369 | BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) |
| 370 | { |
| 371 | return 0; |
| 372 | } |