Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | /* |
| 18 | * This is a ramstage driver for the Intel Management Engine found in the |
| 19 | * 6-series chipset. It handles the required boot-time messages over the |
| 20 | * MMIO-based Management Engine Interface to tell the ME that the BIOS is |
| 21 | * finished with POST. Additional messages are defined for debug but are |
| 22 | * not used unless the console loglevel is high enough. |
| 23 | */ |
| 24 | |
| 25 | #include <arch/acpi.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 26 | #include <arch/io.h> |
| 27 | #include <console/console.h> |
Stefan Reinauer | 24d1d4b | 2013-03-21 11:51:41 -0700 | [diff] [blame] | 28 | #include <device/device.h> |
| 29 | #include <device/pci.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 30 | #include <device/pci_ids.h> |
| 31 | #include <device/pci_def.h> |
| 32 | #include <string.h> |
| 33 | #include <delay.h> |
| 34 | #include <elog.h> |
Patrick Georgi | 546953c | 2014-11-29 10:38:17 +0100 | [diff] [blame] | 35 | #include <halt.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 36 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 37 | #include "me.h" |
| 38 | #include "pch.h" |
| 39 | |
Martin Roth | 7a1a3ad | 2017-06-24 21:29:38 -0600 | [diff] [blame] | 40 | #if IS_ENABLED(CONFIG_CHROMEOS) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 41 | #include <vendorcode/google/chromeos/chromeos.h> |
| 42 | #include <vendorcode/google/chromeos/gnvs.h> |
| 43 | #endif |
| 44 | |
Duncan Laurie | af98062 | 2013-07-18 23:02:18 -0700 | [diff] [blame] | 45 | #ifndef __SMM__ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 46 | /* Path that the BIOS should take based on ME state */ |
| 47 | static const char *me_bios_path_values[] = { |
| 48 | [ME_NORMAL_BIOS_PATH] = "Normal", |
| 49 | [ME_S3WAKE_BIOS_PATH] = "S3 Wake", |
| 50 | [ME_ERROR_BIOS_PATH] = "Error", |
| 51 | [ME_RECOVERY_BIOS_PATH] = "Recovery", |
| 52 | [ME_DISABLE_BIOS_PATH] = "Disable", |
| 53 | [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", |
| 54 | }; |
Elyes HAOUAS | 1dcd8db | 2018-12-05 10:59:42 +0100 | [diff] [blame] | 55 | static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev); |
Duncan Laurie | af98062 | 2013-07-18 23:02:18 -0700 | [diff] [blame] | 56 | #endif |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 57 | |
| 58 | /* MMIO base address for MEI interface */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 59 | static u32 *mei_base_address; |
Elyes HAOUAS | 1dcd8db | 2018-12-05 10:59:42 +0100 | [diff] [blame] | 60 | #ifdef __SIMPLE_DEVICE__ |
| 61 | void intel_me_mbp_clear(pci_devfn_t dev); |
| 62 | #else |
| 63 | void intel_me_mbp_clear(struct device *dev); |
| 64 | #endif |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 65 | |
Martin Roth | 7a1a3ad | 2017-06-24 21:29:38 -0600 | [diff] [blame] | 66 | #if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 67 | static void mei_dump(void *ptr, int dword, int offset, const char *type) |
| 68 | { |
| 69 | struct mei_csr *csr; |
| 70 | |
| 71 | printk(BIOS_SPEW, "%-9s[%02x] : ", type, offset); |
| 72 | |
| 73 | switch (offset) { |
| 74 | case MEI_H_CSR: |
| 75 | case MEI_ME_CSR_HA: |
| 76 | csr = ptr; |
| 77 | if (!csr) { |
| 78 | printk(BIOS_SPEW, "ERROR: 0x%08x\n", dword); |
| 79 | break; |
| 80 | } |
| 81 | printk(BIOS_SPEW, "cbd=%u cbrp=%02u cbwp=%02u ready=%u " |
| 82 | "reset=%u ig=%u is=%u ie=%u\n", csr->buffer_depth, |
| 83 | csr->buffer_read_ptr, csr->buffer_write_ptr, |
| 84 | csr->ready, csr->reset, csr->interrupt_generate, |
| 85 | csr->interrupt_status, csr->interrupt_enable); |
| 86 | break; |
| 87 | case MEI_ME_CB_RW: |
| 88 | case MEI_H_CB_WW: |
| 89 | printk(BIOS_SPEW, "CB: 0x%08x\n", dword); |
| 90 | break; |
| 91 | default: |
| 92 | printk(BIOS_SPEW, "0x%08x\n", offset); |
| 93 | break; |
| 94 | } |
| 95 | } |
| 96 | #else |
| 97 | # define mei_dump(ptr,dword,offset,type) do {} while (0) |
| 98 | #endif |
| 99 | |
| 100 | /* |
| 101 | * ME/MEI access helpers using memcpy to avoid aliasing. |
| 102 | */ |
| 103 | |
| 104 | static inline void mei_read_dword_ptr(void *ptr, int offset) |
| 105 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 106 | u32 dword = read32(mei_base_address + (offset/sizeof(u32))); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 107 | memcpy(ptr, &dword, sizeof(dword)); |
| 108 | mei_dump(ptr, dword, offset, "READ"); |
| 109 | } |
| 110 | |
| 111 | static inline void mei_write_dword_ptr(void *ptr, int offset) |
| 112 | { |
| 113 | u32 dword = 0; |
| 114 | memcpy(&dword, ptr, sizeof(dword)); |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 115 | write32(mei_base_address + (offset/sizeof(u32)), dword); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 116 | mei_dump(ptr, dword, offset, "WRITE"); |
| 117 | } |
| 118 | |
Elyes HAOUAS | 1dcd8db | 2018-12-05 10:59:42 +0100 | [diff] [blame] | 119 | #ifdef __SIMPLE_DEVICE__ |
| 120 | static inline void pci_read_dword_ptr(pci_devfn_t dev, void *ptr, int offset) |
| 121 | #else |
| 122 | static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) |
| 123 | #endif |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 124 | { |
| 125 | u32 dword = pci_read_config32(dev, offset); |
| 126 | memcpy(ptr, &dword, sizeof(dword)); |
| 127 | mei_dump(ptr, dword, offset, "PCI READ"); |
| 128 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 129 | |
| 130 | static inline void read_host_csr(struct mei_csr *csr) |
| 131 | { |
| 132 | mei_read_dword_ptr(csr, MEI_H_CSR); |
| 133 | } |
| 134 | |
| 135 | static inline void write_host_csr(struct mei_csr *csr) |
| 136 | { |
| 137 | mei_write_dword_ptr(csr, MEI_H_CSR); |
| 138 | } |
| 139 | |
| 140 | static inline void read_me_csr(struct mei_csr *csr) |
| 141 | { |
| 142 | mei_read_dword_ptr(csr, MEI_ME_CSR_HA); |
| 143 | } |
| 144 | |
| 145 | static inline void write_cb(u32 dword) |
| 146 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 147 | write32(mei_base_address + (MEI_H_CB_WW/sizeof(u32)), dword); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 148 | mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE"); |
| 149 | } |
| 150 | |
| 151 | static inline u32 read_cb(void) |
| 152 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 153 | u32 dword = read32(mei_base_address + (MEI_ME_CB_RW/sizeof(u32))); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 154 | mei_dump(NULL, dword, MEI_ME_CB_RW, "READ"); |
| 155 | return dword; |
| 156 | } |
| 157 | |
| 158 | /* Wait for ME ready bit to be asserted */ |
| 159 | static int mei_wait_for_me_ready(void) |
| 160 | { |
| 161 | struct mei_csr me; |
| 162 | unsigned try = ME_RETRY; |
| 163 | |
| 164 | while (try--) { |
| 165 | read_me_csr(&me); |
| 166 | if (me.ready) |
| 167 | return 0; |
| 168 | udelay(ME_DELAY); |
| 169 | } |
| 170 | |
| 171 | printk(BIOS_ERR, "ME: failed to become ready\n"); |
| 172 | return -1; |
| 173 | } |
| 174 | |
| 175 | static void mei_reset(void) |
| 176 | { |
| 177 | struct mei_csr host; |
| 178 | |
| 179 | if (mei_wait_for_me_ready() < 0) |
| 180 | return; |
| 181 | |
| 182 | /* Reset host and ME circular buffers for next message */ |
| 183 | read_host_csr(&host); |
| 184 | host.reset = 1; |
| 185 | host.interrupt_generate = 1; |
| 186 | write_host_csr(&host); |
| 187 | |
| 188 | if (mei_wait_for_me_ready() < 0) |
| 189 | return; |
| 190 | |
| 191 | /* Re-init and indicate host is ready */ |
| 192 | read_host_csr(&host); |
| 193 | host.interrupt_generate = 1; |
| 194 | host.ready = 1; |
| 195 | host.reset = 0; |
| 196 | write_host_csr(&host); |
| 197 | } |
| 198 | |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 199 | static int mei_send_packet(struct mei_header *mei, void *req_data) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 200 | { |
| 201 | struct mei_csr host; |
| 202 | unsigned ndata, n; |
| 203 | u32 *data; |
| 204 | |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 205 | /* Number of dwords to write */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 206 | ndata = mei->length >> 2; |
| 207 | |
| 208 | /* Pad non-dword aligned request message length */ |
| 209 | if (mei->length & 3) |
| 210 | ndata++; |
| 211 | if (!ndata) { |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 212 | printk(BIOS_DEBUG, "ME: request has no data\n"); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 213 | return -1; |
| 214 | } |
| 215 | ndata++; /* Add MEI header */ |
| 216 | |
| 217 | /* |
| 218 | * Make sure there is still room left in the circular buffer. |
| 219 | * Reset the buffer pointers if the requested message will not fit. |
| 220 | */ |
| 221 | read_host_csr(&host); |
| 222 | if ((host.buffer_depth - host.buffer_write_ptr) < ndata) { |
| 223 | printk(BIOS_ERR, "ME: circular buffer full, resetting...\n"); |
| 224 | mei_reset(); |
| 225 | read_host_csr(&host); |
| 226 | } |
| 227 | |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 228 | /* Ensure the requested length will fit in the circular buffer. */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 229 | if ((host.buffer_depth - host.buffer_write_ptr) < ndata) { |
| 230 | printk(BIOS_ERR, "ME: message (%u) too large for buffer (%u)\n", |
| 231 | ndata + 2, host.buffer_depth); |
| 232 | return -1; |
| 233 | } |
| 234 | |
| 235 | /* Write MEI header */ |
| 236 | mei_write_dword_ptr(mei, MEI_H_CB_WW); |
| 237 | ndata--; |
| 238 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 239 | /* Write message data */ |
| 240 | data = req_data; |
| 241 | for (n = 0; n < ndata; ++n) |
| 242 | write_cb(*data++); |
| 243 | |
| 244 | /* Generate interrupt to the ME */ |
| 245 | read_host_csr(&host); |
| 246 | host.interrupt_generate = 1; |
| 247 | write_host_csr(&host); |
| 248 | |
| 249 | /* Make sure ME is ready after sending request data */ |
| 250 | return mei_wait_for_me_ready(); |
| 251 | } |
| 252 | |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 253 | static int mei_send_data(u8 me_address, u8 host_address, |
| 254 | void *req_data, int req_bytes) |
| 255 | { |
| 256 | struct mei_header header = { |
| 257 | .client_address = me_address, |
| 258 | .host_address = host_address, |
| 259 | }; |
| 260 | struct mei_csr host; |
| 261 | int current = 0; |
| 262 | u8 *req_ptr = req_data; |
| 263 | |
| 264 | while (!header.is_complete) { |
| 265 | int remain = req_bytes - current; |
| 266 | int buf_len; |
| 267 | |
| 268 | read_host_csr(&host); |
| 269 | buf_len = host.buffer_depth - host.buffer_write_ptr; |
| 270 | |
| 271 | if (buf_len > remain) { |
| 272 | /* Send all remaining data as final message */ |
| 273 | header.length = req_bytes - current; |
| 274 | header.is_complete = 1; |
| 275 | } else { |
| 276 | /* Send as much data as the buffer can hold */ |
| 277 | header.length = buf_len; |
| 278 | } |
| 279 | |
| 280 | mei_send_packet(&header, req_ptr); |
| 281 | |
| 282 | req_ptr += header.length; |
| 283 | current += header.length; |
| 284 | } |
| 285 | |
| 286 | return 0; |
| 287 | } |
| 288 | |
| 289 | static int mei_send_header(u8 me_address, u8 host_address, |
| 290 | void *header, int header_len, int complete) |
| 291 | { |
| 292 | struct mei_header mei = { |
| 293 | .client_address = me_address, |
| 294 | .host_address = host_address, |
| 295 | .length = header_len, |
| 296 | .is_complete = complete, |
| 297 | }; |
| 298 | return mei_send_packet(&mei, header); |
| 299 | } |
| 300 | |
| 301 | static int mei_recv_msg(void *header, int header_bytes, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 302 | void *rsp_data, int rsp_bytes) |
| 303 | { |
| 304 | struct mei_header mei_rsp; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 305 | struct mei_csr me, host; |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 306 | unsigned ndata, n; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 307 | unsigned expected; |
| 308 | u32 *data; |
| 309 | |
| 310 | /* Total number of dwords to read from circular buffer */ |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 311 | expected = (rsp_bytes + sizeof(mei_rsp) + header_bytes) >> 2; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 312 | if (rsp_bytes & 3) |
| 313 | expected++; |
| 314 | |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 315 | if (mei_wait_for_me_ready() < 0) |
| 316 | return -1; |
| 317 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 318 | /* |
| 319 | * The interrupt status bit does not appear to indicate that the |
| 320 | * message has actually been received. Instead we wait until the |
| 321 | * expected number of dwords are present in the circular buffer. |
| 322 | */ |
| 323 | for (n = ME_RETRY; n; --n) { |
| 324 | read_me_csr(&me); |
| 325 | if ((me.buffer_write_ptr - me.buffer_read_ptr) >= expected) |
| 326 | break; |
| 327 | udelay(ME_DELAY); |
| 328 | } |
| 329 | if (!n) { |
| 330 | printk(BIOS_ERR, "ME: timeout waiting for data: expected " |
| 331 | "%u, available %u\n", expected, |
| 332 | me.buffer_write_ptr - me.buffer_read_ptr); |
| 333 | return -1; |
| 334 | } |
| 335 | |
| 336 | /* Read and verify MEI response header from the ME */ |
| 337 | mei_read_dword_ptr(&mei_rsp, MEI_ME_CB_RW); |
| 338 | if (!mei_rsp.is_complete) { |
| 339 | printk(BIOS_ERR, "ME: response is not complete\n"); |
| 340 | return -1; |
| 341 | } |
| 342 | |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 343 | /* Handle non-dword responses and expect at least the header */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 344 | ndata = mei_rsp.length >> 2; |
| 345 | if (mei_rsp.length & 3) |
| 346 | ndata++; |
| 347 | if (ndata != (expected - 1)) { |
| 348 | printk(BIOS_ERR, "ME: response is missing data %d != %d\n", |
| 349 | ndata, (expected - 1)); |
| 350 | return -1; |
| 351 | } |
| 352 | |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 353 | /* Read response header from the ME */ |
| 354 | data = header; |
| 355 | for (n = 0; n < (header_bytes >> 2); ++n) |
| 356 | *data++ = read_cb(); |
| 357 | ndata -= header_bytes >> 2; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 358 | |
| 359 | /* Make sure caller passed a buffer with enough space */ |
| 360 | if (ndata != (rsp_bytes >> 2)) { |
| 361 | printk(BIOS_ERR, "ME: not enough room in response buffer: " |
| 362 | "%u != %u\n", ndata, rsp_bytes >> 2); |
| 363 | return -1; |
| 364 | } |
| 365 | |
| 366 | /* Read response data from the circular buffer */ |
| 367 | data = rsp_data; |
| 368 | for (n = 0; n < ndata; ++n) |
| 369 | *data++ = read_cb(); |
| 370 | |
| 371 | /* Tell the ME that we have consumed the response */ |
| 372 | read_host_csr(&host); |
| 373 | host.interrupt_status = 1; |
| 374 | host.interrupt_generate = 1; |
| 375 | write_host_csr(&host); |
| 376 | |
| 377 | return mei_wait_for_me_ready(); |
| 378 | } |
| 379 | |
Edward O'Callaghan | 97ccefd | 2015-01-07 15:53:00 +1100 | [diff] [blame] | 380 | #if IS_ENABLED (CONFIG_DEBUG_INTEL_ME) || defined(__SMM__) |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 381 | static inline int mei_sendrecv_mkhi(struct mkhi_header *mkhi, |
| 382 | void *req_data, int req_bytes, |
| 383 | void *rsp_data, int rsp_bytes) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 384 | { |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 385 | struct mkhi_header mkhi_rsp; |
| 386 | |
| 387 | /* Send header */ |
| 388 | if (mei_send_header(MEI_ADDRESS_MKHI, MEI_HOST_ADDRESS, |
| 389 | mkhi, sizeof(*mkhi), req_bytes ? 0 : 1) < 0) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 390 | return -1; |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 391 | |
| 392 | /* Send data if available */ |
| 393 | if (req_bytes && mei_send_data(MEI_ADDRESS_MKHI, MEI_HOST_ADDRESS, |
| 394 | req_data, req_bytes) < 0) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 395 | return -1; |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 396 | |
| 397 | /* Return now if no response expected */ |
| 398 | if (!rsp_bytes) |
| 399 | return 0; |
| 400 | |
| 401 | /* Read header and data */ |
| 402 | if (mei_recv_msg(&mkhi_rsp, sizeof(mkhi_rsp), |
| 403 | rsp_data, rsp_bytes) < 0) |
| 404 | return -1; |
| 405 | |
| 406 | if (!mkhi_rsp.is_response || |
| 407 | mkhi->group_id != mkhi_rsp.group_id || |
| 408 | mkhi->command != mkhi_rsp.command) { |
| 409 | printk(BIOS_ERR, "ME: invalid response, group %u ?= %u," |
| 410 | "command %u ?= %u, is_response %u\n", mkhi->group_id, |
| 411 | mkhi_rsp.group_id, mkhi->command, mkhi_rsp.command, |
| 412 | mkhi_rsp.is_response); |
| 413 | return -1; |
| 414 | } |
| 415 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 416 | return 0; |
| 417 | } |
Edward O'Callaghan | 97ccefd | 2015-01-07 15:53:00 +1100 | [diff] [blame] | 418 | #endif /* CONFIG_DEBUG_INTEL_ME || __SMM__ */ |
Duncan Laurie | 0dc0d13 | 2013-08-08 15:31:51 -0700 | [diff] [blame] | 419 | |
Duncan Laurie | 3d299c4 | 2013-07-19 08:48:05 -0700 | [diff] [blame] | 420 | /* |
| 421 | * mbp give up routine. This path is taken if hfs.mpb_rdy is 0 or the read |
| 422 | * state machine on the BIOS end doesn't match the ME's state machine. |
| 423 | */ |
Elyes HAOUAS | 1dcd8db | 2018-12-05 10:59:42 +0100 | [diff] [blame] | 424 | #ifdef __SIMPLE_DEVICE__ |
| 425 | static void intel_me_mbp_give_up(pci_devfn_t dev) |
| 426 | #else |
| 427 | static void intel_me_mbp_give_up(struct device *dev) |
| 428 | #endif |
Duncan Laurie | 3d299c4 | 2013-07-19 08:48:05 -0700 | [diff] [blame] | 429 | { |
| 430 | struct mei_csr csr; |
| 431 | |
| 432 | pci_write_config32(dev, PCI_ME_H_GS2, PCI_ME_MBP_GIVE_UP); |
| 433 | |
| 434 | read_host_csr(&csr); |
| 435 | csr.reset = 1; |
| 436 | csr.interrupt_generate = 1; |
| 437 | write_host_csr(&csr); |
| 438 | } |
| 439 | |
| 440 | /* |
| 441 | * mbp clear routine. This will wait for the ME to indicate that |
| 442 | * the MBP has been read and cleared. |
| 443 | */ |
Elyes HAOUAS | 1dcd8db | 2018-12-05 10:59:42 +0100 | [diff] [blame] | 444 | #ifdef __SIMPLE_DEVICE__ |
| 445 | void intel_me_mbp_clear(pci_devfn_t dev) |
| 446 | #else |
| 447 | void intel_me_mbp_clear(struct device *dev) |
| 448 | #endif |
Duncan Laurie | 3d299c4 | 2013-07-19 08:48:05 -0700 | [diff] [blame] | 449 | { |
| 450 | int count; |
| 451 | struct me_hfs2 hfs2; |
| 452 | |
| 453 | /* Wait for the mbp_cleared indicator */ |
| 454 | for (count = ME_RETRY; count > 0; --count) { |
| 455 | pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2); |
| 456 | if (hfs2.mbp_cleared) |
| 457 | break; |
| 458 | udelay(ME_DELAY); |
| 459 | } |
| 460 | |
| 461 | if (count == 0) { |
| 462 | printk(BIOS_WARNING, "ME: Timeout waiting for mbp_cleared\n"); |
| 463 | intel_me_mbp_give_up(dev); |
| 464 | } else { |
| 465 | printk(BIOS_INFO, "ME: MBP cleared\n"); |
| 466 | } |
| 467 | } |
| 468 | |
Duncan Laurie | af98062 | 2013-07-18 23:02:18 -0700 | [diff] [blame] | 469 | #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) && !defined(__SMM__) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 470 | static void me_print_fw_version(mbp_fw_version_name *vers_name) |
| 471 | { |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 472 | if (!vers_name) { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 473 | printk(BIOS_ERR, "ME: mbp missing version report\n"); |
| 474 | return; |
| 475 | } |
| 476 | |
| 477 | printk(BIOS_DEBUG, "ME: found version %d.%d.%d.%d\n", |
| 478 | vers_name->major_version, vers_name->minor_version, |
| 479 | vers_name->hotfix_version, vers_name->build_version); |
| 480 | } |
| 481 | |
Edward O'Callaghan | 7bf4f48 | 2014-06-17 15:12:09 +1000 | [diff] [blame] | 482 | #if IS_ENABLED (CONFIG_DEBUG_INTEL_ME) |
| 483 | static inline void print_cap(const char *name, int state) |
| 484 | { |
| 485 | printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", |
| 486 | name, state ? " en" : "dis"); |
| 487 | } |
| 488 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 489 | /* Get ME Firmware Capabilities */ |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 490 | static int mkhi_get_fwcaps(mbp_mefwcaps *cap) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 491 | { |
| 492 | u32 rule_id = 0; |
| 493 | struct me_fwcaps cap_msg; |
| 494 | struct mkhi_header mkhi = { |
| 495 | .group_id = MKHI_GROUP_ID_FWCAPS, |
| 496 | .command = MKHI_FWCAPS_GET_RULE, |
| 497 | }; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 498 | |
| 499 | /* Send request and wait for response */ |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 500 | if (mei_sendrecv_mkhi(&mkhi, &rule_id, sizeof(u32), |
| 501 | &cap_msg, sizeof(cap_msg)) < 0) { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 502 | printk(BIOS_ERR, "ME: GET FWCAPS message failed\n"); |
| 503 | return -1; |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 504 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 505 | *cap = cap_msg.caps_sku; |
| 506 | return 0; |
| 507 | } |
| 508 | |
| 509 | /* Get ME Firmware Capabilities */ |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 510 | static void me_print_fwcaps(mbp_mefwcaps *cap) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 511 | { |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 512 | mbp_mefwcaps local_caps; |
| 513 | if (!cap) { |
| 514 | cap = &local_caps; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 515 | printk(BIOS_ERR, "ME: mbp missing fwcaps report\n"); |
| 516 | if (mkhi_get_fwcaps(cap)) |
| 517 | return; |
| 518 | } |
| 519 | |
| 520 | print_cap("Full Network manageability", cap->full_net); |
| 521 | print_cap("Regular Network manageability", cap->std_net); |
| 522 | print_cap("Manageability", cap->manageability); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 523 | print_cap("IntelR Anti-Theft (AT)", cap->intel_at); |
| 524 | print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls); |
| 525 | print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc); |
| 526 | print_cap("ICC Over Clocking", cap->icc_over_clocking); |
Edward O'Callaghan | 7bf4f48 | 2014-06-17 15:12:09 +1000 | [diff] [blame] | 527 | print_cap("Protected Audio Video Path (PAVP)", cap->pavp); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 528 | print_cap("IPV6", cap->ipv6); |
| 529 | print_cap("KVM Remote Control (KVM)", cap->kvm); |
| 530 | print_cap("Outbreak Containment Heuristic (OCH)", cap->och); |
| 531 | print_cap("Virtual LAN (VLAN)", cap->vlan); |
| 532 | print_cap("TLS", cap->tls); |
| 533 | print_cap("Wireless LAN (WLAN)", cap->wlan); |
| 534 | } |
Edward O'Callaghan | 7bf4f48 | 2014-06-17 15:12:09 +1000 | [diff] [blame] | 535 | #endif /* CONFIG_DEBUG_INTEL_ME */ |
Duncan Laurie | 0b3cd36 | 2013-08-08 15:40:01 -0700 | [diff] [blame] | 536 | #endif |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 537 | |
Martin Roth | 7a1a3ad | 2017-06-24 21:29:38 -0600 | [diff] [blame] | 538 | #if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 539 | /* Tell ME to issue a global reset */ |
| 540 | static int mkhi_global_reset(void) |
| 541 | { |
| 542 | struct me_global_reset reset = { |
| 543 | .request_origin = GLOBAL_RESET_BIOS_POST, |
| 544 | .reset_type = CBM_RR_GLOBAL_RESET, |
| 545 | }; |
| 546 | struct mkhi_header mkhi = { |
| 547 | .group_id = MKHI_GROUP_ID_CBM, |
| 548 | .command = MKHI_GLOBAL_RESET, |
| 549 | }; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 550 | |
| 551 | /* Send request and wait for response */ |
| 552 | printk(BIOS_NOTICE, "ME: %s\n", __FUNCTION__); |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 553 | if (mei_sendrecv_mkhi(&mkhi, &reset, sizeof(reset), NULL, 0) < 0) { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 554 | /* No response means reset will happen shortly... */ |
Patrick Georgi | 546953c | 2014-11-29 10:38:17 +0100 | [diff] [blame] | 555 | halt(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 556 | } |
| 557 | |
| 558 | /* If the ME responded it rejected the reset request */ |
| 559 | printk(BIOS_ERR, "ME: Global Reset failed\n"); |
| 560 | return -1; |
| 561 | } |
| 562 | #endif |
| 563 | |
Duncan Laurie | af98062 | 2013-07-18 23:02:18 -0700 | [diff] [blame] | 564 | #ifdef __SMM__ |
| 565 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 566 | /* Send END OF POST message to the ME */ |
| 567 | static int mkhi_end_of_post(void) |
| 568 | { |
| 569 | struct mkhi_header mkhi = { |
| 570 | .group_id = MKHI_GROUP_ID_GEN, |
| 571 | .command = MKHI_END_OF_POST, |
| 572 | }; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 573 | u32 eop_ack; |
| 574 | |
| 575 | /* Send request and wait for response */ |
| 576 | printk(BIOS_NOTICE, "ME: %s\n", __FUNCTION__); |
Duncan Laurie | 2017b4a | 2013-08-08 15:07:12 -0700 | [diff] [blame] | 577 | if (mei_sendrecv_mkhi(&mkhi, NULL, 0, &eop_ack, sizeof(eop_ack)) < 0) { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 578 | printk(BIOS_ERR, "ME: END OF POST message failed\n"); |
| 579 | return -1; |
| 580 | } |
| 581 | |
| 582 | printk(BIOS_INFO, "ME: END OF POST message successful (%d)\n", eop_ack); |
| 583 | return 0; |
| 584 | } |
| 585 | |
Duncan Laurie | af98062 | 2013-07-18 23:02:18 -0700 | [diff] [blame] | 586 | void intel_me_finalize_smm(void) |
| 587 | { |
| 588 | struct me_hfs hfs; |
| 589 | u32 reg32; |
| 590 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 591 | mei_base_address = (u32 *) |
| 592 | (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); |
Duncan Laurie | af98062 | 2013-07-18 23:02:18 -0700 | [diff] [blame] | 593 | |
| 594 | /* S3 path will have hidden this device already */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 595 | if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0) |
Duncan Laurie | af98062 | 2013-07-18 23:02:18 -0700 | [diff] [blame] | 596 | return; |
| 597 | |
Martin Roth | 7a1a3ad | 2017-06-24 21:29:38 -0600 | [diff] [blame] | 598 | #if IS_ENABLED(CONFIG_ME_MBP_CLEAR_LATE) |
Duncan Laurie | 3d299c4 | 2013-07-19 08:48:05 -0700 | [diff] [blame] | 599 | /* Wait for ME MBP Cleared indicator */ |
| 600 | intel_me_mbp_clear(PCH_ME_DEV); |
| 601 | #endif |
| 602 | |
Duncan Laurie | af98062 | 2013-07-18 23:02:18 -0700 | [diff] [blame] | 603 | /* Make sure ME is in a mode that expects EOP */ |
| 604 | reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS); |
| 605 | memcpy(&hfs, ®32, sizeof(u32)); |
| 606 | |
| 607 | /* Abort and leave device alone if not normal mode */ |
| 608 | if (hfs.fpt_bad || |
| 609 | hfs.working_state != ME_HFS_CWS_NORMAL || |
| 610 | hfs.operation_mode != ME_HFS_MODE_NORMAL) |
| 611 | return; |
| 612 | |
| 613 | /* Try to send EOP command so ME stops accepting other commands */ |
| 614 | mkhi_end_of_post(); |
| 615 | |
| 616 | /* Make sure IO is disabled */ |
| 617 | reg32 = pci_read_config32(PCH_ME_DEV, PCI_COMMAND); |
| 618 | reg32 &= ~(PCI_COMMAND_MASTER | |
| 619 | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
| 620 | pci_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32); |
| 621 | |
| 622 | /* Hide the PCI device */ |
| 623 | RCBA32_OR(FD2, PCH_DISABLE_MEI1); |
| 624 | } |
| 625 | |
| 626 | #else /* !__SMM__ */ |
| 627 | |
Edward O'Callaghan | 97ccefd | 2015-01-07 15:53:00 +1100 | [diff] [blame] | 628 | static inline int mei_sendrecv_icc(struct icc_header *icc, |
| 629 | void *req_data, int req_bytes, |
| 630 | void *rsp_data, int rsp_bytes) |
| 631 | { |
| 632 | struct icc_header icc_rsp; |
| 633 | |
| 634 | /* Send header */ |
| 635 | if (mei_send_header(MEI_ADDRESS_ICC, MEI_HOST_ADDRESS, |
| 636 | icc, sizeof(*icc), req_bytes ? 0 : 1) < 0) |
| 637 | return -1; |
| 638 | |
| 639 | /* Send data if available */ |
| 640 | if (req_bytes && mei_send_data(MEI_ADDRESS_ICC, MEI_HOST_ADDRESS, |
| 641 | req_data, req_bytes) < 0) |
| 642 | return -1; |
| 643 | |
| 644 | /* Read header and data, if needed */ |
| 645 | if (rsp_bytes && mei_recv_msg(&icc_rsp, sizeof(icc_rsp), |
| 646 | rsp_data, rsp_bytes) < 0) |
| 647 | return -1; |
| 648 | |
| 649 | return 0; |
| 650 | } |
| 651 | |
Duncan Laurie | 0dc0d13 | 2013-08-08 15:31:51 -0700 | [diff] [blame] | 652 | static int me_icc_set_clock_enables(u32 mask) |
| 653 | { |
| 654 | struct icc_clock_enables_msg clk = { |
| 655 | .clock_enables = 0, /* Turn off specified clocks */ |
| 656 | .clock_mask = mask, |
| 657 | .no_response = 1, /* Do not expect response */ |
| 658 | }; |
| 659 | struct icc_header icc = { |
| 660 | .api_version = ICC_API_VERSION_LYNXPOINT, |
| 661 | .icc_command = ICC_SET_CLOCK_ENABLES, |
| 662 | .length = sizeof(clk), |
| 663 | }; |
| 664 | |
| 665 | /* Send request and wait for response */ |
| 666 | if (mei_sendrecv_icc(&icc, &clk, sizeof(clk), NULL, 0) < 0) { |
| 667 | printk(BIOS_ERR, "ME: ICC SET CLOCK ENABLES message failed\n"); |
| 668 | return -1; |
Duncan Laurie | 0dc0d13 | 2013-08-08 15:31:51 -0700 | [diff] [blame] | 669 | } |
| 670 | |
Elyes HAOUAS | 54f9424 | 2018-10-25 10:57:39 +0200 | [diff] [blame] | 671 | printk(BIOS_INFO, "ME: ICC SET CLOCK ENABLES 0x%08x\n", mask); |
Duncan Laurie | 0dc0d13 | 2013-08-08 15:31:51 -0700 | [diff] [blame] | 672 | return 0; |
| 673 | } |
| 674 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 675 | /* Determine the path that we should take based on ME status */ |
Elyes HAOUAS | 1dcd8db | 2018-12-05 10:59:42 +0100 | [diff] [blame] | 676 | static me_bios_path intel_me_path(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 677 | { |
| 678 | me_bios_path path = ME_DISABLE_BIOS_PATH; |
| 679 | struct me_hfs hfs; |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 680 | struct me_hfs2 hfs2; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 681 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 682 | pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS); |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 683 | pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 684 | |
| 685 | /* Check and dump status */ |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 686 | intel_me_status(&hfs, &hfs2); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 687 | |
| 688 | /* Check Current Working State */ |
| 689 | switch (hfs.working_state) { |
| 690 | case ME_HFS_CWS_NORMAL: |
| 691 | path = ME_NORMAL_BIOS_PATH; |
| 692 | break; |
| 693 | case ME_HFS_CWS_REC: |
| 694 | path = ME_RECOVERY_BIOS_PATH; |
| 695 | break; |
| 696 | default: |
| 697 | path = ME_DISABLE_BIOS_PATH; |
| 698 | break; |
| 699 | } |
| 700 | |
| 701 | /* Check Current Operation Mode */ |
| 702 | switch (hfs.operation_mode) { |
| 703 | case ME_HFS_MODE_NORMAL: |
| 704 | break; |
| 705 | case ME_HFS_MODE_DEBUG: |
| 706 | case ME_HFS_MODE_DIS: |
| 707 | case ME_HFS_MODE_OVER_JMPR: |
| 708 | case ME_HFS_MODE_OVER_MEI: |
| 709 | default: |
| 710 | path = ME_DISABLE_BIOS_PATH; |
| 711 | break; |
| 712 | } |
| 713 | |
| 714 | /* Check for any error code and valid firmware and MBP */ |
| 715 | if (hfs.error_code || hfs.fpt_bad) |
| 716 | path = ME_ERROR_BIOS_PATH; |
| 717 | |
| 718 | /* Check if the MBP is ready */ |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 719 | if (!hfs2.mbp_rdy) { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 720 | printk(BIOS_CRIT, "%s: mbp is not ready!\n", |
| 721 | __FUNCTION__); |
| 722 | path = ME_ERROR_BIOS_PATH; |
| 723 | } |
| 724 | |
Martin Roth | 7a1a3ad | 2017-06-24 21:29:38 -0600 | [diff] [blame] | 725 | #if IS_ENABLED(CONFIG_ELOG) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 726 | if (path != ME_NORMAL_BIOS_PATH) { |
| 727 | struct elog_event_data_me_extended data = { |
| 728 | .current_working_state = hfs.working_state, |
| 729 | .operation_state = hfs.operation_state, |
| 730 | .operation_mode = hfs.operation_mode, |
| 731 | .error_code = hfs.error_code, |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 732 | .progress_code = hfs2.progress_code, |
| 733 | .current_pmevent = hfs2.current_pmevent, |
| 734 | .current_state = hfs2.current_state, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 735 | }; |
| 736 | elog_add_event_byte(ELOG_TYPE_MANAGEMENT_ENGINE, path); |
| 737 | elog_add_event_raw(ELOG_TYPE_MANAGEMENT_ENGINE_EXT, |
| 738 | &data, sizeof(data)); |
| 739 | } |
| 740 | #endif |
| 741 | |
| 742 | return path; |
| 743 | } |
| 744 | |
| 745 | /* Prepare ME for MEI messages */ |
Elyes HAOUAS | 1dcd8db | 2018-12-05 10:59:42 +0100 | [diff] [blame] | 746 | static int intel_mei_setup(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 747 | { |
| 748 | struct resource *res; |
| 749 | struct mei_csr host; |
| 750 | u32 reg32; |
| 751 | |
| 752 | /* Find the MMIO base for the ME interface */ |
| 753 | res = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 754 | if (!res || res->base == 0 || res->size == 0) { |
| 755 | printk(BIOS_DEBUG, "ME: MEI resource not present!\n"); |
| 756 | return -1; |
| 757 | } |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 758 | mei_base_address = (u32 *)(uintptr_t)res->base; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 759 | |
| 760 | /* Ensure Memory and Bus Master bits are set */ |
| 761 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 762 | reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; |
| 763 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 764 | |
| 765 | /* Clean up status for next message */ |
| 766 | read_host_csr(&host); |
| 767 | host.interrupt_generate = 1; |
| 768 | host.ready = 1; |
| 769 | host.reset = 0; |
| 770 | write_host_csr(&host); |
| 771 | |
| 772 | return 0; |
| 773 | } |
| 774 | |
| 775 | /* Read the Extend register hash of ME firmware */ |
Elyes HAOUAS | 1dcd8db | 2018-12-05 10:59:42 +0100 | [diff] [blame] | 776 | static int intel_me_extend_valid(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 777 | { |
| 778 | struct me_heres status; |
| 779 | u32 extend[8] = {0}; |
| 780 | int i, count = 0; |
| 781 | |
| 782 | pci_read_dword_ptr(dev, &status, PCI_ME_HERES); |
| 783 | if (!status.extend_feature_present) { |
| 784 | printk(BIOS_ERR, "ME: Extend Feature not present\n"); |
| 785 | return -1; |
| 786 | } |
| 787 | |
| 788 | if (!status.extend_reg_valid) { |
| 789 | printk(BIOS_ERR, "ME: Extend Register not valid\n"); |
| 790 | return -1; |
| 791 | } |
| 792 | |
| 793 | switch (status.extend_reg_algorithm) { |
| 794 | case PCI_ME_EXT_SHA1: |
| 795 | count = 5; |
| 796 | printk(BIOS_DEBUG, "ME: Extend SHA-1: "); |
| 797 | break; |
| 798 | case PCI_ME_EXT_SHA256: |
| 799 | count = 8; |
| 800 | printk(BIOS_DEBUG, "ME: Extend SHA-256: "); |
| 801 | break; |
| 802 | default: |
| 803 | printk(BIOS_ERR, "ME: Extend Algorithm %d unknown\n", |
| 804 | status.extend_reg_algorithm); |
| 805 | return -1; |
| 806 | } |
| 807 | |
| 808 | for (i = 0; i < count; ++i) { |
| 809 | extend[i] = pci_read_config32(dev, PCI_ME_HER(i)); |
| 810 | printk(BIOS_DEBUG, "%08x", extend[i]); |
| 811 | } |
| 812 | printk(BIOS_DEBUG, "\n"); |
| 813 | |
Martin Roth | 7a1a3ad | 2017-06-24 21:29:38 -0600 | [diff] [blame] | 814 | #if IS_ENABLED(CONFIG_CHROMEOS) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 815 | /* Save hash in NVS for the OS to verify */ |
| 816 | chromeos_set_me_hash(extend, count); |
| 817 | #endif |
| 818 | |
| 819 | return 0; |
| 820 | } |
| 821 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 822 | /* Check whether ME is present and do basic init */ |
Elyes HAOUAS | 1dcd8db | 2018-12-05 10:59:42 +0100 | [diff] [blame] | 823 | static void intel_me_init(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 824 | { |
Duncan Laurie | 0dc0d13 | 2013-08-08 15:31:51 -0700 | [diff] [blame] | 825 | struct southbridge_intel_lynxpoint_config *config = dev->chip_info; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 826 | me_bios_path path = intel_me_path(dev); |
| 827 | me_bios_payload mbp_data; |
| 828 | |
| 829 | /* Do initial setup and determine the BIOS path */ |
| 830 | printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_bios_path_values[path]); |
| 831 | |
Duncan Laurie | 8056dc6 | 2013-07-22 08:47:43 -0700 | [diff] [blame] | 832 | if (path == ME_NORMAL_BIOS_PATH) { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 833 | /* Validate the extend register */ |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 834 | intel_me_extend_valid(dev); |
| 835 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 836 | |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 837 | memset(&mbp_data, 0, sizeof(mbp_data)); |
| 838 | |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 839 | /* |
| 840 | * According to the ME9 BWG, BIOS is required to fetch MBP data in |
| 841 | * all boot flows except S3 Resume. |
| 842 | */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 843 | |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 844 | /* Prepare MEI MMIO interface */ |
| 845 | if (intel_mei_setup(dev) < 0) |
| 846 | return; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 847 | |
Duncan Laurie | 144f7b2 | 2013-05-01 11:27:58 -0700 | [diff] [blame] | 848 | if (intel_me_read_mbp(&mbp_data, dev)) |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 849 | return; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 850 | |
| 851 | #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 852 | me_print_fw_version(mbp_data.fw_version_name); |
Martin Roth | 7a1a3ad | 2017-06-24 21:29:38 -0600 | [diff] [blame] | 853 | #if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 854 | me_print_fwcaps(mbp_data.fw_capabilities); |
Duncan Laurie | 0b3cd36 | 2013-08-08 15:40:01 -0700 | [diff] [blame] | 855 | #endif |
Duncan Laurie | 144f7b2 | 2013-05-01 11:27:58 -0700 | [diff] [blame] | 856 | |
| 857 | if (mbp_data.plat_time) { |
| 858 | printk(BIOS_DEBUG, "ME: Wake Event to ME Reset: %u ms\n", |
| 859 | mbp_data.plat_time->wake_event_mrst_time_ms); |
| 860 | printk(BIOS_DEBUG, "ME: ME Reset to Platform Reset: %u ms\n", |
| 861 | mbp_data.plat_time->mrst_pltrst_time_ms); |
| 862 | printk(BIOS_DEBUG, "ME: Platform Reset to CPU Reset: %u ms\n", |
| 863 | mbp_data.plat_time->pltrst_cpurst_time_ms); |
| 864 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 865 | #endif |
| 866 | |
Duncan Laurie | 0dc0d13 | 2013-08-08 15:31:51 -0700 | [diff] [blame] | 867 | /* Set clock enables according to devicetree */ |
| 868 | if (config && config->icc_clock_disable) |
| 869 | me_icc_set_clock_enables(config->icc_clock_disable); |
| 870 | |
Duncan Laurie | af98062 | 2013-07-18 23:02:18 -0700 | [diff] [blame] | 871 | /* |
| 872 | * Leave the ME unlocked. It will be locked via SMI command later. |
| 873 | */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 874 | } |
| 875 | |
Elyes HAOUAS | 1dcd8db | 2018-12-05 10:59:42 +0100 | [diff] [blame] | 876 | static void set_subsystem(struct device *dev, unsigned int vendor, |
| 877 | unsigned int device) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 878 | { |
| 879 | if (!vendor || !device) { |
| 880 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 881 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 882 | } else { |
| 883 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 884 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 885 | } |
| 886 | } |
| 887 | |
| 888 | static struct pci_operations pci_ops = { |
| 889 | .set_subsystem = set_subsystem, |
| 890 | }; |
| 891 | |
Elyes HAOUAS | 1dcd8db | 2018-12-05 10:59:42 +0100 | [diff] [blame] | 892 | static void intel_me_enable(struct device *dev) |
Duncan Laurie | 8056dc6 | 2013-07-22 08:47:43 -0700 | [diff] [blame] | 893 | { |
Duncan Laurie | 8056dc6 | 2013-07-22 08:47:43 -0700 | [diff] [blame] | 894 | /* Avoid talking to the device in S3 path */ |
Kyösti Mälkki | c3ed886 | 2014-06-19 19:50:51 +0300 | [diff] [blame] | 895 | if (acpi_is_wakeup_s3()) { |
Duncan Laurie | 8056dc6 | 2013-07-22 08:47:43 -0700 | [diff] [blame] | 896 | dev->enabled = 0; |
| 897 | pch_disable_devfn(dev); |
| 898 | } |
Duncan Laurie | 8056dc6 | 2013-07-22 08:47:43 -0700 | [diff] [blame] | 899 | } |
| 900 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 901 | static struct device_operations device_ops = { |
| 902 | .read_resources = pci_dev_read_resources, |
| 903 | .set_resources = pci_dev_set_resources, |
| 904 | .enable_resources = pci_dev_enable_resources, |
Duncan Laurie | 8056dc6 | 2013-07-22 08:47:43 -0700 | [diff] [blame] | 905 | .enable = intel_me_enable, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 906 | .init = intel_me_init, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 907 | .ops_pci = &pci_ops, |
| 908 | }; |
| 909 | |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 910 | static const unsigned short pci_device_ids[] = { |
| 911 | 0x8c3a, /* Mobile */ |
| 912 | 0x9c3a, /* Low Power */ |
| 913 | 0 |
| 914 | }; |
| 915 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 916 | static const struct pci_driver intel_me __pci_driver = { |
| 917 | .ops = &device_ops, |
| 918 | .vendor = PCI_VENDOR_ID_INTEL, |
Duncan Laurie | 26e7dd7 | 2012-12-19 09:12:31 -0800 | [diff] [blame] | 919 | .devices= pci_device_ids, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 920 | }; |
| 921 | |
| 922 | /****************************************************************************** |
| 923 | * */ |
| 924 | static u32 me_to_host_words_pending(void) |
| 925 | { |
| 926 | struct mei_csr me; |
| 927 | read_me_csr(&me); |
| 928 | if (!me.ready) |
| 929 | return 0; |
| 930 | return (me.buffer_write_ptr - me.buffer_read_ptr) & |
| 931 | (me.buffer_depth - 1); |
| 932 | } |
| 933 | |
| 934 | #if 0 |
| 935 | /* This function is not yet being used, keep it in for the future. */ |
| 936 | static u32 host_to_me_words_room(void) |
| 937 | { |
| 938 | struct mei_csr csr; |
| 939 | |
| 940 | read_me_csr(&csr); |
| 941 | if (!csr.ready) |
| 942 | return 0; |
| 943 | |
| 944 | read_host_csr(&csr); |
| 945 | return (csr.buffer_read_ptr - csr.buffer_write_ptr - 1) & |
| 946 | (csr.buffer_depth - 1); |
| 947 | } |
| 948 | #endif |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 949 | |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 950 | struct mbp_payload { |
| 951 | mbp_header header; |
| 952 | u32 data[0]; |
| 953 | }; |
| 954 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 955 | /* |
| 956 | * mbp seems to be following its own flow, let's retrieve it in a dedicated |
| 957 | * function. |
| 958 | */ |
Elyes HAOUAS | 1dcd8db | 2018-12-05 10:59:42 +0100 | [diff] [blame] | 959 | static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 960 | { |
| 961 | mbp_header mbp_hdr; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 962 | u32 me2host_pending; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 963 | struct mei_csr host; |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 964 | struct me_hfs2 hfs2; |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 965 | struct mbp_payload *mbp; |
| 966 | int i; |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 967 | |
| 968 | pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2); |
| 969 | |
| 970 | if (!hfs2.mbp_rdy) { |
| 971 | printk(BIOS_ERR, "ME: MBP not ready\n"); |
| 972 | goto mbp_failure; |
| 973 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 974 | |
| 975 | me2host_pending = me_to_host_words_pending(); |
| 976 | if (!me2host_pending) { |
| 977 | printk(BIOS_ERR, "ME: no mbp data!\n"); |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 978 | goto mbp_failure; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 979 | } |
| 980 | |
| 981 | /* we know for sure that at least the header is there */ |
| 982 | mei_read_dword_ptr(&mbp_hdr, MEI_ME_CB_RW); |
| 983 | |
| 984 | if ((mbp_hdr.num_entries > (mbp_hdr.mbp_size / 2)) || |
| 985 | (me2host_pending < mbp_hdr.mbp_size)) { |
| 986 | printk(BIOS_ERR, "ME: mbp of %d entries, total size %d words" |
| 987 | " buffer contains %d words\n", |
| 988 | mbp_hdr.num_entries, mbp_hdr.mbp_size, |
| 989 | me2host_pending); |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 990 | goto mbp_failure; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 991 | } |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 992 | mbp = malloc(mbp_hdr.mbp_size * sizeof(u32)); |
| 993 | if (!mbp) |
| 994 | goto mbp_failure; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 995 | |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 996 | mbp->header = mbp_hdr; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 997 | me2host_pending--; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 998 | |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 999 | i = 0; |
| 1000 | while (i != me2host_pending) { |
| 1001 | mei_read_dword_ptr(&mbp->data[i], MEI_ME_CB_RW); |
| 1002 | i++; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1003 | } |
| 1004 | |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 1005 | /* Signal to the ME that the host has finished reading the MBP. */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1006 | read_host_csr(&host); |
| 1007 | host.interrupt_generate = 1; |
| 1008 | write_host_csr(&host); |
| 1009 | |
Martin Roth | 7a1a3ad | 2017-06-24 21:29:38 -0600 | [diff] [blame] | 1010 | #if !IS_ENABLED(CONFIG_ME_MBP_CLEAR_LATE) |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 1011 | /* Wait for the mbp_cleared indicator. */ |
Duncan Laurie | 3d299c4 | 2013-07-19 08:48:05 -0700 | [diff] [blame] | 1012 | intel_me_mbp_clear(dev); |
| 1013 | #endif |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1014 | |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 1015 | /* Dump out the MBP contents. */ |
| 1016 | #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) |
| 1017 | printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n", |
| 1018 | mbp->header.num_entries, mbp->header.mbp_size); |
Martin Roth | 7a1a3ad | 2017-06-24 21:29:38 -0600 | [diff] [blame] | 1019 | #if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 1020 | for (i = 0; i < mbp->header.mbp_size - 1; i++) { |
| 1021 | printk(BIOS_INFO, "ME MBP: %04x: 0x%08x\n", i, mbp->data[i]); |
| 1022 | } |
| 1023 | #endif |
Duncan Laurie | 0b3cd36 | 2013-08-08 15:40:01 -0700 | [diff] [blame] | 1024 | #endif |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 1025 | |
| 1026 | #define ASSIGN_FIELD_PTR(field_,val_) \ |
| 1027 | { \ |
| 1028 | mbp_data->field_ = (typeof(mbp_data->field_))(void *)val_; \ |
| 1029 | break; \ |
| 1030 | } |
| 1031 | /* Setup the pointers in the me_bios_payload structure. */ |
| 1032 | for (i = 0; i < mbp->header.mbp_size - 1;) { |
| 1033 | mbp_item_header *item = (void *)&mbp->data[i]; |
| 1034 | |
Elyes HAOUAS | f9de5a4 | 2018-05-03 17:21:02 +0200 | [diff] [blame] | 1035 | switch (MBP_MAKE_IDENT(item->app_id, item->item_id)) { |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 1036 | case MBP_IDENT(KERNEL, FW_VER): |
| 1037 | ASSIGN_FIELD_PTR(fw_version_name, &mbp->data[i+1]); |
| 1038 | |
| 1039 | case MBP_IDENT(ICC, PROFILE): |
| 1040 | ASSIGN_FIELD_PTR(icc_profile, &mbp->data[i+1]); |
| 1041 | |
| 1042 | case MBP_IDENT(INTEL_AT, STATE): |
| 1043 | ASSIGN_FIELD_PTR(at_state, &mbp->data[i+1]); |
| 1044 | |
| 1045 | case MBP_IDENT(KERNEL, FW_CAP): |
| 1046 | ASSIGN_FIELD_PTR(fw_capabilities, &mbp->data[i+1]); |
| 1047 | |
| 1048 | case MBP_IDENT(KERNEL, ROM_BIST): |
| 1049 | ASSIGN_FIELD_PTR(rom_bist_data, &mbp->data[i+1]); |
| 1050 | |
| 1051 | case MBP_IDENT(KERNEL, PLAT_KEY): |
| 1052 | ASSIGN_FIELD_PTR(platform_key, &mbp->data[i+1]); |
| 1053 | |
| 1054 | case MBP_IDENT(KERNEL, FW_TYPE): |
| 1055 | ASSIGN_FIELD_PTR(fw_plat_type, &mbp->data[i+1]); |
| 1056 | |
| 1057 | case MBP_IDENT(KERNEL, MFS_FAILURE): |
| 1058 | ASSIGN_FIELD_PTR(mfsintegrity, &mbp->data[i+1]); |
| 1059 | |
Duncan Laurie | 144f7b2 | 2013-05-01 11:27:58 -0700 | [diff] [blame] | 1060 | case MBP_IDENT(KERNEL, PLAT_TIME): |
| 1061 | ASSIGN_FIELD_PTR(plat_time, &mbp->data[i+1]); |
| 1062 | |
| 1063 | case MBP_IDENT(NFC, SUPPORT_DATA): |
| 1064 | ASSIGN_FIELD_PTR(nfc_data, &mbp->data[i+1]); |
| 1065 | |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 1066 | default: |
Duncan Laurie | 0b3cd36 | 2013-08-08 15:40:01 -0700 | [diff] [blame] | 1067 | printk(BIOS_ERR, "ME MBP: unknown item 0x%x @ " |
| 1068 | "dw offset 0x%x\n", mbp->data[i], i); |
Aaron Durbin | be98524 | 2012-12-12 12:40:33 -0600 | [diff] [blame] | 1069 | break; |
| 1070 | } |
| 1071 | i += item->length; |
| 1072 | } |
| 1073 | #undef ASSIGN_FIELD_PTR |
| 1074 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1075 | return 0; |
Aaron Durbin | 9aa031e | 2012-11-02 09:16:46 -0500 | [diff] [blame] | 1076 | |
| 1077 | mbp_failure: |
| 1078 | intel_me_mbp_give_up(dev); |
| 1079 | return -1; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1080 | } |
Duncan Laurie | af98062 | 2013-07-18 23:02:18 -0700 | [diff] [blame] | 1081 | |
| 1082 | #endif /* !__SMM__ */ |