Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <console/console.h> |
| 18 | #include <device/device.h> |
| 19 | #include <device/pci.h> |
| 20 | #include <device/pciexp.h> |
| 21 | #include <device/pci_ids.h> |
Vladimir Serbinenko | 36fa5b8 | 2014-10-28 23:43:20 +0100 | [diff] [blame] | 22 | #include <southbridge/intel/common/pciehp.h> |
Patrick Rudolph | 604f698 | 2017-06-07 09:46:52 +0200 | [diff] [blame] | 23 | #include <assert.h> |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 24 | #include "pch.h" |
| 25 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 26 | static void pch_pcie_pm_early(struct device *dev) |
| 27 | { |
| 28 | u16 link_width_p0, link_width_p4; |
| 29 | u8 slot_power_limit = 10; /* 10W for x1 */ |
| 30 | u32 reg32; |
| 31 | u8 reg8; |
| 32 | |
Duncan Laurie | 4aca5d7 | 2012-04-27 10:58:22 -0700 | [diff] [blame] | 33 | reg32 = RCBA32(RPC); |
| 34 | |
| 35 | /* Port 0-3 link aggregation from PCIEPCS1[1:0] soft strap */ |
| 36 | switch (reg32 & 3) { |
| 37 | case 3: |
| 38 | link_width_p0 = 4; |
| 39 | break; |
| 40 | case 1: |
| 41 | case 2: |
| 42 | link_width_p0 = 2; |
| 43 | break; |
| 44 | case 0: |
| 45 | default: |
| 46 | link_width_p0 = 1; |
| 47 | } |
| 48 | |
| 49 | /* Port 4-7 link aggregation from PCIEPCS2[1:0] soft strap */ |
| 50 | switch ((reg32 >> 2) & 3) { |
| 51 | case 3: |
| 52 | link_width_p4 = 4; |
| 53 | break; |
| 54 | case 1: |
| 55 | case 2: |
| 56 | link_width_p4 = 2; |
| 57 | break; |
| 58 | case 0: |
| 59 | default: |
| 60 | link_width_p4 = 1; |
| 61 | } |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 62 | |
| 63 | /* Enable dynamic clock gating where needed */ |
| 64 | reg8 = pci_read_config8(dev, 0xe1); |
| 65 | switch (PCI_FUNC(dev->path.pci.devfn)) { |
| 66 | case 0: /* Port 0 */ |
| 67 | if (link_width_p0 == 4) |
| 68 | slot_power_limit = 40; /* 40W for x4 */ |
| 69 | else if (link_width_p0 == 2) |
| 70 | slot_power_limit = 20; /* 20W for x2 */ |
Duncan Laurie | 4aca5d7 | 2012-04-27 10:58:22 -0700 | [diff] [blame] | 71 | reg8 |= 0x3f; |
| 72 | break; |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 73 | case 4: /* Port 4 */ |
| 74 | if (link_width_p4 == 4) |
| 75 | slot_power_limit = 40; /* 40W for x4 */ |
| 76 | else if (link_width_p4 == 2) |
| 77 | slot_power_limit = 20; /* 20W for x2 */ |
| 78 | reg8 |= 0x3f; |
| 79 | break; |
| 80 | case 1: /* Port 1 only if Port 0 is x1 */ |
| 81 | if (link_width_p0 == 1) |
| 82 | reg8 |= 0x3; |
| 83 | break; |
| 84 | case 2: /* Port 2 only if Port 0 is x1 or x2 */ |
| 85 | case 3: /* Port 3 only if Port 0 is x1 or x2 */ |
| 86 | if (link_width_p0 <= 2) |
| 87 | reg8 |= 0x3; |
| 88 | break; |
| 89 | case 5: /* Port 5 only if Port 4 is x1 */ |
| 90 | if (link_width_p4 == 1) |
| 91 | reg8 |= 0x3; |
| 92 | break; |
| 93 | case 6: /* Port 7 only if Port 4 is x1 or x2 */ |
| 94 | case 7: /* Port 7 only if Port 4 is x1 or x2 */ |
| 95 | if (link_width_p4 <= 2) |
| 96 | reg8 |= 0x3; |
| 97 | break; |
| 98 | } |
| 99 | pci_write_config8(dev, 0xe1, reg8); |
| 100 | |
| 101 | /* Set 0xE8[0] = 1 */ |
| 102 | reg32 = pci_read_config32(dev, 0xe8); |
| 103 | reg32 |= 1; |
| 104 | pci_write_config32(dev, 0xe8, reg32); |
| 105 | |
| 106 | /* Adjust Common Clock exit latency */ |
| 107 | reg32 = pci_read_config32(dev, 0xd8); |
| 108 | reg32 &= ~(1 << 17); |
| 109 | reg32 |= (1 << 16) | (1 << 15); |
| 110 | reg32 &= ~(1 << 31); /* Disable PME# SCI for native PME handling */ |
| 111 | pci_write_config32(dev, 0xd8, reg32); |
| 112 | |
| 113 | /* Adjust ASPM L1 exit latency */ |
| 114 | reg32 = pci_read_config32(dev, 0x4c); |
| 115 | reg32 &= ~((1 << 17) | (1 << 16) | (1 << 15)); |
| 116 | if (RCBA32(0x2320) & (1 << 16)) { |
| 117 | /* If RCBA+2320[15]=1 set ASPM L1 to 8-16us */ |
| 118 | reg32 |= (1 << 17); |
| 119 | } else { |
| 120 | /* Else set ASPM L1 to 2-4us */ |
| 121 | reg32 |= (1 << 16); |
| 122 | } |
| 123 | pci_write_config32(dev, 0x4c, reg32); |
| 124 | |
| 125 | /* Set slot power limit as configured above */ |
| 126 | reg32 = pci_read_config32(dev, 0x54); |
| 127 | reg32 &= ~((1 << 15) | (1 << 16)); /* 16:15 = Slot power scale */ |
| 128 | reg32 &= ~(0xff << 7); /* 14:7 = Slot power limit */ |
| 129 | reg32 |= (slot_power_limit << 7); |
| 130 | pci_write_config32(dev, 0x54, reg32); |
| 131 | } |
| 132 | |
| 133 | static void pch_pcie_pm_late(struct device *dev) |
| 134 | { |
Marc Jones | 4adc8cd | 2012-10-31 16:24:37 -0600 | [diff] [blame] | 135 | struct southbridge_intel_bd82x6x_config *config = dev->chip_info; |
| 136 | enum aspm_type apmc = 0; |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 137 | u32 reg32; |
| 138 | |
| 139 | /* Set 0x314 = 0x743a361b */ |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 140 | pci_write_config32(dev, 0x314, 0x743a361b); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 141 | |
| 142 | /* Set 0x318[31:16] = 0x1414 */ |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 143 | reg32 = pci_read_config32(dev, 0x318); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 144 | reg32 &= 0x0000ffff; |
| 145 | reg32 |= 0x14140000; |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 146 | pci_write_config32(dev, 0x318, reg32); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 147 | |
| 148 | /* Set 0x324[5] = 1 */ |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 149 | reg32 = pci_read_config32(dev, 0x324); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 150 | reg32 |= (1 << 5); |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 151 | pci_write_config32(dev, 0x324, reg32); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 152 | |
| 153 | /* Set 0x330[7:0] = 0x40 */ |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 154 | reg32 = pci_read_config32(dev, 0x330); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 155 | reg32 &= ~(0xff); |
| 156 | reg32 |= 0x40; |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 157 | pci_write_config32(dev, 0x330, reg32); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 158 | |
| 159 | /* Set 0x33C[24:0] = 0x854c74 */ |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 160 | reg32 = pci_read_config32(dev, 0x33c); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 161 | reg32 &= 0xff000000; |
| 162 | reg32 |= 0x00854c74; |
Kyösti Mälkki | fd98c65 | 2013-07-26 08:50:53 +0300 | [diff] [blame] | 163 | pci_write_config32(dev, 0x33c, reg32); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 164 | |
| 165 | /* No IO-APIC, Disable EOI forwarding */ |
| 166 | reg32 = pci_read_config32(dev, 0xd4); |
| 167 | reg32 |= (1 << 1); |
| 168 | pci_write_config32(dev, 0xd4, reg32); |
| 169 | |
Marc Jones | 4adc8cd | 2012-10-31 16:24:37 -0600 | [diff] [blame] | 170 | /* Check for a rootport ASPM override */ |
| 171 | switch (PCI_FUNC(dev->path.pci.devfn)) { |
| 172 | case 0: |
| 173 | apmc = config->pcie_aspm_f0; |
| 174 | break; |
| 175 | case 1: |
| 176 | apmc = config->pcie_aspm_f1; |
| 177 | break; |
| 178 | case 2: |
| 179 | apmc = config->pcie_aspm_f2; |
| 180 | break; |
| 181 | case 3: |
| 182 | apmc = config->pcie_aspm_f3; |
| 183 | break; |
| 184 | case 4: |
| 185 | apmc = config->pcie_aspm_f4; |
| 186 | break; |
| 187 | case 5: |
| 188 | apmc = config->pcie_aspm_f5; |
| 189 | break; |
| 190 | case 6: |
| 191 | apmc = config->pcie_aspm_f6; |
| 192 | break; |
| 193 | case 7: |
| 194 | apmc = config->pcie_aspm_f7; |
| 195 | break; |
| 196 | } |
| 197 | |
| 198 | /* Setup the override or get the real ASPM setting */ |
| 199 | if (apmc) { |
| 200 | reg32 = pci_read_config32(dev, 0xd4); |
| 201 | reg32 |= (apmc << 2) | (1 << 4); |
| 202 | pci_write_config32(dev, 0xd4, reg32); |
| 203 | } else { |
| 204 | apmc = pci_read_config32(dev, 0x50) & 3; |
| 205 | } |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 206 | |
| 207 | /* If both L0s and L1 enabled then set root port 0xE8[1]=1 */ |
| 208 | if (apmc == PCIE_ASPM_BOTH) { |
| 209 | reg32 = pci_read_config32(dev, 0xe8); |
| 210 | reg32 |= (1 << 1); |
| 211 | pci_write_config32(dev, 0xe8, reg32); |
| 212 | } |
| 213 | } |
| 214 | |
| 215 | static void pci_init(struct device *dev) |
| 216 | { |
| 217 | u16 reg16; |
| 218 | u32 reg32; |
Vladimir Serbinenko | 36fa5b8 | 2014-10-28 23:43:20 +0100 | [diff] [blame] | 219 | struct southbridge_intel_bd82x6x_config *config = dev->chip_info; |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 220 | |
| 221 | printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n"); |
| 222 | |
| 223 | /* Enable Bus Master */ |
| 224 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 225 | reg32 |= PCI_COMMAND_MASTER; |
| 226 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 227 | |
| 228 | /* Set Cache Line Size to 0x10 */ |
| 229 | // This has no effect but the OS might expect it |
| 230 | pci_write_config8(dev, 0x0c, 0x10); |
| 231 | |
| 232 | reg16 = pci_read_config16(dev, 0x3e); |
| 233 | reg16 &= ~(1 << 0); /* disable parity error response */ |
| 234 | // reg16 &= ~(1 << 1); /* disable SERR */ |
| 235 | reg16 |= (1 << 2); /* ISA enable */ |
| 236 | pci_write_config16(dev, 0x3e, reg16); |
| 237 | |
| 238 | #ifdef EVEN_MORE_DEBUG |
| 239 | reg32 = pci_read_config32(dev, 0x20); |
| 240 | printk(BIOS_SPEW, " MBL = 0x%08x\n", reg32); |
| 241 | reg32 = pci_read_config32(dev, 0x24); |
| 242 | printk(BIOS_SPEW, " PMBL = 0x%08x\n", reg32); |
| 243 | reg32 = pci_read_config32(dev, 0x28); |
| 244 | printk(BIOS_SPEW, " PMBU32 = 0x%08x\n", reg32); |
| 245 | reg32 = pci_read_config32(dev, 0x2c); |
| 246 | printk(BIOS_SPEW, " PMLU32 = 0x%08x\n", reg32); |
| 247 | #endif |
| 248 | |
| 249 | /* Clear errors in status registers */ |
| 250 | reg16 = pci_read_config16(dev, 0x06); |
| 251 | //reg16 |= 0xf900; |
| 252 | pci_write_config16(dev, 0x06, reg16); |
| 253 | |
| 254 | reg16 = pci_read_config16(dev, 0x1e); |
| 255 | //reg16 |= 0xf900; |
| 256 | pci_write_config16(dev, 0x1e, reg16); |
Vladimir Serbinenko | 36fa5b8 | 2014-10-28 23:43:20 +0100 | [diff] [blame] | 257 | |
| 258 | /* Enable expresscard hotplug events. */ |
| 259 | if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) { |
| 260 | pci_write_config32(dev, 0xd8, |
| 261 | pci_read_config32(dev, 0xd8) |
| 262 | | (1 << 30)); |
| 263 | pci_write_config16(dev, 0x42, 0x142); |
| 264 | } |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 265 | } |
| 266 | |
Elyes HAOUAS | 4aec340 | 2018-05-25 08:29:27 +0200 | [diff] [blame] | 267 | static void pch_pcie_enable(struct device *dev) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 268 | { |
| 269 | /* Power Management init before enumeration */ |
| 270 | pch_pcie_pm_early(dev); |
| 271 | } |
| 272 | |
Elyes HAOUAS | 4aec340 | 2018-05-25 08:29:27 +0200 | [diff] [blame] | 273 | static void pch_pciexp_scan_bridge(struct device *dev) |
Marc Jones | 4adc8cd | 2012-10-31 16:24:37 -0600 | [diff] [blame] | 274 | { |
Vladimir Serbinenko | 36fa5b8 | 2014-10-28 23:43:20 +0100 | [diff] [blame] | 275 | struct southbridge_intel_bd82x6x_config *config = dev->chip_info; |
Marc Jones | 4adc8cd | 2012-10-31 16:24:37 -0600 | [diff] [blame] | 276 | |
| 277 | /* Normal PCIe Scan */ |
Kyösti Mälkki | 580e722 | 2015-03-19 21:04:23 +0200 | [diff] [blame] | 278 | pciexp_scan_bridge(dev); |
Marc Jones | 4adc8cd | 2012-10-31 16:24:37 -0600 | [diff] [blame] | 279 | |
Vladimir Serbinenko | 36fa5b8 | 2014-10-28 23:43:20 +0100 | [diff] [blame] | 280 | if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) { |
| 281 | intel_acpi_pcie_hotplug_scan_slot(dev->link_list); |
| 282 | } |
| 283 | |
Marc Jones | 4adc8cd | 2012-10-31 16:24:37 -0600 | [diff] [blame] | 284 | /* Late Power Management init after bridge device enumeration */ |
| 285 | pch_pcie_pm_late(dev); |
Marc Jones | 4adc8cd | 2012-10-31 16:24:37 -0600 | [diff] [blame] | 286 | } |
| 287 | |
Aaron Durbin | aa090cb | 2017-09-13 16:01:52 -0600 | [diff] [blame] | 288 | static const char *pch_pcie_acpi_name(const struct device *dev) |
Patrick Rudolph | 604f698 | 2017-06-07 09:46:52 +0200 | [diff] [blame] | 289 | { |
| 290 | ASSERT(dev); |
| 291 | |
| 292 | if (PCI_SLOT(dev->path.pci.devfn) == 0x1c) { |
| 293 | static const char *names[] = { "RP01", |
| 294 | "RP02", |
| 295 | "RP03", |
| 296 | "RP04", |
| 297 | "RP05", |
| 298 | "RP06", |
| 299 | "RP07", |
| 300 | "RP08"}; |
| 301 | |
| 302 | return names[PCI_FUNC(dev->path.pci.devfn)]; |
| 303 | } |
| 304 | |
| 305 | return NULL; |
| 306 | } |
| 307 | |
Elyes HAOUAS | 4aec340 | 2018-05-25 08:29:27 +0200 | [diff] [blame] | 308 | static void pcie_set_subsystem(struct device *dev, unsigned vendor, |
| 309 | unsigned device) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 310 | { |
| 311 | /* NOTE: This is not the default position! */ |
| 312 | if (!vendor || !device) { |
| 313 | pci_write_config32(dev, 0x94, |
| 314 | pci_read_config32(dev, 0)); |
| 315 | } else { |
| 316 | pci_write_config32(dev, 0x94, |
| 317 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 318 | } |
| 319 | } |
| 320 | |
| 321 | static struct pci_operations pci_ops = { |
| 322 | .set_subsystem = pcie_set_subsystem, |
| 323 | }; |
| 324 | |
| 325 | static struct device_operations device_ops = { |
| 326 | .read_resources = pci_bus_read_resources, |
| 327 | .set_resources = pci_dev_set_resources, |
| 328 | .enable_resources = pci_bus_enable_resources, |
| 329 | .init = pci_init, |
| 330 | .enable = pch_pcie_enable, |
Marc Jones | 4adc8cd | 2012-10-31 16:24:37 -0600 | [diff] [blame] | 331 | .scan_bus = pch_pciexp_scan_bridge, |
Patrick Rudolph | 604f698 | 2017-06-07 09:46:52 +0200 | [diff] [blame] | 332 | .acpi_name = pch_pcie_acpi_name, |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 333 | .ops_pci = &pci_ops, |
| 334 | }; |
| 335 | |
Stefan Reinauer | 9a380ab | 2012-06-22 13:16:11 -0700 | [diff] [blame] | 336 | static const unsigned short pci_device_ids[] = { 0x1c10, 0x1c12, 0x1c14, 0x1c16, |
| 337 | 0x1c18, 0x1c1a, 0x1c1c, 0x1c1e, |
| 338 | 0x1e10, 0x1e12, 0x1e14, 0x1e16, |
| 339 | 0x1e18, 0x1e1a, 0x1e1c, 0x1e1e, |
| 340 | 0 }; |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 341 | |
Stefan Reinauer | 9a380ab | 2012-06-22 13:16:11 -0700 | [diff] [blame] | 342 | static const struct pci_driver pch_pcie __pci_driver = { |
| 343 | .ops = &device_ops, |
| 344 | .vendor = PCI_VENDOR_ID_INTEL, |
| 345 | .devices = pci_device_ids, |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 346 | }; |