commit fd98c65b9d89e1ca665e25b6abf6d2019855e85a
author Kyösti Mälkki <kyosti.malkki@gmail.com> Fri Jul 26 08:50:53 2013 +0300
committer Kyösti Mälkki <kyosti.malkki@gmail.com> Fri Aug 09 23:20:52 2013 +0200
tree 17f16d8659ca8056aa06a2628bec4c7da1cea827
parent 0cc33da5530cf2ef776fc9fa2dbb80bb4dc4c830

intel/sandybridge intel/bd82x6x: remove explicit pcie config accesses

Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove
the pcie explicit accesses. The default config accesses use
MMIO.

Change-Id: I58c4b021ac87a035ac2ec2b6b110b75e6d263ab4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3810
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>

src/southbridge/intel/bd82x6x/pcie.c

diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c
index 2e3e465..fadb43f 100644
--- a/src/southbridge/intel/bd82x6x/pcie.c
+++ b/src/southbridge/intel/bd82x6x/pcie.c
@@ -139,30 +139,30 @@
 	u32 reg32;
 
 	/* Set 0x314 = 0x743a361b */
-	pci_mmio_write_config32(dev, 0x314, 0x743a361b);
+	pci_write_config32(dev, 0x314, 0x743a361b);
 
 	/* Set 0x318[31:16] = 0x1414 */
-	reg32 = pci_mmio_read_config32(dev, 0x318);
+	reg32 = pci_read_config32(dev, 0x318);
 	reg32 &= 0x0000ffff;
 	reg32 |= 0x14140000;
-	pci_mmio_write_config32(dev, 0x318, reg32);
+	pci_write_config32(dev, 0x318, reg32);
 
 	/* Set 0x324[5] = 1 */
-	reg32 = pci_mmio_read_config32(dev, 0x324);
+	reg32 = pci_read_config32(dev, 0x324);
 	reg32 |= (1 << 5);
-	pci_mmio_write_config32(dev, 0x324, reg32);
+	pci_write_config32(dev, 0x324, reg32);
 
 	/* Set 0x330[7:0] = 0x40 */
-	reg32 = pci_mmio_read_config32(dev, 0x330);
+	reg32 = pci_read_config32(dev, 0x330);
 	reg32 &= ~(0xff);
 	reg32 |= 0x40;
-	pci_mmio_write_config32(dev, 0x330, reg32);
+	pci_write_config32(dev, 0x330, reg32);
 
 	/* Set 0x33C[24:0] = 0x854c74 */
-	reg32 = pci_mmio_read_config32(dev, 0x33c);
+	reg32 = pci_read_config32(dev, 0x33c);
 	reg32 &= 0xff000000;
 	reg32 |= 0x00854c74;
-	pci_mmio_write_config32(dev, 0x33c, reg32);
+	pci_write_config32(dev, 0x33c, reg32);
 
 	/* No IO-APIC, Disable EOI forwarding */
 	reg32 = pci_read_config32(dev, 0xd4);