blob: 53bd16f68a84dba7bcd458f949a39cd5f2d9dd99 [file] [log] [blame]
Nicolas Reinecke2bffa8a2015-10-01 15:34:37 +02001chip northbridge/intel/sandybridge
2 # IGD Displays
3 register "gfx.ndid" = "3"
4 register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
5
6 # Enable DisplayPort Hotplug with 6ms pulse
7 register "gpu_dp_d_hotplug" = "0x06"
8
9 # Enable Panel as LVDS and configure power delays
10 register "gpu_panel_port_select" = "0" # LVDS
11 register "gpu_panel_power_cycle_delay" = "1"
12 register "gpu_panel_power_up_delay" = "300" # T1+T2: 30ms
13 register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms
14 register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms
15 register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms
16 register "gfx.use_spread_spectrum_clock" = "1"
17 register "gfx.link_frequency_270_mhz" = "1"
18 register "gpu_cpu_backlight" = "0x1155"
19 register "gpu_pch_backlight" = "0x06100610"
20
21 device cpu_cluster 0 on
Nicolas Reinecke2bffa8a2015-10-01 15:34:37 +020022 chip cpu/intel/model_206ax
23 # Magic APIC ID to locate this chip
Arthur Heymans7e6946a2019-01-21 17:55:02 +010024 device lapic 0x0 on end
Arthur Heymansb3f23232019-01-21 17:48:55 +010025 device lapic 0xacac off end
Nicolas Reinecke2bffa8a2015-10-01 15:34:37 +020026
27 register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1)
28 register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)
29 register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7)
30
31 register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1)
32 register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)
33 register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7)
34 end
35 end
36
Patrick Rudolph266a1f72016-06-09 18:13:34 +020037 register "pci_mmio_size" = "2048"
38
Nicolas Reinecke2bffa8a2015-10-01 15:34:37 +020039 device domain 0 on
Peter Lemenkovf15f3102019-11-27 12:04:42 +010040 subsystemid 0x17aa 0x21ce inherit
41
42 device pci 00.0 on end # host bridge
Patrick Rudolph830fdc72016-04-21 07:15:14 +020043 device pci 01.0 on end # PCIe Bridge for discrete graphics
Peter Lemenkovf15f3102019-11-27 12:04:42 +010044 device pci 02.0 on end # Integrated Graphics Controller
Nicolas Reinecke2bffa8a2015-10-01 15:34:37 +020045
46 chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
47 # GPI routing
48 # 0 No effect (default)
49 # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
50 # 2 SCI (if corresponding GPIO_EN bit is also set)
51 register "alt_gp_smi_en" = "0x0000"
52 register "gpi1_routing" = "2"
53 register "gpi13_routing" = "2"
54
Iru Cai0bca3c92016-05-06 23:05:28 +080055 # Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 3 (eSATA) & 4 (dock)
56 register "sata_port_map" = "0x1f"
Nicolas Reinecke2bffa8a2015-10-01 15:34:37 +020057 # Set max SATA speed to 6.0 Gb/s
58 register "sata_interface_speed_support" = "0x3"
59
60 register "gen1_dec" = "0x7c1601"
61 register "gen2_dec" = "0x0c15e1"
62 register "gen4_dec" = "0x0c06a1"
63
64 register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
65
66 # Enable zero-based linear PCIe root port functions
67 register "pcie_port_coalesce" = "1"
Peter Lemenkovf15f3102019-11-27 12:04:42 +010068
Nicolas Reinecke2bffa8a2015-10-01 15:34:37 +020069 register "c2_latency" = "101" # c2 not supported
Nicolas Reinecke2bffa8a2015-10-01 15:34:37 +020070
Patrick Rudolphc670a412017-04-28 17:28:32 +020071 # device specific SPI configuration
72 register "spi_uvscc" = "0x2005"
73 register "spi_lvscc" = "0x2005"
74
Nicolas Reinecke2bffa8a2015-10-01 15:34:37 +020075 device pci 16.0 off end # Management Engine Interface 1
76 device pci 16.1 off end # Management Engine Interface 2
77 device pci 16.2 off end # Management Engine IDE-R
78 device pci 16.3 off end # Management Engine KT
Peter Lemenkovf15f3102019-11-27 12:04:42 +010079 device pci 19.0 on end # Intel Gigabit Ethernet
80 device pci 1a.0 on end # USB Enhanced Host Controller #2
81 device pci 1b.0 on end # High Definition Audio Controller
Nicolas Reinecke2bffa8a2015-10-01 15:34:37 +020082 device pci 1c.0 off end # PCIe Port #1
Peter Lemenkovf15f3102019-11-27 12:04:42 +010083 device pci 1c.1 on end # PCIe Port #2 Integrated Wireless LAN
Nicolas Reinecke2bffa8a2015-10-01 15:34:37 +020084 device pci 1c.2 off end # PCIe Port #3
85 device pci 1c.3 on
Patrick Rudolph05216322019-04-12 16:14:27 +020086 smbios_slot_desc "7" "3" "ExpressCard Slot" "8"
Nicolas Reinecke2bffa8a2015-10-01 15:34:37 +020087 end # PCIe Port #4 ExpressCard
88 device pci 1c.4 on
Nicolas Reinecke2bffa8a2015-10-01 15:34:37 +020089 chip drivers/ricoh/rce822
90 register "sdwppol" = "1"
91 register "disable_mask" = "0x87"
Peter Lemenkovf15f3102019-11-27 12:04:42 +010092 device pci 00.0 on end
Nicolas Reinecke2bffa8a2015-10-01 15:34:37 +020093 end
94 end # PCIe Port #5 (Ricoh SD & FW)
95 device pci 1c.5 off end # PCIe Port #6 Intel Gigabit Ethernet PHY (not PCIe)
96 device pci 1c.6 off end # PCIe Port #7
97 device pci 1c.7 off end # PCIe Port #8
Peter Lemenkovf15f3102019-11-27 12:04:42 +010098 device pci 1d.0 on end # USB Enhanced Host Controller #1
Nicolas Reinecke2bffa8a2015-10-01 15:34:37 +020099 device pci 1e.0 off end # PCI bridge
100 device pci 1f.0 on
Nicolas Reinecke2bffa8a2015-10-01 15:34:37 +0200101 chip ec/lenovo/pmh7
Peter Lemenkovf15f3102019-11-27 12:04:42 +0100102 device pnp ff.1 on end # dummy
Nicolas Reinecke2bffa8a2015-10-01 15:34:37 +0200103 register "backlight_enable" = "0x01"
104 register "dock_event_enable" = "0x01"
105 end
106
107 chip drivers/pc80/tpm
108 device pnp 0c31.0 on end
109 end
110
111 chip ec/lenovo/h8
112 device pnp ff.2 on # dummy
113 io 0x60 = 0x62
114 io 0x62 = 0x66
115 io 0x64 = 0x1600
116 io 0x66 = 0x1604
117 end
118
119 register "config0" = "0xa7"
120 register "config1" = "0x01"
121 register "config2" = "0xa0"
122 register "config3" = "0xe2"
123
124 register "has_keyboard_backlight" = "0"
125
126 register "beepmask0" = "0x02"
127 register "beepmask1" = "0x86"
128 register "has_power_management_beeps" = "1"
129 register "event2_enable" = "0xff"
130 register "event3_enable" = "0xff"
131 register "event4_enable" = "0xf0"
132 register "event5_enable" = "0x3c"
133 register "event6_enable" = "0x00"
134 register "event7_enable" = "0xa1"
135 register "event8_enable" = "0x7b"
136 register "event9_enable" = "0xff"
137 register "eventa_enable" = "0x00"
138 register "eventb_enable" = "0x00"
139 register "eventc_enable" = "0xff"
140 register "eventd_enable" = "0xff"
141 register "evente_enable" = "0x0d"
Patrick Rudolphb77eec82017-05-21 09:20:39 +0200142
143 register "has_bdc_detection" = "1"
144 register "bdc_gpio_num" = "54"
145 register "bdc_gpio_lvl" = "0"
Nicolas Reinecke2bffa8a2015-10-01 15:34:37 +0200146 end
Patrick Rudolphdb27e3382017-07-27 18:00:59 +0200147 chip drivers/lenovo/hybrid_graphics
148 device pnp ff.f on end # dummy
149
150 register "detect_gpio" = "21"
151
152 register "has_panel_hybrid_gpio" = "1"
153 register "panel_hybrid_gpio" = "52"
154 register "panel_integrated_lvl" = "1"
155
156 register "has_backlight_gpio" = "0"
157 register "has_dgpu_power_gpio" = "0"
158
159 register "has_thinker1" = "1"
160 end
Nicolas Reinecke2bffa8a2015-10-01 15:34:37 +0200161 end # LPC Controller
Peter Lemenkovf15f3102019-11-27 12:04:42 +0100162 device pci 1f.2 on end # 6 port SATA AHCI Controller
Nicolas Reinecke2bffa8a2015-10-01 15:34:37 +0200163 device pci 1f.3 on
Nicolas Reinecke2bffa8a2015-10-01 15:34:37 +0200164 # eeprom, 8 virtual devices, same chip
165 chip drivers/i2c/at24rf08c
166 device i2c 54 on end
167 device i2c 55 on end
168 device i2c 56 on end
169 device i2c 57 on end
170 device i2c 5c on end
171 device i2c 5d on end
172 device i2c 5e on end
173 device i2c 5f on end
174 end
175 end # SMBus Controller
176 device pci 1f.5 off end # SATA Controller 2
Peter Lemenkovf15f3102019-11-27 12:04:42 +0100177 device pci 1f.6 on end # Thermal
Nicolas Reinecke2bffa8a2015-10-01 15:34:37 +0200178 end
179 end
180end