efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 4 | * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | /*---------------------------------------------------------------------------------------- |
| 21 | * M O D U L E S U S E D |
| 22 | *---------------------------------------------------------------------------------------- |
| 23 | */ |
| 24 | |
| 25 | #include <stdint.h> |
| 26 | #include <string.h> |
| 27 | #include "agesawrapper.h" |
| 28 | #include "BiosCallOuts.h" |
| 29 | #include "cpuRegisters.h" |
| 30 | #include "cpuCacheInit.h" |
| 31 | #include "cpuApicUtilities.h" |
| 32 | #include "cpuEarlyInit.h" |
| 33 | #include "cpuLateInit.h" |
| 34 | #include "Dispatcher.h" |
| 35 | #include "cpuCacheInit.h" |
| 36 | #include "amdlib.h" |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 37 | #include "Filecode.h" |
| 38 | #include "heapManager.h" |
| 39 | #include <cpuFamilyTranslation.h> /* CPU_SPECIFIC_SERVICES */ |
| 40 | |
| 41 | #define FILECODE UNASSIGNED_FILE_FILECODE |
| 42 | |
| 43 | /*---------------------------------------------------------------------------------------- |
| 44 | * D E F I N I T I O N S A N D M A C R O S |
| 45 | *---------------------------------------------------------------------------------------- |
| 46 | */ |
| 47 | |
| 48 | /* ACPI table pointers returned by AmdInitLate */ |
| 49 | VOID *DmiTable = NULL; |
| 50 | VOID *AcpiPstate = NULL; |
| 51 | VOID *AcpiSrat = NULL; |
| 52 | VOID *AcpiSlit = NULL; |
| 53 | |
| 54 | VOID *AcpiWheaMce = NULL; |
| 55 | VOID *AcpiWheaCmc = NULL; |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 56 | VOID *AcpiAlib = NULL; |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 57 | |
| 58 | |
| 59 | /*---------------------------------------------------------------------------------------- |
| 60 | * T Y P E D E F S A N D S T R U C T U R E S |
| 61 | *---------------------------------------------------------------------------------------- |
| 62 | */ |
| 63 | |
| 64 | /*---------------------------------------------------------------------------------------- |
| 65 | * P R O T O T Y P E S O F L O C A L F U N C T I O N S |
| 66 | *---------------------------------------------------------------------------------------- |
| 67 | */ |
| 68 | |
| 69 | /*---------------------------------------------------------------------------------------- |
| 70 | * E X P O R T E D F U N C T I O N S |
| 71 | *---------------------------------------------------------------------------------------- |
| 72 | */ |
| 73 | |
| 74 | /*--------------------------------------------------------------------------------------- |
| 75 | * L O C A L F U N C T I O N S |
| 76 | *--------------------------------------------------------------------------------------- |
| 77 | */ |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 78 | extern VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 79 | |
| 80 | static UINT32 agesawrapper_amdinitcpuio(VOID) |
| 81 | { |
| 82 | AGESA_STATUS Status; |
| 83 | UINT32 PciData; |
| 84 | PCI_ADDR PciAddress; |
| 85 | AMD_CONFIG_PARAMS StdHeader; |
| 86 | UINT32 nodes; |
| 87 | UINT32 node; |
| 88 | UINT32 sblink; |
| 89 | UINT32 i; |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 90 | UINT32 TOM; |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 91 | |
| 92 | /* get the number of coherent nodes in the system */ |
| 93 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60); |
| 94 | LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 95 | nodes = ((PciData >> 4) & 7) + 1; //NodeCnt[2:0] |
| 96 | |
| 97 | /* Find out the Link ID of Node0 that connects to the |
| 98 | * Southbridge (system IO hub). e.g. family10 MCM Processor, |
| 99 | * sbLink is Processor0 Link2, internal Node0 Link3 |
| 100 | */ |
| 101 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x64); |
| 102 | LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 103 | sblink = (PciData >> 8) & 3; //assume ganged |
| 104 | |
| 105 | /* Enable MMIO on AMD CPU Address Map Controller for all nodes */ |
| 106 | for (node = 0; node < nodes; node++) { |
| 107 | /* clear all MMIO Mapped Base/Limit Registers */ |
| 108 | for (i = 0; i < 8; i++) { |
| 109 | PciData = 0x00000000; |
| 110 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80 + i*8); |
| 111 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 112 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84 + i*8); |
| 113 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 114 | } |
| 115 | |
| 116 | /* clear all IO Space Base/Limit Registers */ |
| 117 | for (i = 0; i < 4; i++) { |
| 118 | PciData = 0x00000000; |
| 119 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4 + i*8); |
| 120 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 121 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0 + i*8); |
| 122 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 123 | } |
| 124 | |
| 125 | /* Set VGA Ram MMIO 0000A0000-0000BFFFF to Node0 sbLink */ |
| 126 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84); |
| 127 | PciData = 0x00000B00; |
| 128 | PciData |= sblink << 4; |
| 129 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 130 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80); |
| 131 | PciData = 0x00000A03; |
| 132 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 133 | |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 134 | /* Set TOM1-FFFFFFFF to Node0 sbLink. */ |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 135 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x8C); |
| 136 | PciData = 0x00FFFF00; |
| 137 | PciData |= sblink << 4; |
| 138 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 139 | TOM = (UINT32)MsrRead(TOP_MEM); |
| 140 | PciData = (TOM >> 8) | 0x03; |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 141 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x88); |
| 142 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 143 | |
| 144 | /* Set MMCONF space to Node0 sbLink with NP set. |
| 145 | * default E0000000-EFFFFFFF |
| 146 | * Just have all mmio set to non-posted, |
| 147 | * coreboot not implemente the range by range setting yet. |
| 148 | */ |
| 149 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xBC); |
Konstantin Aladyshev | 3d990ff | 2013-01-25 19:20:51 +0400 | [diff] [blame] | 150 | PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000) - 1;//1MB each bus |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 151 | PciData = (PciData >> 8) & 0xFFFFFF00; |
| 152 | PciData |= 0x80; //NP |
| 153 | PciData |= sblink << 4; |
| 154 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 155 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xB8); |
| 156 | PciData = (PCIE_BASE_ADDRESS >> 8) | 0x03; |
| 157 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 158 | |
| 159 | |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 160 | /* Set PCIO: 0x0 - 0xFFF000 to Node0 sbLink and enabled VGA IO*/ |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 161 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4); |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 162 | PciData = 0x00FFF000; |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 163 | PciData |= sblink << 4; |
| 164 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 165 | PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0); |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 166 | PciData = 0x00000033; |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 167 | LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| 168 | } |
| 169 | |
| 170 | Status = AGESA_SUCCESS; |
| 171 | return (UINT32)Status; |
| 172 | } |
| 173 | |
| 174 | UINT32 agesawrapper_amdinitmmio(VOID) |
| 175 | { |
| 176 | AGESA_STATUS Status; |
| 177 | UINT64 MsrReg; |
| 178 | AMD_CONFIG_PARAMS StdHeader; |
| 179 | |
| 180 | /* |
| 181 | * Set the MMIO Configuration Base Address and Bus Range onto |
| 182 | * MMIO configuration base Address MSR register. |
| 183 | */ |
| 184 | MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; |
| 185 | LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader); |
| 186 | |
| 187 | /* |
| 188 | * Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. |
| 189 | */ |
| 190 | LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader); |
| 191 | MsrReg = MsrReg | (1ULL << 46); |
| 192 | LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader); |
| 193 | |
| 194 | /* Set ROM cache onto WP to decrease post time */ |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 195 | MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5; |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 196 | LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); |
Martin Roth | 09574d5 | 2013-01-14 15:46:38 -0700 | [diff] [blame] | 197 | MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 198 | LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); |
| 199 | |
| 200 | Status = AGESA_SUCCESS; |
| 201 | return (UINT32)Status; |
| 202 | } |
| 203 | |
| 204 | UINT32 agesawrapper_amdinitreset(VOID) |
| 205 | { |
| 206 | AGESA_STATUS status = AGESA_SUCCESS; |
| 207 | AMD_INTERFACE_PARAMS AmdParamStruct; |
| 208 | AMD_RESET_PARAMS AmdResetParams; |
| 209 | |
| 210 | LibAmdMemFill(&AmdParamStruct, |
| 211 | 0, |
| 212 | sizeof(AMD_INTERFACE_PARAMS), |
| 213 | &(AmdParamStruct.StdHeader)); |
| 214 | |
| 215 | LibAmdMemFill(&AmdResetParams, |
| 216 | 0, |
| 217 | sizeof(AMD_RESET_PARAMS), |
| 218 | &(AmdResetParams.StdHeader)); |
| 219 | |
| 220 | AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; |
| 221 | AmdParamStruct.AllocationMethod = ByHost; |
| 222 | AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); |
| 223 | AmdParamStruct.NewStructPtr = &AmdResetParams; |
| 224 | AmdParamStruct.StdHeader.AltImageBasePtr = 0; |
| 225 | AmdParamStruct.StdHeader.CalloutPtr = NULL; |
| 226 | AmdParamStruct.StdHeader.Func = 0; |
| 227 | AmdParamStruct.StdHeader.ImageBasePtr = 0; |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 228 | status = AmdCreateStruct(&AmdParamStruct); |
| 229 | if (status != AGESA_SUCCESS) { |
| 230 | return (UINT32)status; |
| 231 | } |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 232 | AmdResetParams.HtConfig.Depth = 0; |
| 233 | |
| 234 | //MARG34PI disabled AGESA_ENTRY_INIT_RESET by default |
| 235 | //but we need to call AmdCreateStruct to call HeapManagerInit, or the event log not work |
| 236 | #if (defined AGESA_ENTRY_INIT_RESET) && (AGESA_ENTRY_INIT_RESET == TRUE) |
| 237 | status = AmdInitReset((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); |
| 238 | #endif |
| 239 | if (status != AGESA_SUCCESS) |
| 240 | agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); |
| 241 | AmdReleaseStruct(&AmdParamStruct); |
| 242 | |
| 243 | return (UINT32)status; |
| 244 | } |
| 245 | |
| 246 | UINT32 agesawrapper_amdinitearly(VOID) |
| 247 | { |
| 248 | AGESA_STATUS status; |
| 249 | AMD_INTERFACE_PARAMS AmdParamStruct; |
| 250 | AMD_EARLY_PARAMS *AmdEarlyParamsPtr; |
| 251 | UINT32 TscRateInMhz; |
| 252 | CPU_SPECIFIC_SERVICES *FamilySpecificServices; |
| 253 | |
| 254 | LibAmdMemFill(&AmdParamStruct, |
| 255 | 0, |
| 256 | sizeof(AMD_INTERFACE_PARAMS), |
| 257 | &(AmdParamStruct.StdHeader)); |
| 258 | |
| 259 | AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; |
| 260 | AmdParamStruct.AllocationMethod = PreMemHeap; |
| 261 | AmdParamStruct.StdHeader.AltImageBasePtr = 0; |
| 262 | AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; |
| 263 | AmdParamStruct.StdHeader.Func = 0; |
| 264 | AmdParamStruct.StdHeader.ImageBasePtr = 0; |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 265 | status = AmdCreateStruct(&AmdParamStruct); |
| 266 | if (status != AGESA_SUCCESS) { |
| 267 | return (UINT32)status; |
| 268 | } |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 269 | |
| 270 | AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; |
| 271 | OemCustomizeInitEarly(AmdEarlyParamsPtr); |
| 272 | |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 273 | status = AmdInitEarly(AmdEarlyParamsPtr); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 274 | if (status != AGESA_SUCCESS) |
| 275 | agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); |
| 276 | |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 277 | GetCpuServicesOfCurrentCore((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &AmdParamStruct.StdHeader); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 278 | FamilySpecificServices->GetTscRate(FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader); |
Martin Roth | 7675d8a | 2013-02-24 15:09:11 -0700 | [diff] [blame] | 279 | printk(BIOS_DEBUG, "BSP Frequency: %uMHz\n", (unsigned int)TscRateInMhz); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 280 | |
| 281 | AmdReleaseStruct(&AmdParamStruct); |
| 282 | return (UINT32)status; |
| 283 | } |
| 284 | |
| 285 | UINT32 agesawrapper_amdinitpost(VOID) |
| 286 | { |
| 287 | AGESA_STATUS status; |
| 288 | UINT16 i; |
| 289 | UINT32 *HeadPtr; |
| 290 | AMD_INTERFACE_PARAMS AmdParamStruct; |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 291 | AMD_POST_PARAMS *PostParams; |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 292 | BIOS_HEAP_MANAGER *BiosManagerPtr; |
| 293 | UINT32 TscRateInMhz; |
| 294 | CPU_SPECIFIC_SERVICES *FamilySpecificServices; |
| 295 | |
| 296 | LibAmdMemFill(&AmdParamStruct, |
| 297 | 0, |
| 298 | sizeof(AMD_INTERFACE_PARAMS), |
| 299 | &(AmdParamStruct.StdHeader)); |
| 300 | |
| 301 | AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; |
| 302 | AmdParamStruct.AllocationMethod = PreMemHeap; |
| 303 | AmdParamStruct.StdHeader.AltImageBasePtr = 0; |
| 304 | AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; |
| 305 | AmdParamStruct.StdHeader.Func = 0; |
| 306 | AmdParamStruct.StdHeader.ImageBasePtr = 0; |
| 307 | |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 308 | status = AmdCreateStruct(&AmdParamStruct); |
| 309 | if (status != AGESA_SUCCESS) { |
| 310 | return (UINT32)status; |
| 311 | } |
| 312 | PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; |
| 313 | status = AmdInitPost(PostParams); |
| 314 | if (status != AGESA_SUCCESS) { |
| 315 | agesawrapper_amdreadeventlog(PostParams->StdHeader.HeapStatus); |
| 316 | } |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 317 | AmdReleaseStruct(&AmdParamStruct); |
| 318 | |
| 319 | /* Initialize heap space */ |
| 320 | BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS; |
| 321 | |
| 322 | HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof(BIOS_HEAP_MANAGER)); |
| 323 | for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof(BIOS_HEAP_MANAGER)/4)); i++) { |
| 324 | *HeadPtr = 0x00000000; |
| 325 | HeadPtr++; |
| 326 | } |
| 327 | BiosManagerPtr->StartOfAllocatedNodes = 0; |
| 328 | BiosManagerPtr->StartOfFreedNodes = 0; |
| 329 | |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 330 | GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &AmdParamStruct.StdHeader); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 331 | FamilySpecificServices->GetTscRate (FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader); |
Martin Roth | 7675d8a | 2013-02-24 15:09:11 -0700 | [diff] [blame] | 332 | printk(BIOS_DEBUG, "BSP Frequency: %uMHz\n", (unsigned int)TscRateInMhz); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 333 | |
| 334 | return (UINT32)status; |
| 335 | } |
| 336 | |
| 337 | UINT32 agesawrapper_amdinitenv(VOID) |
| 338 | { |
| 339 | AGESA_STATUS status; |
| 340 | AMD_INTERFACE_PARAMS AmdParamStruct; |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 341 | AMD_ENV_PARAMS *EnvParams; |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 342 | |
| 343 | LibAmdMemFill(&AmdParamStruct, |
| 344 | 0, |
| 345 | sizeof(AMD_INTERFACE_PARAMS), |
| 346 | &(AmdParamStruct.StdHeader)); |
| 347 | |
| 348 | AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; |
| 349 | AmdParamStruct.AllocationMethod = PostMemDram; |
| 350 | AmdParamStruct.StdHeader.AltImageBasePtr = 0; |
| 351 | AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; |
| 352 | AmdParamStruct.StdHeader.Func = 0; |
| 353 | AmdParamStruct.StdHeader.ImageBasePtr = 0; |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 354 | |
| 355 | status = AmdCreateStruct(&AmdParamStruct); |
| 356 | if (status != AGESA_SUCCESS) { |
| 357 | return (UINT32)status; |
| 358 | } |
| 359 | EnvParams = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr; |
| 360 | status = AmdInitEnv(EnvParams); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 361 | if (status != AGESA_SUCCESS) |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 362 | agesawrapper_amdreadeventlog(EnvParams->StdHeader.HeapStatus); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 363 | |
| 364 | AmdReleaseStruct(&AmdParamStruct); |
| 365 | return (UINT32)status; |
| 366 | } |
| 367 | |
| 368 | VOID * agesawrapper_getlateinitptr(int pick) |
| 369 | { |
| 370 | switch (pick) { |
| 371 | case PICK_DMI: |
| 372 | return DmiTable; |
| 373 | |
| 374 | case PICK_PSTATE: |
| 375 | return AcpiPstate; |
| 376 | |
| 377 | case PICK_SRAT: |
| 378 | return AcpiSrat; |
| 379 | |
| 380 | case PICK_SLIT: |
| 381 | return AcpiSlit; |
| 382 | case PICK_WHEA_MCE: |
| 383 | return AcpiWheaMce; |
| 384 | case PICK_WHEA_CMC: |
| 385 | return AcpiWheaCmc; |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 386 | case PICK_ALIB: |
| 387 | return AcpiAlib; |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 388 | default: |
| 389 | return NULL; |
| 390 | } |
| 391 | |
| 392 | return NULL; |
| 393 | } |
| 394 | |
| 395 | UINT32 agesawrapper_amdinitmid(VOID) |
| 396 | { |
| 397 | AGESA_STATUS status; |
| 398 | AMD_INTERFACE_PARAMS AmdParamStruct; |
| 399 | |
| 400 | /* Enable MMIO on AMD CPU Address Map Controller */ |
| 401 | agesawrapper_amdinitcpuio(); |
| 402 | |
| 403 | LibAmdMemFill(&AmdParamStruct, |
| 404 | 0, |
| 405 | sizeof(AMD_INTERFACE_PARAMS), |
| 406 | &(AmdParamStruct.StdHeader)); |
| 407 | |
| 408 | AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; |
| 409 | AmdParamStruct.AllocationMethod = PostMemDram; |
| 410 | AmdParamStruct.StdHeader.AltImageBasePtr = 0; |
| 411 | AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; |
| 412 | AmdParamStruct.StdHeader.Func = 0; |
| 413 | AmdParamStruct.StdHeader.ImageBasePtr = 0; |
| 414 | |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 415 | status = AmdCreateStruct(&AmdParamStruct); |
| 416 | if (status != AGESA_SUCCESS) { |
| 417 | return (UINT32)status; |
| 418 | } |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 419 | status = AmdInitMid((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); |
| 420 | if (status != AGESA_SUCCESS) |
| 421 | agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); |
| 422 | AmdReleaseStruct(&AmdParamStruct); |
| 423 | |
| 424 | return (UINT32)status; |
| 425 | } |
| 426 | |
| 427 | UINT32 agesawrapper_amdinitlate(VOID) |
| 428 | { |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 429 | AGESA_STATUS Status; |
| 430 | AMD_INTERFACE_PARAMS AmdParamStruct; |
| 431 | AMD_LATE_PARAMS *AmdLateParamsPtr; |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 432 | |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 433 | LibAmdMemFill(&AmdParamStruct, |
| 434 | 0, |
| 435 | sizeof (AMD_INTERFACE_PARAMS), |
| 436 | &(AmdParamStruct.StdHeader)); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 437 | |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 438 | AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; |
| 439 | AmdParamStruct.AllocationMethod = PostMemDram; |
| 440 | AmdParamStruct.StdHeader.AltImageBasePtr = 0; |
| 441 | AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; |
| 442 | AmdParamStruct.StdHeader.Func = 0; |
| 443 | AmdParamStruct.StdHeader.ImageBasePtr = 0; |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 444 | |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 445 | AmdCreateStruct (&AmdParamStruct); |
| 446 | AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr; |
| 447 | |
| 448 | printk(BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr); |
| 449 | |
| 450 | Status = AmdInitLate(AmdLateParamsPtr); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 451 | if (Status != AGESA_SUCCESS) { |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 452 | agesawrapper_amdreadeventlog(AmdLateParamsPtr->StdHeader.HeapStatus); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 453 | ASSERT(Status == AGESA_SUCCESS); |
| 454 | } |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 455 | DmiTable = AmdLateParamsPtr->DmiTable; |
| 456 | AcpiPstate = AmdLateParamsPtr->AcpiPState; |
| 457 | AcpiSrat = AmdLateParamsPtr->AcpiSrat; |
| 458 | AcpiSlit = AmdLateParamsPtr->AcpiSlit; |
| 459 | AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce; |
| 460 | AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc; |
| 461 | AcpiAlib = AmdLateParamsPtr->AcpiAlib; |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 462 | |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 463 | printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n" |
| 464 | " DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n" |
| 465 | " Mce:%p\n Cmc:%p\n Alib:%p\n", |
| 466 | __func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit, |
| 467 | AcpiWheaMce, AcpiWheaCmc, AcpiAlib); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 468 | |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 469 | /* Don't release the structure until coreboot has copied the ACPI tables. |
| 470 | * AmdReleaseStruct (&AmdLateParams); |
| 471 | */ |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 472 | |
| 473 | return (UINT32)Status; |
| 474 | } |
| 475 | |
| 476 | /** |
| 477 | * @param[in] UINTN ApicIdOfCore, |
| 478 | * @param[in] AP_EXE_PARAMS *LaunchApParams |
| 479 | */ |
| 480 | UINT32 agesawrapper_amdlaterunaptask(UINT32 Data, VOID *ConfigPtr) |
| 481 | { |
| 482 | AGESA_STATUS Status; |
| 483 | AMD_LATE_PARAMS AmdLateParams; |
| 484 | |
| 485 | LibAmdMemFill(&AmdLateParams, |
| 486 | 0, |
| 487 | sizeof(AMD_LATE_PARAMS), |
| 488 | &(AmdLateParams.StdHeader)); |
| 489 | |
| 490 | AmdLateParams.StdHeader.AltImageBasePtr = 0; |
| 491 | AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; |
| 492 | AmdLateParams.StdHeader.Func = 0; |
| 493 | AmdLateParams.StdHeader.ImageBasePtr = 0; |
| 494 | AmdLateParams.StdHeader.HeapStatus = HEAP_TEMP_MEM; |
| 495 | |
| 496 | printk(BIOS_DEBUG, "AmdLateRunApTask on Core: %x\n", (uint32_t)Data); |
| 497 | Status = AmdLateRunApTask((AP_EXE_PARAMS *)ConfigPtr); |
| 498 | if (Status != AGESA_SUCCESS) { |
| 499 | agesawrapper_amdreadeventlog(AmdLateParams.StdHeader.HeapStatus); |
| 500 | ASSERT(Status <= AGESA_UNSUPPORTED); |
| 501 | } |
| 502 | |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 503 | return (UINT32)Status; |
| 504 | } |
| 505 | |
| 506 | /** |
| 507 | * |
| 508 | */ |
| 509 | static void agesa_bound_check(EVENT_PARAMS *event) |
| 510 | { |
| 511 | switch (event->EventInfo) { |
| 512 | case CPU_ERROR_HEAP_IS_FULL: |
| 513 | printk(BIOS_DEBUG, "Heap allocation for specified buffer handle failed as heap is full\n"); |
| 514 | break; |
| 515 | |
| 516 | case CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED: |
| 517 | printk(BIOS_DEBUG, "Allocation incomplete as buffer has previously been allocated\n"); |
| 518 | break; |
| 519 | |
| 520 | case CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT: |
| 521 | printk(BIOS_DEBUG, "Unable to locate buffer handle or deallocate heap as buffer handle cannot be located\n"); |
| 522 | break; |
| 523 | |
| 524 | case CPU_ERROR_HEAP_BUFFER_IS_NOT_PRESENT: |
| 525 | printk(BIOS_DEBUG, "Unable to locate pointer to the heap buffer\n"); |
| 526 | break; |
| 527 | |
| 528 | default: |
| 529 | break; |
| 530 | } |
| 531 | } |
| 532 | |
| 533 | /** |
| 534 | * |
| 535 | */ |
| 536 | static void agesa_alert(EVENT_PARAMS *event) |
| 537 | { |
| 538 | switch (event->EventInfo) { |
| 539 | case MEM_ALERT_USER_TMG_MODE_OVERRULED: |
Martin Roth | 7675d8a | 2013-02-24 15:09:11 -0700 | [diff] [blame] | 540 | printk(BIOS_DEBUG, "Socket %x Dct %x Channel %x " |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 541 | "TIMING_MODE_SPECIFIC is requested but can not be applied to current configurations.\n", |
Martin Roth | 7675d8a | 2013-02-24 15:09:11 -0700 | [diff] [blame] | 542 | (unsigned int)event->DataParam1, |
| 543 | (unsigned int)event->DataParam2, |
| 544 | (unsigned int)event->DataParam3); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 545 | break; |
| 546 | |
| 547 | case MEM_ALERT_ORG_MISMATCH_DIMM: |
Martin Roth | 7675d8a | 2013-02-24 15:09:11 -0700 | [diff] [blame] | 548 | printk(BIOS_DEBUG, "Socket %x Dct %x Channel %x " |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 549 | "DIMM organization miss-match\n", |
Martin Roth | 7675d8a | 2013-02-24 15:09:11 -0700 | [diff] [blame] | 550 | (unsigned int)event->DataParam1, |
| 551 | (unsigned int)event->DataParam2, |
| 552 | (unsigned int)event->DataParam3); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 553 | break; |
| 554 | |
| 555 | case MEM_ALERT_BK_INT_DIS: |
Martin Roth | 7675d8a | 2013-02-24 15:09:11 -0700 | [diff] [blame] | 556 | printk(BIOS_DEBUG, "Socket %x Dct %x Channel %x " |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 557 | "Bank interleaving disable for internal issue\n", |
Martin Roth | 7675d8a | 2013-02-24 15:09:11 -0700 | [diff] [blame] | 558 | (unsigned int)event->DataParam1, |
| 559 | (unsigned int)event->DataParam2, |
| 560 | (unsigned int)event->DataParam3); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 561 | break; |
| 562 | |
| 563 | case CPU_EVENT_BIST_ERROR: |
Martin Roth | 7675d8a | 2013-02-24 15:09:11 -0700 | [diff] [blame] | 564 | printk(BIOS_DEBUG, "BIST error: %x reported on Socket %x Core %x\n", |
| 565 | (unsigned int)event->DataParam1, |
| 566 | (unsigned int)event->DataParam2, |
| 567 | (unsigned int)event->DataParam3); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 568 | break; |
| 569 | |
| 570 | case HT_EVENT_HW_SYNCFLOOD: |
Martin Roth | 7675d8a | 2013-02-24 15:09:11 -0700 | [diff] [blame] | 571 | printk(BIOS_DEBUG, "HT_EVENT_DATA_HW_SYNCFLOOD error on Socket %x Link %x\n", |
| 572 | (unsigned int)event->DataParam1, |
| 573 | (unsigned int)event->DataParam2); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 574 | break; |
| 575 | |
| 576 | case HT_EVENT_HW_HTCRC: |
Martin Roth | 7675d8a | 2013-02-24 15:09:11 -0700 | [diff] [blame] | 577 | printk(BIOS_DEBUG, "HT_EVENT_HW_HTCRC error on Socket %x Link %x Lanemask:%x\n", |
| 578 | (unsigned int)event->DataParam1, |
| 579 | (unsigned int)event->DataParam2, |
| 580 | (unsigned int)event->DataParam3); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 581 | break; |
| 582 | |
| 583 | default: |
| 584 | break; |
| 585 | } |
| 586 | } |
| 587 | |
| 588 | /** |
| 589 | * |
| 590 | */ |
| 591 | static void agesa_warning(EVENT_PARAMS *event) |
| 592 | { |
| 593 | /* |
| 594 | if (event->EventInfo == CPU_EVENT_STACK_REENTRY) { |
| 595 | printk(BIOS_DEBUG, |
| 596 | "The stack has already been enabled and this is a |
| 597 | redundant invocation of AMD_ENABLE_STACK. There is no event logged and |
| 598 | no data values. The event sub-class is returned along with the status code\n"); |
| 599 | return; |
| 600 | } |
| 601 | */ |
| 602 | |
| 603 | switch (event->EventInfo >> 24) { |
| 604 | case 0x04: |
Martin Roth | 7675d8a | 2013-02-24 15:09:11 -0700 | [diff] [blame] | 605 | printk(BIOS_DEBUG, "Memory: Socket %x Dct %x Channel%x ", |
| 606 | (unsigned int)event->DataParam1, |
| 607 | (unsigned int)event->DataParam2, |
| 608 | (unsigned int)event->DataParam3); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 609 | break; |
| 610 | |
| 611 | case 0x08: |
| 612 | printk(BIOS_DEBUG, "Processor: "); |
| 613 | break; |
| 614 | |
| 615 | case 0x10: |
| 616 | printk(BIOS_DEBUG, "Hyper Transport: "); |
| 617 | break; |
| 618 | |
| 619 | default: |
| 620 | break; |
| 621 | } |
| 622 | |
| 623 | switch (event->EventInfo) { |
| 624 | case MEM_WARNING_UNSUPPORTED_QRDIMM: |
| 625 | printk(BIOS_DEBUG, "QR DIMMs detected but not supported\n"); |
| 626 | break; |
| 627 | |
| 628 | case MEM_WARNING_UNSUPPORTED_UDIMM: |
| 629 | printk(BIOS_DEBUG, "Unbuffered DIMMs detected but not supported\n"); |
| 630 | break; |
| 631 | |
| 632 | case MEM_WARNING_UNSUPPORTED_SODIMM: |
| 633 | printk(BIOS_DEBUG, "SO-DIMMs detected but not supported"); |
| 634 | break; |
| 635 | |
| 636 | case MEM_WARNING_UNSUPPORTED_X4DIMM: |
| 637 | printk(BIOS_DEBUG, "x4 DIMMs detected but not supported"); |
| 638 | break; |
| 639 | |
| 640 | case MEM_WARNING_UNSUPPORTED_RDIMM: |
| 641 | printk(BIOS_DEBUG, "Registered DIMMs detected but not supported"); |
| 642 | break; |
| 643 | |
| 644 | /* |
| 645 | case MEM_WARNING_UNSUPPORTED_LRDIMM: |
| 646 | printk(BIOS_DEBUG, "Load Reduced DIMMs detected but not supported"); |
| 647 | break; |
| 648 | */ |
| 649 | |
| 650 | case MEM_WARNING_NO_SPDTRC_FOUND: |
| 651 | printk(BIOS_DEBUG, "NO_SPDTRC_FOUND"); |
| 652 | break; |
| 653 | |
| 654 | case MEM_WARNING_EMP_NOT_SUPPORTED: |
| 655 | printk(BIOS_DEBUG, "Processor is not capable for EMP");// |
| 656 | break; |
| 657 | |
| 658 | case MEM_WARNING_EMP_CONFLICT: |
| 659 | printk(BIOS_DEBUG, "EMP cannot be enabled if channel interleaving bank interleaving, or bank swizzle is enabled\n");// |
| 660 | break; |
| 661 | |
| 662 | case MEM_WARNING_EMP_NOT_ENABLED: |
| 663 | printk(BIOS_DEBUG, "Memory size is not power of two\n");// |
| 664 | break; |
| 665 | |
| 666 | case MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED: |
| 667 | printk(BIOS_DEBUG, "MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED\n"); |
| 668 | break; |
| 669 | |
| 670 | case MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED: |
| 671 | printk(BIOS_DEBUG, "MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED\n"); |
| 672 | break; |
| 673 | |
| 674 | case MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED: |
| 675 | printk(BIOS_DEBUG, "MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED\n"); |
| 676 | break; |
| 677 | |
| 678 | case MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED: |
| 679 | printk(BIOS_DEBUG, "MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED\n"); |
| 680 | break; |
| 681 | |
| 682 | case MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED: |
| 683 | printk(BIOS_DEBUG, "MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED\n"); |
| 684 | break; |
| 685 | |
| 686 | /* |
| 687 | case MEM_WARNING_INITIAL_DDR3VOLT_NONZERO: |
| 688 | printk(BIOS_DEBUG, "MEM_WARNING_INITIAL_DDR3VOLT_NONZERO\n"); |
| 689 | break; |
| 690 | |
| 691 | case MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO: |
| 692 | printk(BIOS_DEBUG, "MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO\n"); |
| 693 | break; |
| 694 | */ |
| 695 | |
| 696 | case CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR: |
| 697 | printk(BIOS_DEBUG, "Allocation rule number that has been violated:"); |
| 698 | if ((event->EventInfo & 0x000000FF) == 0x01) { |
| 699 | printk(BIOS_DEBUG, "AGESA_CACHE_SIZE_REDUCED\n"); |
| 700 | } else if ((event->EventInfo & 0x000000FF) == 0x02) { |
| 701 | printk(BIOS_DEBUG, "AGESA_CACHE_REGIONS_ACROSS_1MB\n"); |
| 702 | } else if ((event->EventInfo & 0x000000FF) == 0x03) { |
| 703 | printk(BIOS_DEBUG, "AGESA_CACHE_REGIONS_ACROSS_4GB\n"); |
| 704 | } |
Martin Roth | 7675d8a | 2013-02-24 15:09:11 -0700 | [diff] [blame] | 705 | printk(BIOS_DEBUG, "cache region index:%x, start:%x size:%x\n", |
| 706 | (unsigned int)event->DataParam1, |
| 707 | (unsigned int)event->DataParam2, |
| 708 | (unsigned int)event->DataParam3); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 709 | break; |
| 710 | |
| 711 | case CPU_WARNING_ADJUSTED_LEVELING_MODE: |
| 712 | printk(BIOS_DEBUG, "CPU_WARNING_ADJUSTED_LEVELING_MODE " |
Martin Roth | 7675d8a | 2013-02-24 15:09:11 -0700 | [diff] [blame] | 713 | "requested: %x, actual level:%x\n", |
| 714 | (unsigned int)event->DataParam1, |
| 715 | (unsigned int)event->DataParam2); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 716 | break; |
| 717 | |
| 718 | case CPU_EVENT_PM_PSTATE_OVERCURRENT: |
| 719 | printk(BIOS_DEBUG, "CPU_EVENT_PM_PSTATE_OVERCURRENT " |
Martin Roth | 7675d8a | 2013-02-24 15:09:11 -0700 | [diff] [blame] | 720 | "Socket: %x, Pstate:%x\n", |
| 721 | (unsigned int)event->DataParam1, |
| 722 | (unsigned int)event->DataParam2); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 723 | break; |
| 724 | |
| 725 | case CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG: |
| 726 | printk(BIOS_DEBUG, "CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG\n"); |
| 727 | break; |
| 728 | |
| 729 | /* |
| 730 | case CPU_EVENT_UNKNOWN_PROCESSOR_REVISION: |
| 731 | printk(BIOS_DEBUG, "CPU_EVENT_UNKNOWN_PROCESSOR_REVISION, socket: %lx, cpuid:%lx\n", |
| 732 | event->DataParam1, |
| 733 | event->DataParam2); |
| 734 | break; |
| 735 | */ |
| 736 | |
| 737 | case HT_EVENT_OPT_REQUIRED_CAP_RETRY: |
Martin Roth | 7675d8a | 2013-02-24 15:09:11 -0700 | [diff] [blame] | 738 | printk(BIOS_DEBUG, "HT_EVENT_OPT_REQUIRED_CAP_RETRY, Socket %x Link %x Depth %x\n", |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 739 | event->DataParam1, |
| 740 | event->DataParam2, |
| 741 | event->DataParam3); |
| 742 | break; |
| 743 | |
| 744 | case HT_EVENT_OPT_REQUIRED_CAP_GEN3: |
Martin Roth | 7675d8a | 2013-02-24 15:09:11 -0700 | [diff] [blame] | 745 | printk(BIOS_DEBUG, "HT_EVENT_OPT_REQUIRED_CAP_GEN3, Socket %x Link %x Depth %x\n", |
| 746 | (unsigned int)event->DataParam1, |
| 747 | (unsigned int)event->DataParam2, |
| 748 | (unsigned int)event->DataParam3); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 749 | break; |
| 750 | |
| 751 | case HT_EVENT_OPT_UNUSED_LINKS: |
Martin Roth | 7675d8a | 2013-02-24 15:09:11 -0700 | [diff] [blame] | 752 | printk(BIOS_DEBUG, "HT_EVENT_OPT_UNUSED_LINKS, SocketA%x LinkA%x SocketB%x LinkB%x\n", |
| 753 | (unsigned int)event->DataParam1, |
| 754 | (unsigned int)event->DataParam2, |
| 755 | (unsigned int)event->DataParam3, |
| 756 | (unsigned int)event->DataParam4); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 757 | break; |
| 758 | |
| 759 | case HT_EVENT_OPT_LINK_PAIR_EXCEED: |
Martin Roth | 7675d8a | 2013-02-24 15:09:11 -0700 | [diff] [blame] | 760 | printk(BIOS_DEBUG, "HT_EVENT_OPT_LINK_PAIR_EXCEED, SocketA%x MasterLink%x SocketB%x AltLink%x\n", |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 761 | |
Martin Roth | 7675d8a | 2013-02-24 15:09:11 -0700 | [diff] [blame] | 762 | (unsigned int)event->DataParam1, |
| 763 | (unsigned int)event->DataParam2, |
| 764 | (unsigned int)event->DataParam3, |
| 765 | (unsigned int)event->DataParam4); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 766 | default: |
| 767 | break; |
| 768 | } |
| 769 | } |
| 770 | |
| 771 | /** |
| 772 | * |
| 773 | */ |
| 774 | static void agesa_error(EVENT_PARAMS *event) |
| 775 | { |
| 776 | |
| 777 | switch (event->EventInfo >> 24) { |
| 778 | case 0x04: |
Martin Roth | 7675d8a | 2013-02-24 15:09:11 -0700 | [diff] [blame] | 779 | printk(BIOS_DEBUG, "Memory: Socket %x Dct %x Channel%x ", |
| 780 | (unsigned int)event->DataParam1, |
| 781 | (unsigned int)event->DataParam2, |
| 782 | (unsigned int)event->DataParam3); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 783 | break; |
| 784 | |
| 785 | case 0x08: |
| 786 | printk(BIOS_DEBUG, "Processor: "); |
| 787 | break; |
| 788 | |
| 789 | case 0x10: |
| 790 | printk(BIOS_DEBUG, "Hyper Transport: "); |
| 791 | break; |
| 792 | |
| 793 | default: |
| 794 | break; |
| 795 | } |
| 796 | |
| 797 | switch (event->EventInfo) { |
| 798 | case MEM_ERROR_NO_DQS_POS_RD_WINDOW: |
| 799 | printk(BIOS_DEBUG, "No DQS Position window for RD DQS\n"); |
| 800 | break; |
| 801 | |
| 802 | case MEM_ERROR_SMALL_DQS_POS_RD_WINDOW: |
| 803 | printk(BIOS_DEBUG, "Small DQS Position window for RD DQS\n"); |
| 804 | break; |
| 805 | |
| 806 | case MEM_ERROR_NO_DQS_POS_WR_WINDOW: |
| 807 | printk(BIOS_DEBUG, "No DQS Position window for WR DQS\n"); |
| 808 | break; |
| 809 | |
| 810 | case MEM_ERROR_SMALL_DQS_POS_WR_WINDOW: |
| 811 | printk(BIOS_DEBUG, "Small DQS Position window for WR DQS\n"); |
| 812 | break; |
| 813 | |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 814 | case MEM_ERROR_DIMM_SPARING_NOT_ENABLED: |
| 815 | printk(BIOS_DEBUG, "DIMM sparing has not been enabled for an internal issues\n"); |
| 816 | break; |
| 817 | |
| 818 | case MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE: |
| 819 | printk(BIOS_DEBUG, "Receive Enable value is too large\n"); |
| 820 | break; |
| 821 | case MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW: |
| 822 | printk(BIOS_DEBUG, "There is no DQS receiver enable window\n"); |
| 823 | break; |
| 824 | |
| 825 | case MEM_ERROR_DRAM_ENABLED_TIME_OUT: |
| 826 | printk(BIOS_DEBUG, "Time out when polling DramEnabled bit\n"); |
| 827 | break; |
| 828 | |
| 829 | case MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT: |
| 830 | printk(BIOS_DEBUG, "Time out when polling DctAccessDone bit\n"); |
| 831 | break; |
| 832 | |
| 833 | case MEM_ERROR_SEND_CTRL_WORD_TIME_OUT: |
| 834 | printk(BIOS_DEBUG, "Time out when polling SendCtrlWord bit\n"); |
| 835 | break; |
| 836 | |
| 837 | case MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT: |
| 838 | printk(BIOS_DEBUG, "Time out when polling PrefDramTrainMode bit\n"); |
| 839 | break; |
| 840 | |
| 841 | case MEM_ERROR_ENTER_SELF_REF_TIME_OUT: |
| 842 | printk(BIOS_DEBUG, "Time out when polling EnterSelfRef bit\n"); |
| 843 | break; |
| 844 | |
| 845 | case MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT: |
| 846 | printk(BIOS_DEBUG, "Time out when polling FreqChgInProg bit\n"); |
| 847 | break; |
| 848 | |
| 849 | case MEM_ERROR_EXIT_SELF_REF_TIME_OUT: |
| 850 | printk(BIOS_DEBUG, "Time out when polling ExitSelfRef bit\n"); |
| 851 | break; |
| 852 | |
| 853 | case MEM_ERROR_SEND_MRS_CMD_TIME_OUT: |
| 854 | printk(BIOS_DEBUG, "Time out when polling SendMrsCmd bit\n"); |
| 855 | break; |
| 856 | |
| 857 | case MEM_ERROR_SEND_ZQ_CMD_TIME_OUT: |
| 858 | printk(BIOS_DEBUG, "Time out when polling SendZQCmd bit\n"); |
| 859 | break; |
| 860 | |
| 861 | case MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT: |
| 862 | printk(BIOS_DEBUG, "Time out when polling DctExtraAccessDone bit\n"); |
| 863 | break; |
| 864 | |
| 865 | case MEM_ERROR_MEM_CLR_BUSY_TIME_OUT: |
| 866 | printk(BIOS_DEBUG, "Time out when polling MemClrBusy bit\n"); |
| 867 | break; |
| 868 | |
| 869 | case MEM_ERROR_MEM_CLEARED_TIME_OUT: |
| 870 | printk(BIOS_DEBUG, "Time out when polling MemCleared bit\n"); |
| 871 | break; |
| 872 | |
| 873 | case MEM_ERROR_FLUSH_WR_TIME_OUT: |
| 874 | printk(BIOS_DEBUG, "Time out when polling FlushWr bit\n"); |
| 875 | break; |
| 876 | |
| 877 | case MEM_ERROR_MAX_LAT_NO_WINDOW: |
| 878 | printk(BIOS_DEBUG, "Fail to find pass during Max Rd Latency training\n"); |
| 879 | break; |
| 880 | |
| 881 | case MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL: |
| 882 | printk(BIOS_DEBUG, "Fail to launch training code on an AP\n"); |
| 883 | break; |
| 884 | |
| 885 | case MEM_ERROR_PARALLEL_TRAINING_TIME_OUT: |
| 886 | printk(BIOS_DEBUG, "Fail to finish parallel training\n"); |
| 887 | break; |
| 888 | |
| 889 | case MEM_ERROR_NO_ADDRESS_MAPPING: |
| 890 | printk(BIOS_DEBUG, "No address mapping found for a dimm\n"); |
| 891 | break; |
| 892 | |
| 893 | case MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT: |
| 894 | printk(BIOS_DEBUG, "There is no DQS receiver enable window and the value is equal to the largest value\n"); |
| 895 | break; |
| 896 | |
| 897 | case MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE: |
| 898 | printk(BIOS_DEBUG, "Receive Enable value is too large and is 1 less than limit\n"); |
| 899 | break; |
| 900 | |
| 901 | case MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR: |
| 902 | printk(BIOS_DEBUG, "SPD Checksum error for NV_SPDCHK_RESTRT\n"); |
| 903 | break; |
| 904 | |
| 905 | case MEM_ERROR_NO_CHIPSELECT: |
| 906 | printk(BIOS_DEBUG, "No chipselects found\n"); |
| 907 | break; |
| 908 | |
| 909 | case MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM: |
| 910 | printk(BIOS_DEBUG, "Unbuffered dimm is not supported at 333MHz\n"); |
| 911 | break; |
| 912 | |
| 913 | case MEM_ERROR_WL_PRE_OUT_OF_RANGE: |
| 914 | printk(BIOS_DEBUG, "Returned PRE value during write levelizzation was out of range\n"); |
| 915 | break; |
| 916 | |
| 917 | case CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE: |
| 918 | printk(BIOS_DEBUG, "No heap is allocated for BrandId structure\n"); |
| 919 | break; |
| 920 | |
| 921 | case CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED: |
| 922 | printk(BIOS_DEBUG, "Unable to load micro code patch\n"); |
| 923 | break; |
| 924 | |
| 925 | case CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE: |
| 926 | printk(BIOS_DEBUG, "No heap is allocated for the Pstate structure\n"); |
| 927 | break; |
| 928 | |
| 929 | /* |
| 930 | case CPU_ERROR_PM_NB_PSTATE_MISMATCH: |
| 931 | printk(BIOS_DEBUG, "NB P-state indicated by Index was disabled due to mismatch between processors\n"); |
| 932 | break; |
| 933 | */ |
| 934 | |
| 935 | case CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR: |
| 936 | printk(BIOS_DEBUG, "Allocation rule number that has been violated:"); |
| 937 | if ((event->EventInfo & 0x000000FF) == 0x04) { |
| 938 | printk(BIOS_DEBUG, "AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY\n"); |
| 939 | } else if ((event->EventInfo & 0x000000FF) == 0x05) { |
| 940 | printk(BIOS_DEBUG, "AGESA_START_ADDRESS_LESS_D0000\n"); |
| 941 | } else if ((event->EventInfo & 0x000000FF) == 0x06) { |
| 942 | printk(BIOS_DEBUG, "AGESA_THREE_CACHE_REGIONS_ABOVE_1MB\n"); |
| 943 | } else if ((event->EventInfo & 0x000000FF) == 0x07) { |
| 944 | printk(BIOS_DEBUG, "AGESA_DEALLOCATE_CACHE_REGIONS\n"); |
| 945 | } |
Martin Roth | 7675d8a | 2013-02-24 15:09:11 -0700 | [diff] [blame] | 946 | printk(BIOS_DEBUG, "cache region index:%x, start:%x size:%x\n", |
| 947 | (unsigned int)event->DataParam1, |
| 948 | (unsigned int)event->DataParam2, |
| 949 | (unsigned int)event->DataParam3); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 950 | break; |
| 951 | |
| 952 | case HT_EVENT_COH_NO_TOPOLOGY: |
Martin Roth | 7675d8a | 2013-02-24 15:09:11 -0700 | [diff] [blame] | 953 | printk(BIOS_DEBUG, "no Matching Topology was found during coherent initializatio TotalHtNodes: %x\n", |
| 954 | (unsigned int)event->DataParam1); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 955 | break; |
| 956 | |
| 957 | case HT_EVENT_NCOH_BUID_EXCEED: |
Martin Roth | 7675d8a | 2013-02-24 15:09:11 -0700 | [diff] [blame] | 958 | printk(BIOS_DEBUG, "there is a limit of 32 unit IDs per chain Socket%x Link%x Depth%x" |
| 959 | "Current BUID: %x, Unit Count: %x\n", |
| 960 | (unsigned int)event->DataParam1, |
| 961 | (unsigned int)event->DataParam2, |
| 962 | (unsigned int)event->DataParam3, |
| 963 | (unsigned int)event->DataParam4 >> 16, |
| 964 | (unsigned int)event->DataParam4 & 0x0000FFFF); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 965 | break; |
| 966 | |
| 967 | case HT_EVENT_NCOH_BUS_MAX_EXCEED: |
Martin Roth | 7675d8a | 2013-02-24 15:09:11 -0700 | [diff] [blame] | 968 | printk(BIOS_DEBUG, "maximum auto bus limit exceeded, Socket %x Link %x Bus %x\n", |
| 969 | (unsigned int)event->DataParam1, |
| 970 | (unsigned int)event->DataParam2, |
| 971 | (unsigned int)event->DataParam3); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 972 | break; |
| 973 | |
| 974 | case HT_EVENT_NCOH_CFG_MAP_EXCEED: |
Martin Roth | 7675d8a | 2013-02-24 15:09:11 -0700 | [diff] [blame] | 975 | printk(BIOS_DEBUG, "there is a limit of four non-coherent chains, Socket %x Link %x\n", |
| 976 | (unsigned int)event->DataParam1, |
| 977 | (unsigned int)event->DataParam2); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 978 | break; |
| 979 | |
| 980 | case HT_EVENT_NCOH_DEVICE_FAILED: |
| 981 | printk(BIOS_DEBUG, "after assigning an IO Device an ID, it does not respond at the new ID" |
Martin Roth | 7675d8a | 2013-02-24 15:09:11 -0700 | [diff] [blame] | 982 | "Socket %x Link %x Depth %x DeviceID %x\n", |
| 983 | (unsigned int)event->DataParam1, |
| 984 | (unsigned int)event->DataParam2, |
| 985 | (unsigned int)event->DataParam3, |
| 986 | (unsigned int)event->DataParam4); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 987 | default: |
| 988 | break; |
| 989 | } |
| 990 | } |
| 991 | /** |
| 992 | * |
| 993 | */ |
| 994 | static void agesa_critical(EVENT_PARAMS *event) |
| 995 | { |
| 996 | switch (event->EventInfo) { |
| 997 | case MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3: |
Martin Roth | 7675d8a | 2013-02-24 15:09:11 -0700 | [diff] [blame] | 998 | printk(BIOS_DEBUG, "Socket: %x, Heap allocation error for DMI table for DDR3\n", |
| 999 | (unsigned int)event->DataParam1); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 1000 | break; |
| 1001 | |
| 1002 | case MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2: |
Martin Roth | 7675d8a | 2013-02-24 15:09:11 -0700 | [diff] [blame] | 1003 | printk(BIOS_DEBUG, "Socket: %x, Heap allocation error for DMI table for DDR2\n", |
| 1004 | (unsigned int)event->DataParam1); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 1005 | break; |
| 1006 | |
| 1007 | case MEM_ERROR_UNSUPPORTED_DIMM_CONFIG: |
Martin Roth | 7675d8a | 2013-02-24 15:09:11 -0700 | [diff] [blame] | 1008 | printk(BIOS_DEBUG, "Socket: %x, Dimm population is not supported\n", |
| 1009 | (unsigned int)event->DataParam1); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 1010 | break; |
| 1011 | |
| 1012 | case HT_EVENT_COH_PROCESSOR_TYPE_MIX: |
Martin Roth | 7675d8a | 2013-02-24 15:09:11 -0700 | [diff] [blame] | 1013 | printk(BIOS_DEBUG, "Socket %x Link %x TotalSockets %x, HT_EVENT_COH_PROCESSOR_TYPE_MIX \n", |
| 1014 | (unsigned int)event->DataParam1, |
| 1015 | (unsigned int)event->DataParam2, |
| 1016 | (unsigned int)event->DataParam3); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 1017 | break; |
| 1018 | |
| 1019 | case HT_EVENT_COH_MPCAP_MISMATCH: |
Martin Roth | 7675d8a | 2013-02-24 15:09:11 -0700 | [diff] [blame] | 1020 | printk(BIOS_DEBUG, "Socket %x Link %x MpCap %x TotalSockets %x, HT_EVENT_COH_MPCAP_MISMATCH\n", |
| 1021 | (unsigned int)event->DataParam1, |
| 1022 | (unsigned int)event->DataParam2, |
| 1023 | (unsigned int)event->DataParam3, |
| 1024 | (unsigned int)event->DataParam4); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 1025 | default: |
| 1026 | break; |
| 1027 | } |
| 1028 | } |
| 1029 | |
| 1030 | /** |
| 1031 | * |
| 1032 | */ |
| 1033 | static void agesa_fatal(EVENT_PARAMS *event) |
| 1034 | { |
| 1035 | |
| 1036 | switch (event->EventInfo >> 24) { |
| 1037 | case 0x04: |
Martin Roth | 7675d8a | 2013-02-24 15:09:11 -0700 | [diff] [blame] | 1038 | printk(BIOS_DEBUG, "Memory: Socket %x Dct %x Channel%x ", |
| 1039 | (unsigned int)event->DataParam1, |
| 1040 | (unsigned int)event->DataParam2, |
| 1041 | (unsigned int)event->DataParam3); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 1042 | break; |
| 1043 | |
| 1044 | case 0x08: |
| 1045 | printk(BIOS_DEBUG, "Processor: "); |
| 1046 | break; |
| 1047 | |
| 1048 | case 0x10: |
| 1049 | printk(BIOS_DEBUG, "Hyper Transport: "); |
| 1050 | break; |
| 1051 | |
| 1052 | default: |
| 1053 | break; |
| 1054 | } |
| 1055 | |
| 1056 | switch (event->EventInfo) { |
| 1057 | case MEM_ERROR_MINIMUM_MODE: |
| 1058 | printk(BIOS_DEBUG, "Running in minimum mode\n"); |
| 1059 | break; |
| 1060 | |
| 1061 | case MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM: |
| 1062 | printk(BIOS_DEBUG, "DIMM modules are missmatched\n"); |
| 1063 | break; |
| 1064 | |
| 1065 | case MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM: |
| 1066 | printk(BIOS_DEBUG, "No DIMMs have been foun\n"); |
| 1067 | break; |
| 1068 | |
| 1069 | case MEM_ERROR_MISMATCH_DIMM_CLOCKS: |
| 1070 | printk(BIOS_DEBUG, "DIMM clocks miss-matched\n"); |
| 1071 | break; |
| 1072 | |
| 1073 | case MEM_ERROR_NO_CYC_TIME: |
| 1074 | printk(BIOS_DEBUG, "No cycle time found\n"); |
| 1075 | break; |
| 1076 | case MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS: |
| 1077 | printk(BIOS_DEBUG, "Heap allocation error with dynamic storing of trained timings\n"); |
| 1078 | break; |
| 1079 | |
| 1080 | case MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs: |
| 1081 | printk(BIOS_DEBUG, "Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT\n"); |
| 1082 | break; |
| 1083 | |
| 1084 | case MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV: |
| 1085 | printk(BIOS_DEBUG, "Heap allocation error with REMOTE_TRAINING_ENV\n"); |
| 1086 | break; |
| 1087 | |
| 1088 | case MEM_ERROR_HEAP_ALLOCATE_FOR_SPD: |
| 1089 | printk(BIOS_DEBUG, "Heap allocation error for SPD data\n"); |
| 1090 | break; |
| 1091 | |
| 1092 | case MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA: |
| 1093 | printk(BIOS_DEBUG, "Heap allocation error for RECEIVED_DATA during parallel training\n"); |
| 1094 | break; |
| 1095 | |
| 1096 | case MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS: |
| 1097 | printk(BIOS_DEBUG, "Heap allocation error for S3 \"SPECIAL_CASE_REGISTER\"\n"); |
| 1098 | break; |
| 1099 | |
| 1100 | case MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA: |
| 1101 | printk(BIOS_DEBUG, "Heap allocation error for Training Data\n"); |
| 1102 | break; |
| 1103 | |
| 1104 | case MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK: |
| 1105 | printk(BIOS_DEBUG, "Heap allocation error for DIMM Identify \"MEM_NB_BLOCK\"\n"); |
| 1106 | break; |
| 1107 | |
| 1108 | case MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM: |
| 1109 | printk(BIOS_DEBUG, "No Constructor for DIMM Identify\n"); |
| 1110 | break; |
| 1111 | |
| 1112 | case MEM_ERROR_VDDIO_UNSUPPORTED: |
| 1113 | printk(BIOS_DEBUG, "VDDIO of the dimms on the board is not supported\n"); |
| 1114 | break; |
| 1115 | |
| 1116 | case CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT: |
Martin Roth | 7675d8a | 2013-02-24 15:09:11 -0700 | [diff] [blame] | 1117 | printk(BIOS_DEBUG, "Socket: %x, All PStates exceeded the motherboard current limit on specified socket\n", |
| 1118 | (unsigned int)event->DataParam1); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 1119 | break; |
| 1120 | |
| 1121 | default: |
| 1122 | break; |
| 1123 | } |
| 1124 | } |
| 1125 | |
| 1126 | /** |
| 1127 | * |
| 1128 | * Interprte the agesa event log to an user readable string |
| 1129 | */ |
| 1130 | static void interpret_agesa_eventlog(EVENT_PARAMS *event) |
| 1131 | { |
| 1132 | switch (event->EventClass) { |
| 1133 | case AGESA_BOUNDS_CHK: |
| 1134 | agesa_bound_check(event); |
| 1135 | break; |
| 1136 | |
| 1137 | case AGESA_ALERT: |
| 1138 | agesa_alert(event); |
| 1139 | break; |
| 1140 | |
| 1141 | case AGESA_WARNING: |
| 1142 | agesa_warning(event); |
| 1143 | break; |
| 1144 | |
| 1145 | case AGESA_ERROR: |
| 1146 | agesa_error(event); |
| 1147 | break; |
| 1148 | |
| 1149 | case AGESA_CRITICAL: |
| 1150 | agesa_critical(event); |
| 1151 | break; |
| 1152 | |
| 1153 | case AGESA_FATAL: |
| 1154 | agesa_fatal(event); |
| 1155 | break; |
| 1156 | |
| 1157 | default: |
| 1158 | break; |
| 1159 | } |
| 1160 | } |
| 1161 | |
| 1162 | /** |
| 1163 | * @param HeapStatus -the current HeapStatus |
| 1164 | */ |
| 1165 | UINT32 agesawrapper_amdreadeventlog(UINT8 HeapStatus) |
| 1166 | { |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 1167 | printk(BIOS_DEBUG, "enter in %s\n", __func__); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 1168 | AGESA_STATUS Status; |
| 1169 | EVENT_PARAMS AmdEventParams; |
| 1170 | |
| 1171 | LibAmdMemFill(&AmdEventParams, |
| 1172 | 0, |
| 1173 | sizeof(EVENT_PARAMS), |
| 1174 | &(AmdEventParams.StdHeader)); |
| 1175 | |
| 1176 | AmdEventParams.StdHeader.AltImageBasePtr = 0; |
Aladyshev Konstantin | c855dce | 2012-12-19 05:53:53 +0400 | [diff] [blame] | 1177 | AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 1178 | AmdEventParams.StdHeader.Func = 0; |
| 1179 | AmdEventParams.StdHeader.ImageBasePtr = 0; |
| 1180 | /* I have to know the current HeapStatus to Locate the EventLogHeapPointer */ |
| 1181 | AmdEventParams.StdHeader.HeapStatus = HeapStatus; |
| 1182 | Status = AmdReadEventLog(&AmdEventParams); |
| 1183 | while (AmdEventParams.EventClass != 0) { |
Martin Roth | 7675d8a | 2013-02-24 15:09:11 -0700 | [diff] [blame] | 1184 | printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", |
| 1185 | (unsigned int)AmdEventParams.EventClass, |
| 1186 | (unsigned int)AmdEventParams.EventInfo); |
| 1187 | printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n", |
| 1188 | (unsigned int)AmdEventParams.DataParam1, |
| 1189 | (unsigned int)AmdEventParams.DataParam2); |
| 1190 | printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n", |
| 1191 | (unsigned int)AmdEventParams.DataParam3, |
| 1192 | (unsigned int)AmdEventParams.DataParam4); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 1193 | interpret_agesa_eventlog(&AmdEventParams); |
| 1194 | Status = AmdReadEventLog(&AmdEventParams); |
| 1195 | } |
| 1196 | |
Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame] | 1197 | printk(BIOS_DEBUG, "exit %s \n", __func__); |
efdesign98 | 95b6611 | 2011-07-20 13:23:04 -0600 | [diff] [blame] | 1198 | return (UINT32)Status; |
| 1199 | } |
| 1200 | |