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Uwe Hermann970d06b2007-09-21 15:56:05 +00001/*
Stefan Reinauer7e61e452008-01-18 10:35:56 +00002 * This file is part of the coreboot project.
Uwe Hermann970d06b2007-09-21 15:56:05 +00003 *
4 * Copyright (C) 2007 AMD
5 * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22#include <console/console.h>
23#include <arch/smp/mpspec.h>
24#include <device/pci.h>
25#include <string.h>
26#include <stdint.h>
27#include <cpu/amd/amdk8_sysconf.h>
28
Uwe Hermann970d06b2007-09-21 15:56:05 +000029extern unsigned char bus_mcp55[8]; // 1
30extern unsigned apicid_mcp55;
Uwe Hermann970d06b2007-09-21 15:56:05 +000031
Myles Watson08e0fb82010-03-22 16:33:25 +000032static void *smp_write_config_table(void *v)
Uwe Hermann970d06b2007-09-21 15:56:05 +000033{
Uwe Hermann970d06b2007-09-21 15:56:05 +000034 struct mp_config_table *mc;
35 unsigned int sbdn;
Patrick Georgi5244e1b2010-11-21 14:41:07 +000036 int i, j, bus_isa;
Uwe Hermann970d06b2007-09-21 15:56:05 +000037
38 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
Uwe Hermann970d06b2007-09-21 15:56:05 +000039
Patrick Georgic8feedd2012-02-16 18:43:25 +010040 mptable_init(mc, LOCAL_APIC_ADDR);
Uwe Hermann970d06b2007-09-21 15:56:05 +000041
42 smp_write_processors(mc);
43
44 get_bus_conf();
45 sbdn = sysconf.sbdn;
46
Patrick Georgi5244e1b2010-11-21 14:41:07 +000047 mptable_write_buses(mc, NULL, &bus_isa);
Uwe Hermann970d06b2007-09-21 15:56:05 +000048
49 /* I/O APICs: APIC ID Version State Address */
50 {
51 device_t dev;
52 struct resource *res;
53 uint32_t dword;
54
55 dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x1, 0));
56 if (dev) {
57 res = find_resource(dev, PCI_BASE_ADDRESS_1);
58 if (res)
59 smp_write_ioapic(mc, apicid_mcp55, 0x11, res->base);
60
61 dword = 0x43c6c643;
62 pci_write_config32(dev, 0x7c, dword);
63
64 dword = 0x81001a00;
65 pci_write_config32(dev, 0x80, dword);
66
67 dword = 0xd0001202;
68 pci_write_config32(dev, 0x84, dword);
69 }
70 }
71
Patrick Georgic5b87c82010-05-20 15:28:19 +000072 mptable_add_isa_interrupts(mc, bus_isa, apicid_mcp55, 0);
73
Uwe Hermann970d06b2007-09-21 15:56:05 +000074 /* I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */
Uwe Hermann970d06b2007-09-21 15:56:05 +000075 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 1) << 2) | 1, apicid_mcp55, 0xa);
76 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 2) << 2) | 0, apicid_mcp55, 0x16); // 22
77 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 2) << 2) | 1, apicid_mcp55, 0x17); // 23
78 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 6) << 2) | 1, apicid_mcp55, 0x17); // 23
79 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 5) << 2) | 0, apicid_mcp55, 0x14); // 20
80 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 5) << 2) | 1, apicid_mcp55, 0x17); // 23
81 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 5) << 2) | 2, apicid_mcp55, 0x15); // 21
82 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 8) << 2) | 0, apicid_mcp55, 0x16); // 22
83
84 for (j = 7; j >= 2; j--) {
85 if (!bus_mcp55[j])
86 continue;
87 for (i = 0; i < 4; i++)
88 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[j], (0x00 << 2) | i, apicid_mcp55, 0x10 + (2 + j + i + 4 - sbdn % 4) % 4);
89 }
90
91 for (j = 0; j < 2; j++) {
92 for (i = 0; i < 4; i++)
93 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[1], ((0x06 + j) << 2) | i, apicid_mcp55, 0x10 + (2 + i + j) % 4);
94 }
95
96 /* Local Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */
Patrick Georgi6eb7a532011-10-07 21:42:52 +020097 mptable_lintsrc(mc, bus_isa);
Uwe Hermann970d06b2007-09-21 15:56:05 +000098
99 /* There is no extension information... */
100
101 /* Compute the checksums. */
Patrick Georgib0a9c5c2011-10-07 23:01:55 +0200102 return mptable_finalize(mc);
Uwe Hermann970d06b2007-09-21 15:56:05 +0000103}
104
105unsigned long write_smp_table(unsigned long addr)
106{
107 void *v;
Patrick Georgic75c79b2011-10-07 22:41:07 +0200108 v = smp_write_floating_table(addr, 0);
Uwe Hermann970d06b2007-09-21 15:56:05 +0000109 return (unsigned long)smp_write_config_table(v);
110}