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review.coreboot.org / coreboot / f12e56181788387c560c9b8d0f3d61fce4a4333a / . / src / mainboard / msi / ms7260 / irq_tables.c
blob: df471267be83473a4331d658dc289984130ae225 [file] [log] [blame]
Uwe Hermann970d06b2007-09-21 15:56:05 +0000[diff] [blame]1/*
Stefan Reinauer7e61e452008-01-18 10:35:56 +0000[diff] [blame]2 * This file is part of the coreboot project.
Uwe Hermann970d06b2007-09-21 15:56:05 +0000[diff] [blame]3 *
4 * Copyright (C) 2007 AMD
5 * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22#include <console/console.h>
23#include <device/pci.h>
24#include <string.h>
25#include <stdint.h>
26#include <arch/pirq_routing.h>
27#include <cpu/amd/amdk8_sysconf.h>
28
29static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus,
30 uint8_t devfn, uint8_t link0, uint16_t bitmap0,
31 uint8_t link1, uint16_t bitmap1, uint8_t link2,
32 uint16_t bitmap2, uint8_t link3, uint16_t bitmap3,
33 uint8_t slot, uint8_t rfu)
34{
35 pirq_info->bus = bus;
36 pirq_info->devfn = devfn;
37 pirq_info->irq[0].link = link0;
38 pirq_info->irq[0].bitmap = bitmap0;
39 pirq_info->irq[1].link = link1;
40 pirq_info->irq[1].bitmap = bitmap1;
41 pirq_info->irq[2].link = link2;
42 pirq_info->irq[2].bitmap = bitmap2;
43 pirq_info->irq[3].link = link3;
44 pirq_info->irq[3].bitmap = bitmap3;
45 pirq_info->slot = slot;
46 pirq_info->rfu = rfu;
47}
48
Uwe Hermann970d06b2007-09-21 15:56:05 +0000[diff] [blame]49extern unsigned char bus_mcp55[8]; // 1
50
Uwe Hermann970d06b2007-09-21 15:56:05 +0000[diff] [blame]51unsigned long write_pirq_routing_table(unsigned long addr)
52{
53 struct irq_routing_table *pirq;
54 struct irq_info *pirq_info;
55 unsigned int slot_num, sbdn;
56 uint8_t *v;
57 uint8_t sum = 0;
58 int i;
59
60 /* Will find out all bus num and apic that share with mptable.c
61 * and mptable.c and acpi_tables.c.
62 */
63 get_bus_conf();
64 sbdn = sysconf.sbdn;
65
66 /* Align the table to be 16 byte aligned. */
67 addr += 15;
68 addr &= ~15;
69
70 /* This table must be betweeen 0xf0000 and 0x100000. */
Myles Watson08e0fb82010-03-22 16:33:25 +0000[diff] [blame]71 printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
Uwe Hermann970d06b2007-09-21 15:56:05 +0000[diff] [blame]72
73 pirq = (void *)(addr);
74 v = (uint8_t *)(addr);
75
76 pirq->signature = PIRQ_SIGNATURE;
77 pirq->version = PIRQ_VERSION;
78 pirq->rtr_bus = bus_mcp55[0];
79 pirq->rtr_devfn = ((sbdn + 6) << 3) | 0;
80 pirq->exclusive_irqs = 0;
81 pirq->rtr_vendor = 0x10de;
82 pirq->rtr_device = 0x0370; /* TODO: Hm, getpir suggests 0x0364 !? */
83 pirq->miniport_data = 0;
84
85 memset(pirq->rfu, 0, sizeof(pirq->rfu));
86
87 pirq_info = (void *)(&pirq->checksum + 1);
88 slot_num = 0;
89
90 /* PCI bridge (00:06.0) */
91 write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn + 6) << 3) | 0, 0x1,
92 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
93 pirq_info++;
94 slot_num++;
95
96 pirq->size = 32 + 16 * slot_num;
97
98 for (i = 0; i < pirq->size; i++)
99 sum += v[i];
100
101 sum = pirq->checksum - sum;
102
103 if (sum != pirq->checksum)
104 pirq->checksum = sum;
105
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000[diff] [blame]106 printk(BIOS_INFO, "done.\n");
Uwe Hermann970d06b2007-09-21 15:56:05 +0000[diff] [blame]107
108 return (unsigned long)pirq_info;
109}