Zheng Bao | 584ab84 | 2010-03-16 01:53:10 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | /* |
| 21 | DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 |
| 22 | ) |
| 23 | { |
| 24 | #include "routing.asl" |
| 25 | } |
| 26 | */ |
| 27 | |
| 28 | /* Routing is in System Bus scope */ |
| 29 | Scope(\_SB) { |
| 30 | Name(PR0, Package(){ |
| 31 | /* NB devices */ |
| 32 | /* Bus 0, Dev 0 - RS780 Host Controller */ |
| 33 | /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ |
Marc Jones | 94fa3db | 2012-01-13 14:39:48 -0700 | [diff] [blame] | 34 | Package(){0x0001FFFF, 0, INTC, 0 }, |
| 35 | Package(){0x0001FFFF, 1, INTD, 0 }, |
Zheng Bao | 584ab84 | 2010-03-16 01:53:10 +0000 | [diff] [blame] | 36 | /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ |
| 37 | Package(){0x0002FFFF, 0, INTC, 0 }, |
| 38 | Package(){0x0002FFFF, 1, INTD, 0 }, |
| 39 | Package(){0x0002FFFF, 2, INTA, 0 }, |
| 40 | Package(){0x0002FFFF, 3, INTB, 0 }, |
| 41 | /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ |
| 42 | /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ |
| 43 | Package(){0x0004FFFF, 0, INTA, 0 }, |
| 44 | Package(){0x0004FFFF, 1, INTB, 0 }, |
| 45 | Package(){0x0004FFFF, 2, INTC, 0 }, |
| 46 | Package(){0x0004FFFF, 3, INTD, 0 }, |
| 47 | /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ |
| 48 | /* Package(){0x0005FFFF, 0, INTB, 0 }, */ |
| 49 | /* Package(){0x0005FFFF, 1, INTC, 0 }, */ |
| 50 | /* Package(){0x0005FFFF, 2, INTD, 0 }, */ |
| 51 | /* Package(){0x0005FFFF, 3, INTA, 0 }, */ |
| 52 | /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ |
| 53 | Package(){0x0006FFFF, 0, INTC, 0 }, |
| 54 | Package(){0x0006FFFF, 1, INTD, 0 }, |
| 55 | Package(){0x0006FFFF, 2, INTA, 0 }, |
| 56 | Package(){0x0006FFFF, 3, INTB, 0 }, |
| 57 | /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ |
| 58 | Package(){0x0007FFFF, 0, INTD, 0 }, |
| 59 | Package(){0x0007FFFF, 1, INTA, 0 }, |
| 60 | Package(){0x0007FFFF, 2, INTB, 0 }, |
| 61 | Package(){0x0007FFFF, 3, INTC, 0 }, |
Marc Jones | 94fa3db | 2012-01-13 14:39:48 -0700 | [diff] [blame] | 62 | |
| 63 | Package(){0x0009FFFF, 0, INTB, 0 }, |
| 64 | Package(){0x0009FFFF, 1, INTC, 0 }, |
| 65 | Package(){0x0009FFFF, 2, INTD, 0 }, |
| 66 | Package(){0x0009FFFF, 3, INTA, 0 }, |
| 67 | |
| 68 | Package(){0x000AFFFF, 0, INTC, 0 }, |
| 69 | Package(){0x000AFFFF, 1, INTD, 0 }, |
| 70 | Package(){0x000AFFFF, 2, INTA, 0 }, |
| 71 | Package(){0x000AFFFF, 3, INTB, 0 }, |
| 72 | |
| 73 | Package(){0x000BFFFF, 0, INTD, 0 }, |
| 74 | Package(){0x000BFFFF, 1, INTA, 0 }, |
| 75 | Package(){0x000BFFFF, 2, INTB, 0 }, |
| 76 | Package(){0x000BFFFF, 3, INTC, 0 }, |
| 77 | |
| 78 | Package(){0x000CFFFF, 0, INTA, 0 }, |
| 79 | Package(){0x000CFFFF, 1, INTB, 0 }, |
| 80 | Package(){0x000CFFFF, 2, INTC, 0 }, |
| 81 | Package(){0x000CFFFF, 3, INTD, 0 }, |
| 82 | |
Zheng Bao | 584ab84 | 2010-03-16 01:53:10 +0000 | [diff] [blame] | 83 | /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ |
| 84 | |
| 85 | /* SB devices */ |
| 86 | /* Bus 0, Dev 17 - SATA controller #2 */ |
| 87 | /* Bus 0, Dev 18 - SATA controller #1 */ |
Marc Jones | 94fa3db | 2012-01-13 14:39:48 -0700 | [diff] [blame] | 88 | Package(){0x0011FFFF, 0, INTG, 0 }, |
Zheng Bao | 584ab84 | 2010-03-16 01:53:10 +0000 | [diff] [blame] | 89 | |
| 90 | /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; |
| 91 | * EHCI, dev 18, 19 func 2 */ |
| 92 | Package(){0x0012FFFF, 0, INTA, 0 }, |
| 93 | Package(){0x0012FFFF, 1, INTB, 0 }, |
| 94 | Package(){0x0012FFFF, 2, INTC, 0 }, |
Marc Jones | 94fa3db | 2012-01-13 14:39:48 -0700 | [diff] [blame] | 95 | Package(){0x0012FFFF, 3, INTD, 0 }, |
Zheng Bao | 584ab84 | 2010-03-16 01:53:10 +0000 | [diff] [blame] | 96 | |
| 97 | Package(){0x0013FFFF, 0, INTC, 0 }, |
| 98 | Package(){0x0013FFFF, 1, INTD, 0 }, |
| 99 | Package(){0x0013FFFF, 2, INTA, 0 }, |
Marc Jones | 94fa3db | 2012-01-13 14:39:48 -0700 | [diff] [blame] | 100 | Package(){0x0013FFFF, 3, INTB, 0 }, |
Zheng Bao | 584ab84 | 2010-03-16 01:53:10 +0000 | [diff] [blame] | 101 | |
| 102 | /* Package(){0x0014FFFF, 1, INTA, 0 }, */ |
| 103 | |
| 104 | /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ |
| 105 | Package(){0x0014FFFF, 0, INTA, 0 }, |
| 106 | Package(){0x0014FFFF, 1, INTB, 0 }, |
| 107 | Package(){0x0014FFFF, 2, INTC, 0 }, |
| 108 | Package(){0x0014FFFF, 3, INTD, 0 }, |
Marc Jones | 94fa3db | 2012-01-13 14:39:48 -0700 | [diff] [blame] | 109 | |
| 110 | /* Package(){0x0015FFFF, 0, INTA, 0 }, |
| 111 | Package(){0x0015FFFF, 1, INTB, 0 }, |
| 112 | Package(){0x0015FFFF, 2, INTC, 0 }, |
| 113 | Package(){0x0015FFFF, 3, INTD, 0 }, |
| 114 | */ |
Zheng Bao | 584ab84 | 2010-03-16 01:53:10 +0000 | [diff] [blame] | 115 | }) |
| 116 | |
| 117 | Name(APR0, Package(){ |
| 118 | /* NB devices in APIC mode */ |
| 119 | /* Bus 0, Dev 0 - RS780 Host Controller */ |
| 120 | |
| 121 | /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ |
| 122 | /* Package(){0x0001FFFF, 0, 0, 18 }, */ |
| 123 | /* package(){0x0001FFFF, 1, 0, 19 }, */ |
| 124 | |
| 125 | /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ |
| 126 | Package(){0x0002FFFF, 0, 0, 18 }, |
| 127 | /* Package(){0x0002FFFF, 1, 0, 19 }, */ |
| 128 | /* Package(){0x0002FFFF, 2, 0, 16 }, */ |
| 129 | /* Package(){0x0002FFFF, 3, 0, 17 }, */ |
| 130 | |
| 131 | /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ |
| 132 | Package(){0x0003FFFF, 0, 0, 19 }, |
| 133 | |
| 134 | /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ |
| 135 | Package(){0x0004FFFF, 0, 0, 16 }, |
| 136 | /* Package(){0x0004FFFF, 1, 0, 17 }, */ |
| 137 | /* Package(){0x0004FFFF, 2, 0, 18 }, */ |
| 138 | /* Package(){0x0004FFFF, 3, 0, 19 }, */ |
| 139 | |
| 140 | /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ |
| 141 | /* Package(){0x0005FFFF, 0, 0, 17 }, */ |
| 142 | /* Package(){0x0005FFFF, 1, 0, 18 }, */ |
| 143 | /* Package(){0x0005FFFF, 2, 0, 19 }, */ |
| 144 | /* Package(){0x0005FFFF, 3, 0, 16 }, */ |
| 145 | |
| 146 | /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ |
| 147 | /* Package(){0x0006FFFF, 0, 0, 18 }, */ |
| 148 | /* Package(){0x0006FFFF, 1, 0, 19 }, */ |
| 149 | /* Package(){0x0006FFFF, 2, 0, 16 }, */ |
| 150 | /* Package(){0x0006FFFF, 3, 0, 17 }, */ |
| 151 | |
| 152 | /* Bus 0, Dev 7 - PCIe Bridge for network card */ |
| 153 | /* Package(){0x0007FFFF, 0, 0, 19 }, */ |
| 154 | /* Package(){0x0007FFFF, 1, 0, 16 }, */ |
| 155 | /* Package(){0x0007FFFF, 2, 0, 17 }, */ |
| 156 | /* Package(){0x0007FFFF, 3, 0, 18 }, */ |
| 157 | |
| 158 | /* Bus 0, Dev 9 - PCIe Bridge for network card */ |
| 159 | Package(){0x0009FFFF, 0, 0, 17 }, |
| 160 | /* Package(){0x0009FFFF, 1, 0, 16 }, */ |
| 161 | /* Package(){0x0009FFFF, 2, 0, 17 }, */ |
| 162 | /* Package(){0x0009FFFF, 3, 0, 18 }, */ |
Marc Jones | 94fa3db | 2012-01-13 14:39:48 -0700 | [diff] [blame] | 163 | |
Zheng Bao | 584ab84 | 2010-03-16 01:53:10 +0000 | [diff] [blame] | 164 | /* Bus 0, Dev A - PCIe Bridge for network card */ |
| 165 | Package(){0x000AFFFF, 0, 0, 18 }, |
| 166 | /* Package(){0x000AFFFF, 1, 0, 16 }, */ |
| 167 | /* Package(){0x000AFFFF, 2, 0, 17 }, */ |
| 168 | /* Package(){0x000AFFFF, 3, 0, 18 }, */ |
Marc Jones | 94fa3db | 2012-01-13 14:39:48 -0700 | [diff] [blame] | 169 | |
Zheng Bao | 584ab84 | 2010-03-16 01:53:10 +0000 | [diff] [blame] | 170 | /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ |
| 171 | |
| 172 | /* SB devices in APIC mode */ |
| 173 | /* Bus 0, Dev 17 - SATA controller #2 */ |
| 174 | /* Bus 0, Dev 18 - SATA controller #1 */ |
| 175 | Package(){0x0011FFFF, 0, 0, 22 }, |
| 176 | |
| 177 | /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; |
| 178 | * EHCI, dev 18, 19 func 2 */ |
| 179 | Package(){0x0012FFFF, 0, 0, 16 }, |
| 180 | Package(){0x0012FFFF, 1, 0, 17 }, |
| 181 | Package(){0x0012FFFF, 2, 0, 18 }, |
Marc Jones | 94fa3db | 2012-01-13 14:39:48 -0700 | [diff] [blame] | 182 | Package(){0x0012FFFF, 3, 0, 19 }, |
Zheng Bao | 584ab84 | 2010-03-16 01:53:10 +0000 | [diff] [blame] | 183 | |
| 184 | Package(){0x0013FFFF, 0, 0, 18 }, |
| 185 | Package(){0x0013FFFF, 1, 0, 19 }, |
| 186 | Package(){0x0013FFFF, 2, 0, 16 }, |
Marc Jones | 94fa3db | 2012-01-13 14:39:48 -0700 | [diff] [blame] | 187 | Package(){0x0013FFFF, 3, 0, 17 }, |
Zheng Bao | 584ab84 | 2010-03-16 01:53:10 +0000 | [diff] [blame] | 188 | |
| 189 | /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ |
| 190 | Package(){0x0014FFFF, 0, 0, 16 }, |
| 191 | Package(){0x0014FFFF, 1, 0, 17 }, |
| 192 | Package(){0x0014FFFF, 2, 0, 18 }, |
| 193 | Package(){0x0014FFFF, 3, 0, 19 }, |
Zheng Bao | 584ab84 | 2010-03-16 01:53:10 +0000 | [diff] [blame] | 194 | }) |
| 195 | |
| 196 | Name(PR1, Package(){ |
| 197 | /* Internal graphics - RS780 VGA, Bus1, Dev5 */ |
Marc Jones | 94fa3db | 2012-01-13 14:39:48 -0700 | [diff] [blame] | 198 | Package(){0x0005FFFF, 0, INTC, 0 }, |
| 199 | Package(){0x0005FFFF, 1, INTD, 0 }, |
| 200 | Package(){0x0005FFFF, 2, INTA, 0 }, |
| 201 | Package(){0x0005FFFF, 3, INTB, 0 }, |
Zheng Bao | 584ab84 | 2010-03-16 01:53:10 +0000 | [diff] [blame] | 202 | }) |
| 203 | |
| 204 | Name(APR1, Package(){ |
| 205 | /* Internal graphics - RS780 VGA, Bus1, Dev5 */ |
| 206 | Package(){0x0005FFFF, 0, 0, 18 }, |
| 207 | Package(){0x0005FFFF, 1, 0, 19 }, |
Marc Jones | 94fa3db | 2012-01-13 14:39:48 -0700 | [diff] [blame] | 208 | Package(){0x0005FFFF, 2, 0, 16 }, |
| 209 | Package(){0x0005FFFF, 3, 0, 17 }, |
Zheng Bao | 584ab84 | 2010-03-16 01:53:10 +0000 | [diff] [blame] | 210 | }) |
| 211 | |
| 212 | Name(PS2, Package(){ |
| 213 | /* The external GFX - Hooked to PCIe slot 2 */ |
| 214 | Package(){0x0000FFFF, 0, INTC, 0 }, |
| 215 | Package(){0x0000FFFF, 1, INTD, 0 }, |
| 216 | Package(){0x0000FFFF, 2, INTA, 0 }, |
| 217 | Package(){0x0000FFFF, 3, INTB, 0 }, |
| 218 | }) |
| 219 | |
| 220 | Name(APS2, Package(){ |
| 221 | /* The external GFX - Hooked to PCIe slot 2 */ |
| 222 | Package(){0x0000FFFF, 0, 0, 18 }, |
| 223 | Package(){0x0000FFFF, 1, 0, 19 }, |
| 224 | Package(){0x0000FFFF, 2, 0, 16 }, |
| 225 | Package(){0x0000FFFF, 3, 0, 17 }, |
| 226 | }) |
| 227 | |
| 228 | Name(PS4, Package(){ |
| 229 | /* PCIe slot - Hooked to PCIe slot 4 */ |
Marc Jones | 94fa3db | 2012-01-13 14:39:48 -0700 | [diff] [blame] | 230 | Package(){0x0000FFFF, 0, INTD, 0 }, |
| 231 | Package(){0x0000FFFF, 1, INTA, 0 }, |
| 232 | Package(){0x0000FFFF, 2, INTB, 0 }, |
| 233 | Package(){0x0000FFFF, 3, INTC, 0 }, |
Zheng Bao | 584ab84 | 2010-03-16 01:53:10 +0000 | [diff] [blame] | 234 | }) |
| 235 | |
| 236 | Name(APS4, Package(){ |
| 237 | /* PCIe slot - Hooked to PCIe slot 4 */ |
| 238 | Package(){0x0000FFFF, 0, 0, 16 }, |
| 239 | Package(){0x0000FFFF, 1, 0, 17 }, |
| 240 | Package(){0x0000FFFF, 2, 0, 18 }, |
| 241 | Package(){0x0000FFFF, 3, 0, 19 }, |
| 242 | }) |
| 243 | |
| 244 | Name(PS5, Package(){ |
| 245 | /* PCIe slot - Hooked to PCIe slot 5 */ |
| 246 | Package(){0x0000FFFF, 0, INTB, 0 }, |
| 247 | Package(){0x0000FFFF, 1, INTC, 0 }, |
| 248 | Package(){0x0000FFFF, 2, INTD, 0 }, |
| 249 | Package(){0x0000FFFF, 3, INTA, 0 }, |
| 250 | }) |
| 251 | |
| 252 | Name(APS5, Package(){ |
| 253 | /* PCIe slot - Hooked to PCIe slot 5 */ |
| 254 | Package(){0x0000FFFF, 0, 0, 17 }, |
| 255 | Package(){0x0000FFFF, 1, 0, 18 }, |
| 256 | Package(){0x0000FFFF, 2, 0, 19 }, |
| 257 | Package(){0x0000FFFF, 3, 0, 16 }, |
| 258 | }) |
| 259 | |
| 260 | Name(PS6, Package(){ |
| 261 | /* PCIe slot - Hooked to PCIe slot 6 */ |
| 262 | Package(){0x0000FFFF, 0, INTC, 0 }, |
| 263 | Package(){0x0000FFFF, 1, INTD, 0 }, |
| 264 | Package(){0x0000FFFF, 2, INTA, 0 }, |
| 265 | Package(){0x0000FFFF, 3, INTB, 0 }, |
| 266 | }) |
| 267 | |
| 268 | Name(APS6, Package(){ |
| 269 | /* PCIe slot - Hooked to PCIe slot 6 */ |
| 270 | Package(){0x0000FFFF, 0, 0, 18 }, |
| 271 | Package(){0x0000FFFF, 1, 0, 19 }, |
| 272 | Package(){0x0000FFFF, 2, 0, 16 }, |
| 273 | Package(){0x0000FFFF, 3, 0, 17 }, |
| 274 | }) |
| 275 | |
| 276 | Name(PS7, Package(){ |
| 277 | /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ |
| 278 | Package(){0x0000FFFF, 0, INTD, 0 }, |
| 279 | Package(){0x0000FFFF, 1, INTA, 0 }, |
| 280 | Package(){0x0000FFFF, 2, INTB, 0 }, |
| 281 | Package(){0x0000FFFF, 3, INTC, 0 }, |
| 282 | }) |
| 283 | |
| 284 | Name(APS7, Package(){ |
| 285 | /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ |
| 286 | Package(){0x0000FFFF, 0, 0, 19 }, |
| 287 | Package(){0x0000FFFF, 1, 0, 16 }, |
| 288 | Package(){0x0000FFFF, 2, 0, 17 }, |
| 289 | Package(){0x0000FFFF, 3, 0, 18 }, |
| 290 | }) |
| 291 | Name(PS9, Package(){ |
| 292 | /* PCIe slot - Hooked to PCIe slot 9 */ |
| 293 | Package(){0x0000FFFF, 0, INTD, 0 }, |
| 294 | Package(){0x0000FFFF, 1, INTA, 0 }, |
| 295 | Package(){0x0000FFFF, 2, INTB, 0 }, |
| 296 | Package(){0x0000FFFF, 3, INTC, 0 }, |
| 297 | }) |
| 298 | |
| 299 | Name(APS9, Package(){ |
| 300 | /* PCIe slot - Hooked to PCIe slot 9 */ |
Marc Jones | 94fa3db | 2012-01-13 14:39:48 -0700 | [diff] [blame] | 301 | Package(){0x0000FFFF, 0, 0, 19 }, |
| 302 | Package(){0x0000FFFF, 1, 0, 16 }, |
| 303 | Package(){0x0000FFFF, 2, 0, 17 }, |
| 304 | Package(){0x0000FFFF, 3, 0, 18 }, |
Zheng Bao | 584ab84 | 2010-03-16 01:53:10 +0000 | [diff] [blame] | 305 | }) |
| 306 | Name(PSa, Package(){ |
| 307 | /* PCIe slot - Hooked to PCIe slot 10 */ |
| 308 | Package(){0x0000FFFF, 0, INTD, 0 }, |
| 309 | Package(){0x0000FFFF, 1, INTA, 0 }, |
| 310 | Package(){0x0000FFFF, 2, INTB, 0 }, |
| 311 | Package(){0x0000FFFF, 3, INTC, 0 }, |
| 312 | }) |
| 313 | |
| 314 | Name(APSa, Package(){ |
| 315 | /* PCIe slot - Hooked to PCIe slot 10 */ |
| 316 | Package(){0x0000FFFF, 0, 0, 18 }, |
Marc Jones | 94fa3db | 2012-01-13 14:39:48 -0700 | [diff] [blame] | 317 | Package(){0x0000FFFF, 1, 0, 16 }, |
| 318 | Package(){0x0000FFFF, 2, 0, 17 }, |
| 319 | Package(){0x0000FFFF, 3, 0, 18 }, |
Zheng Bao | 584ab84 | 2010-03-16 01:53:10 +0000 | [diff] [blame] | 320 | }) |
| 321 | |
| 322 | Name(PCIB, Package(){ |
| 323 | /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ |
| 324 | Package(){0x0005FFFF, 0, 0, 0x14 }, |
| 325 | Package(){0x0005FFFF, 1, 0, 0x15 }, |
| 326 | Package(){0x0005FFFF, 2, 0, 0x16 }, |
| 327 | Package(){0x0005FFFF, 3, 0, 0x17 }, |
| 328 | Package(){0x0006FFFF, 0, 0, 0x15 }, |
| 329 | Package(){0x0006FFFF, 1, 0, 0x16 }, |
| 330 | Package(){0x0006FFFF, 2, 0, 0x17 }, |
| 331 | Package(){0x0006FFFF, 3, 0, 0x14 }, |
| 332 | Package(){0x0007FFFF, 0, 0, 0x16 }, |
| 333 | Package(){0x0007FFFF, 1, 0, 0x17 }, |
| 334 | Package(){0x0007FFFF, 2, 0, 0x14 }, |
| 335 | Package(){0x0007FFFF, 3, 0, 0x15 }, |
| 336 | }) |
| 337 | } |