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review.coreboot.org / coreboot / f12e56181788387c560c9b8d0f3d61fce4a4333a / . / src / mainboard / amd / bimini_fam10 / mptable.c
blob: ec60b35a1db2d571f7d6557b254413bf91131c14 [file] [log] [blame]
Zheng Bao8210e892011-01-20 05:29:37 +0000[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20#include <console/console.h>
21#include <arch/smp/mpspec.h>
22#include <device/pci.h>
23#include <arch/io.h>
24#include <string.h>
25#include <stdint.h>
26#include <southbridge/amd/sb800/sb800.h>
27#include <cpu/amd/amdfam10_sysconf.h>
28
29extern int bus_isa;
30extern u8 bus_rs780[11];
31extern u8 bus_sb800[2];
32extern u32 apicid_sb800;
33extern u32 bus_type[256];
34extern u32 sbdn_rs780;
35extern u32 sbdn_sb800;
36
37u8 intr_data[] = {
38 [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
39 [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
40 [0x10] = 0x1F,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
41 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
42 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
43 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
44 0x10,0x11,0x12,0x13
45};
46
47static void *smp_write_config_table(void *v)
48{
49 struct mp_config_table *mc;
50 u32 dword;
51 u8 byte;
52
53 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
54
Patrick Georgic8feedd2012-02-16 18:43:25 +0100[diff] [blame]55 mptable_init(mc, LOCAL_APIC_ADDR);
Zheng Bao8210e892011-01-20 05:29:37 +0000[diff] [blame]56
57 smp_write_processors(mc);
58
59 get_bus_conf();
60
61 mptable_write_buses(mc, NULL, &bus_isa);
62
63 /* I/O APICs: APIC ID Version State Address */
64
65 dword = 0;
66 dword = pm_ioread(0x34) & 0xF0;
67 dword |= (pm_ioread(0x35) & 0xFF) << 8;
68 dword |= (pm_ioread(0x36) & 0xFF) << 16;
69 dword |= (pm_ioread(0x37) & 0xFF) << 24;
70 smp_write_ioapic(mc, apicid_sb800, 0x11, dword);
71
72 for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
73 outb(byte | 0x80, 0xC00);
74 outb(intr_data[byte], 0xC01);
75 }
76
77 /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
78#define IO_LOCAL_INT(type, intr, apicid, pin) \
79 smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
80
81 mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
82
83 /* PCI interrupts are level triggered, and are
84 * associated with a specific bus/device/function tuple.
85 */
Patrick Georgie1667822012-05-05 15:29:32 +0200[diff] [blame]86#if !CONFIG_GENERATE_ACPI_TABLES
Zheng Bao8210e892011-01-20 05:29:37 +0000[diff] [blame]87#define PCI_INT(bus, dev, fn, pin) \
88 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
89#else
90#define PCI_INT(bus, dev, fn, pin)
91#endif
92
93 PCI_INT(0x0, 0x14, 0x0, 0x10);
94 /* HD Audio: */
95 PCI_INT(0x0, 0x14, 0x2, 0x12);
96
97 PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
98 PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
99 PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
100 PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
101 PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
102 PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
103
104 /* sata */
105 PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
106
107 /* on board NIC & Slot PCIE. */
108 /* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */
109/* PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */
110 PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); /* Dev 2, external GFX */
111 /* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */
112 PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10);
113 /* configuration B doesnt need dev 5,6,7 */
114 /*
115 * PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11);
116 * PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12);
117 * PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13);
118 */
119 PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11);
120 PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); /* NIC */
121
122 /* PCI slots */
123 /* PCI_SLOT 0. */
124 PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
125 PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
126 PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
127 PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
128
129 /* PCI_SLOT 1. */
130 PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
131 PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
132 PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
133 PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
134
135 /* PCI_SLOT 2. */
136 PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
137 PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
138 PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
139 PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
140
141 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
142 IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
143 IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
144 /* There is no extension information... */
145
146 /* Compute the checksums */
Patrick Georgib0a9c5c2011-10-07 23:01:55 +0200[diff] [blame]147 return mptable_finalize(mc);
Zheng Bao8210e892011-01-20 05:29:37 +0000[diff] [blame]148}
149
150unsigned long write_smp_table(unsigned long addr)
151{
152 void *v;
Patrick Georgic75c79b2011-10-07 22:41:07 +0200[diff] [blame]153 v = smp_write_floating_table(addr, 0);
Zheng Bao8210e892011-01-20 05:29:37 +0000[diff] [blame]154 return (unsigned long)smp_write_config_table(v);
155}