Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
| 2 | |
| 3 | config SOC_AMD_CEZANNE |
| 4 | bool |
| 5 | help |
| 6 | AMD Cezanne support |
| 7 | |
| 8 | if SOC_AMD_CEZANNE |
| 9 | |
| 10 | config SOC_SPECIFIC_OPTIONS |
| 11 | def_bool y |
| 12 | select ARCH_BOOTBLOCK_X86_32 |
| 13 | select ARCH_VERSTAGE_X86_32 |
| 14 | select ARCH_ROMSTAGE_X86_32 |
| 15 | select ARCH_RAMSTAGE_X86_32 |
Felix Held | 44f4153 | 2020-12-09 02:01:16 +0100 | [diff] [blame] | 16 | select HAVE_CF9_RESET |
Felix Held | cb97734 | 2021-01-19 20:36:38 +0100 | [diff] [blame] | 17 | select IDT_IN_EVERY_STAGE |
Felix Held | 4be064a | 2020-12-08 17:21:04 +0100 | [diff] [blame] | 18 | select IOAPIC |
Felix Held | 8d0a609 | 2021-01-14 01:40:50 +0100 | [diff] [blame] | 19 | select PLATFORM_USES_FSP2_0 |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 20 | select RESET_VECTOR_IN_RAM |
| 21 | select SOC_AMD_COMMON |
Felix Held | 64de2c1 | 2020-12-05 20:53:59 +0100 | [diff] [blame] | 22 | select SOC_AMD_COMMON_BLOCK_ACPIMMIO |
Felix Held | 62ef88f | 2020-12-08 23:18:19 +0100 | [diff] [blame] | 23 | select SOC_AMD_COMMON_BLOCK_AOAC |
Felix Held | 07462ef | 2020-12-11 15:55:45 +0100 | [diff] [blame] | 24 | select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 25 | select SOC_AMD_COMMON_BLOCK_NONCAR |
| 26 | select SOC_AMD_COMMON_BLOCK_PCI_MMCONF |
Felix Held | 4be064a | 2020-12-08 17:21:04 +0100 | [diff] [blame] | 27 | select SOC_AMD_COMMON_BLOCK_SMBUS |
Zheng Bao | 02a5ddd | 2020-12-15 22:16:51 +0800 | [diff] [blame] | 28 | select SOC_AMD_COMMON_BLOCK_SMI |
Felix Held | 65783fb | 2020-12-04 17:38:46 +0100 | [diff] [blame] | 29 | select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H |
Felix Held | 8a3d4d5 | 2021-01-13 03:06:21 +0100 | [diff] [blame] | 30 | select SOC_AMD_COMMON_BLOCK_UART |
Felix Held | 8d0a609 | 2021-01-14 01:40:50 +0100 | [diff] [blame] | 31 | select UDK_2017_BINDING |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 32 | |
Furquan Shaikh | 696f4ea | 2021-01-08 11:48:52 -0800 | [diff] [blame] | 33 | config CHIPSET_DEVICETREE |
| 34 | string |
| 35 | default "soc/amd/cezanne/chipset.cb" |
| 36 | |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 37 | config EARLY_RESERVED_DRAM_BASE |
| 38 | hex |
| 39 | default 0x2000000 |
| 40 | help |
| 41 | This variable defines the base address of the DRAM which is reserved |
| 42 | for usage by coreboot in early stages (i.e. before ramstage is up). |
| 43 | This memory gets reserved in BIOS tables to ensure that the OS does |
| 44 | not use it, thus preventing corruption of OS memory in case of S3 |
| 45 | resume. |
| 46 | |
| 47 | config EARLYRAM_BSP_STACK_SIZE |
| 48 | hex |
| 49 | default 0x1000 |
| 50 | |
| 51 | config PSP_APOB_DRAM_ADDRESS |
| 52 | hex |
| 53 | default 0x2001000 |
| 54 | help |
| 55 | Location in DRAM where the PSP will copy the AGESA PSP Output |
| 56 | Block. |
| 57 | |
| 58 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 59 | hex |
| 60 | default 0x1600 |
| 61 | help |
| 62 | Increase this value if preram cbmem console is getting truncated |
| 63 | |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 64 | config C_ENV_BOOTBLOCK_SIZE |
| 65 | hex |
| 66 | default 0x10000 |
| 67 | help |
| 68 | Sets the size of the bootblock stage that should be loaded in DRAM. |
| 69 | This variable controls the DRAM allocation size in linker script |
| 70 | for bootblock stage. |
| 71 | |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 72 | config ROMSTAGE_ADDR |
| 73 | hex |
| 74 | default 0x2040000 |
| 75 | help |
| 76 | Sets the address in DRAM where romstage should be loaded. |
| 77 | |
| 78 | config ROMSTAGE_SIZE |
| 79 | hex |
| 80 | default 0x80000 |
| 81 | help |
| 82 | Sets the size of DRAM allocation for romstage in linker script. |
| 83 | |
| 84 | config FSP_M_ADDR |
| 85 | hex |
| 86 | default 0x20C0000 |
| 87 | help |
| 88 | Sets the address in DRAM where FSP-M should be loaded. cbfstool |
| 89 | performs relocation of FSP-M to this address. |
| 90 | |
| 91 | config FSP_M_SIZE |
| 92 | hex |
| 93 | default 0x80000 |
| 94 | help |
| 95 | Sets the size of DRAM allocation for FSP-M in linker script. |
| 96 | |
Felix Held | 8d0a609 | 2021-01-14 01:40:50 +0100 | [diff] [blame] | 97 | config FSP_TEMP_RAM_SIZE |
| 98 | hex |
| 99 | default 0x40000 |
| 100 | help |
| 101 | The amount of coreboot-allocated heap and stack usage by the FSP. |
| 102 | |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 103 | config RAMBASE |
| 104 | hex |
| 105 | default 0x10000000 |
| 106 | |
| 107 | config CPU_ADDR_BITS |
| 108 | int |
| 109 | default 48 |
| 110 | |
| 111 | config MMCONF_BASE_ADDRESS |
| 112 | hex |
| 113 | default 0xF8000000 |
| 114 | |
| 115 | config MMCONF_BUS_NUMBER |
| 116 | int |
| 117 | default 64 |
| 118 | |
Felix Held | 8861562 | 2021-01-19 23:51:45 +0100 | [diff] [blame] | 119 | config MAX_CPUS |
| 120 | int |
| 121 | default 16 |
| 122 | |
Felix Held | 8a3d4d5 | 2021-01-13 03:06:21 +0100 | [diff] [blame] | 123 | config CONSOLE_UART_BASE_ADDRESS |
| 124 | depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART |
| 125 | hex |
| 126 | default 0xfedc9000 if UART_FOR_CONSOLE = 0 |
| 127 | default 0xfedca000 if UART_FOR_CONSOLE = 1 |
| 128 | |
Zheng Bao | f51738d | 2021-01-20 16:43:52 +0800 | [diff] [blame] | 129 | menu "PSP Configuration Options" |
| 130 | |
| 131 | config AMD_FWM_POSITION_INDEX |
| 132 | int "Firmware Directory Table location (0 to 5)" |
| 133 | range 0 5 |
| 134 | default 0 if BOARD_ROMSIZE_KB_512 |
| 135 | default 1 if BOARD_ROMSIZE_KB_1024 |
| 136 | default 2 if BOARD_ROMSIZE_KB_2048 |
| 137 | default 3 if BOARD_ROMSIZE_KB_4096 |
| 138 | default 4 if BOARD_ROMSIZE_KB_8192 |
| 139 | default 5 if BOARD_ROMSIZE_KB_16384 |
| 140 | help |
| 141 | Typically this is calculated by the ROM size, but there may |
| 142 | be situations where you want to put the firmware directory |
| 143 | table in a different location. |
| 144 | 0: 512 KB - 0xFFFA0000 |
| 145 | 1: 1 MB - 0xFFF20000 |
| 146 | 2: 2 MB - 0xFFE20000 |
| 147 | 3: 4 MB - 0xFFC20000 |
| 148 | 4: 8 MB - 0xFF820000 |
| 149 | 5: 16 MB - 0xFF020000 |
| 150 | |
| 151 | comment "AMD Firmware Directory Table set to location for 512KB ROM" |
| 152 | depends on AMD_FWM_POSITION_INDEX = 0 |
| 153 | comment "AMD Firmware Directory Table set to location for 1MB ROM" |
| 154 | depends on AMD_FWM_POSITION_INDEX = 1 |
| 155 | comment "AMD Firmware Directory Table set to location for 2MB ROM" |
| 156 | depends on AMD_FWM_POSITION_INDEX = 2 |
| 157 | comment "AMD Firmware Directory Table set to location for 4MB ROM" |
| 158 | depends on AMD_FWM_POSITION_INDEX = 3 |
| 159 | comment "AMD Firmware Directory Table set to location for 8MB ROM" |
| 160 | depends on AMD_FWM_POSITION_INDEX = 4 |
| 161 | comment "AMD Firmware Directory Table set to location for 16MB ROM" |
| 162 | depends on AMD_FWM_POSITION_INDEX = 5 |
| 163 | |
| 164 | config AMDFW_CONFIG_FILE |
| 165 | string |
| 166 | default "src/soc/amd/cezanne/fw.cfg" |
| 167 | |
| 168 | config USE_PSPSECUREOS |
| 169 | bool |
| 170 | default y |
| 171 | help |
| 172 | Include the PspSecureOs and PspTrustlet binaries in the PSP build. |
| 173 | |
| 174 | If unsure, answer 'y' |
| 175 | |
| 176 | config PSP_LOAD_MP2_FW |
| 177 | bool |
| 178 | default n |
| 179 | help |
| 180 | Include the MP2 firmwares and configuration into the PSP build. |
| 181 | |
| 182 | If unsure, answer 'n' |
| 183 | |
| 184 | config PSP_LOAD_S0I3_FW |
| 185 | bool |
| 186 | default n |
| 187 | help |
| 188 | Select this item to include the S0i3 file into the PSP build. |
| 189 | |
| 190 | config PSP_UNLOCK_SECURE_DEBUG |
| 191 | bool "Unlock secure debug" |
| 192 | default y |
| 193 | help |
| 194 | Select this item to enable secure debug options in PSP. |
| 195 | |
| 196 | endmenu |
| 197 | |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 198 | endif # SOC_AMD_CEZANNE |