Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Chromium OS Authors |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <arch/io.h> |
| 21 | #include <console/console.h> |
| 22 | #include <delay.h> |
| 23 | #include <device/device.h> |
| 24 | #include <device/pci.h> |
| 25 | #include <device/pci_ids.h> |
| 26 | |
| 27 | #include "chip.h" |
| 28 | #include "haswell.h" |
| 29 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 30 | /* some vga option roms are used for several chipsets but they only have one |
| 31 | * PCI ID in their header. If we encounter such an option rom, we need to do |
| 32 | * the mapping ourselfes |
| 33 | */ |
| 34 | |
| 35 | u32 map_oprom_vendev(u32 vendev) |
| 36 | { |
| 37 | u32 new_vendev=vendev; |
| 38 | |
| 39 | switch (vendev) { |
| 40 | case 0x80860102: /* GT1 Desktop */ |
| 41 | case 0x8086010a: /* GT1 Server */ |
| 42 | case 0x80860112: /* GT2 Desktop */ |
| 43 | case 0x80860116: /* GT2 Mobile */ |
| 44 | case 0x80860122: /* GT2 Desktop >=1.3GHz */ |
| 45 | case 0x80860126: /* GT2 Mobile >=1.3GHz */ |
| 46 | case 0x80860166: /* IVB */ |
| 47 | new_vendev=0x80860106; /* GT1 Mobile */ |
| 48 | break; |
| 49 | } |
| 50 | |
| 51 | return new_vendev; |
| 52 | } |
| 53 | |
| 54 | static struct resource *gtt_res = NULL; |
| 55 | |
| 56 | static inline u32 gtt_read(u32 reg) |
| 57 | { |
| 58 | return read32(gtt_res->base + reg); |
| 59 | } |
| 60 | |
| 61 | static inline void gtt_write(u32 reg, u32 data) |
| 62 | { |
| 63 | write32(gtt_res->base + reg, data); |
| 64 | } |
| 65 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 66 | #define GTT_RETRY 1000 |
| 67 | static int gtt_poll(u32 reg, u32 mask, u32 value) |
| 68 | { |
| 69 | unsigned try = GTT_RETRY; |
| 70 | u32 data; |
| 71 | |
| 72 | while (try--) { |
| 73 | data = gtt_read(reg); |
| 74 | if ((data & mask) == value) |
| 75 | return 1; |
| 76 | udelay(10); |
| 77 | } |
| 78 | |
| 79 | printk(BIOS_ERR, "GT init timeout\n"); |
| 80 | return 0; |
| 81 | } |
| 82 | |
| 83 | static void gma_pm_init_pre_vbios(struct device *dev) |
| 84 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 85 | printk(BIOS_DEBUG, "GT Power Management Init\n"); |
| 86 | |
| 87 | gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 88 | if (!gtt_res || !gtt_res->base) |
| 89 | return; |
| 90 | |
Duncan Laurie | 67113e9 | 2013-01-10 13:23:04 -0800 | [diff] [blame] | 91 | /* |
| 92 | * Enable RC6 |
| 93 | */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 94 | |
Duncan Laurie | 67113e9 | 2013-01-10 13:23:04 -0800 | [diff] [blame] | 95 | /* Enable Force Wake */ |
| 96 | gtt_write(0x0a180, 1 << 5); |
| 97 | gtt_write(0x0a188, 0x00010001); |
| 98 | gtt_poll(0x130044, 1 << 0, 1 << 0); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 99 | |
Duncan Laurie | 67113e9 | 2013-01-10 13:23:04 -0800 | [diff] [blame] | 100 | /* Enable counters and lock */ |
| 101 | gtt_write(0x0a248, 0x80000016); |
| 102 | gtt_write(0x0a000, 0x00070020); |
| 103 | gtt_write(0x0a180, 0xc5000020); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 104 | |
Duncan Laurie | 67113e9 | 2013-01-10 13:23:04 -0800 | [diff] [blame] | 105 | /* Enable DOP clock gating */ |
| 106 | gtt_write(0x09424, 0x00000001); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 107 | |
Duncan Laurie | 67113e9 | 2013-01-10 13:23:04 -0800 | [diff] [blame] | 108 | /* Enable unit level clock gating */ |
| 109 | gtt_write(0x09400, 0x00000080); |
| 110 | gtt_write(0x09404, 0x40401000); |
| 111 | gtt_write(0x09408, 0x00000000); |
| 112 | gtt_write(0x0940c, 0x02000001); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 113 | |
Duncan Laurie | 67113e9 | 2013-01-10 13:23:04 -0800 | [diff] [blame] | 114 | /* Configure max ilde count */ |
| 115 | gtt_write(0x02054, 0x0000000a); |
| 116 | gtt_write(0x12054, 0x0000000a); |
| 117 | gtt_write(0x22054, 0x0000000a); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 118 | |
Duncan Laurie | 67113e9 | 2013-01-10 13:23:04 -0800 | [diff] [blame] | 119 | gtt_write(0x0a008, 0x10000000); |
| 120 | gtt_write(0x0a024, 0x00000b92); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 121 | |
Duncan Laurie | 67113e9 | 2013-01-10 13:23:04 -0800 | [diff] [blame] | 122 | /* Enable RC6 in idle */ |
| 123 | gtt_write(0x0a094, 0x00040000); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 124 | } |
| 125 | |
| 126 | static void gma_pm_init_post_vbios(struct device *dev) |
| 127 | { |
| 128 | struct northbridge_intel_haswell_config *conf = dev->chip_info; |
| 129 | u32 reg32; |
| 130 | |
| 131 | printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n"); |
| 132 | |
Duncan Laurie | 67113e9 | 2013-01-10 13:23:04 -0800 | [diff] [blame] | 133 | /* Disable Force Wake */ |
| 134 | gtt_write(0x0a188, 0x00010000); |
| 135 | gtt_poll(0x130044, 1 << 0, 0 << 0); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 136 | |
| 137 | /* Setup Digital Port Hotplug */ |
| 138 | reg32 = gtt_read(0xc4030); |
| 139 | if (!reg32) { |
| 140 | reg32 = (conf->gpu_dp_b_hotplug & 0x7) << 2; |
| 141 | reg32 |= (conf->gpu_dp_c_hotplug & 0x7) << 10; |
| 142 | reg32 |= (conf->gpu_dp_d_hotplug & 0x7) << 18; |
| 143 | gtt_write(0xc4030, reg32); |
| 144 | } |
| 145 | |
| 146 | /* Setup Panel Power On Delays */ |
| 147 | reg32 = gtt_read(0xc7208); |
| 148 | if (!reg32) { |
| 149 | reg32 = (conf->gpu_panel_port_select & 0x3) << 30; |
| 150 | reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16; |
| 151 | reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); |
| 152 | gtt_write(0xc7208, reg32); |
| 153 | } |
| 154 | |
| 155 | /* Setup Panel Power Off Delays */ |
| 156 | reg32 = gtt_read(0xc720c); |
| 157 | if (!reg32) { |
| 158 | reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16; |
| 159 | reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff); |
| 160 | gtt_write(0xc720c, reg32); |
| 161 | } |
| 162 | |
| 163 | /* Setup Panel Power Cycle Delay */ |
| 164 | if (conf->gpu_panel_power_cycle_delay) { |
| 165 | reg32 = gtt_read(0xc7210); |
| 166 | reg32 &= ~0xff; |
| 167 | reg32 |= conf->gpu_panel_power_cycle_delay & 0xff; |
| 168 | gtt_write(0xc7210, reg32); |
| 169 | } |
| 170 | |
| 171 | /* Enable Backlight if needed */ |
| 172 | if (conf->gpu_cpu_backlight) { |
| 173 | gtt_write(0x48250, (1 << 31)); |
| 174 | gtt_write(0x48254, conf->gpu_cpu_backlight); |
| 175 | } |
| 176 | if (conf->gpu_pch_backlight) { |
| 177 | gtt_write(0xc8250, (1 << 31)); |
| 178 | gtt_write(0xc8254, conf->gpu_pch_backlight); |
| 179 | } |
| 180 | } |
| 181 | |
| 182 | static void gma_func0_init(struct device *dev) |
| 183 | { |
| 184 | u32 reg32; |
| 185 | |
| 186 | /* IGD needs to be Bus Master */ |
| 187 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 188 | reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; |
| 189 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 190 | |
| 191 | /* Init graphics power management */ |
| 192 | gma_pm_init_pre_vbios(dev); |
| 193 | |
| 194 | /* PCI Init, will run VBIOS */ |
| 195 | pci_dev_init(dev); |
| 196 | |
| 197 | /* Post VBIOS init */ |
| 198 | gma_pm_init_post_vbios(dev); |
| 199 | } |
| 200 | |
| 201 | static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) |
| 202 | { |
| 203 | if (!vendor || !device) { |
| 204 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 205 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 206 | } else { |
| 207 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 208 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 209 | } |
| 210 | } |
| 211 | |
| 212 | static struct pci_operations gma_pci_ops = { |
| 213 | .set_subsystem = gma_set_subsystem, |
| 214 | }; |
| 215 | |
| 216 | static struct device_operations gma_func0_ops = { |
| 217 | .read_resources = pci_dev_read_resources, |
| 218 | .set_resources = pci_dev_set_resources, |
| 219 | .enable_resources = pci_dev_enable_resources, |
| 220 | .init = gma_func0_init, |
| 221 | .scan_bus = 0, |
| 222 | .enable = 0, |
| 223 | .ops_pci = &gma_pci_ops, |
| 224 | }; |
| 225 | |
Duncan Laurie | df7be71 | 2012-12-17 11:22:57 -0800 | [diff] [blame] | 226 | static const unsigned short pci_device_ids[] = { |
| 227 | 0x0402, /* Desktop GT1 */ |
| 228 | 0x0412, /* Desktop GT2 */ |
| 229 | 0x0422, /* Desktop GT3 */ |
| 230 | 0x0406, /* Mobile GT1 */ |
| 231 | 0x0416, /* Mobile GT2 */ |
| 232 | 0x0426, /* Mobile GT3 */ |
| 233 | 0x0d16, /* Mobile 4+3 GT1 */ |
| 234 | 0x0d26, /* Mobile 4+3 GT2 */ |
| 235 | 0x0d36, /* Mobile 4+3 GT3 */ |
| 236 | 0x0a06, /* ULT GT1 */ |
| 237 | 0x0a16, /* ULT GT2 */ |
| 238 | 0x0a26, /* ULT GT3 */ |
| 239 | 0, |
| 240 | }; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 241 | |
| 242 | static const struct pci_driver pch_lpc __pci_driver = { |
| 243 | .ops = &gma_func0_ops, |
| 244 | .vendor = PCI_VENDOR_ID_INTEL, |
| 245 | .devices = pci_device_ids, |
| 246 | }; |