| Angel Pons | dbdd528 | 2021-06-14 12:14:48 +0200 | [diff] [blame] | 1 | config INTEL_LYNXPOINT_LP |
| 2 | bool |
| 3 | default y if SOC_INTEL_BROADWELL |
| 4 | |
| 5 | config PCH_SPECIFIC_OPTIONS |
| 6 | def_bool y |
| 7 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
| 8 | select ACPI_SOC_NVS |
| 9 | select AZALIA_PLUGIN_SUPPORT |
| 10 | select BOOT_DEVICE_SUPPORTS_WRITES |
| 11 | select HAVE_EM100PRO_SPI_CONSOLE_SUPPORT |
| 12 | select HAVE_POWER_STATE_AFTER_FAILURE |
| 13 | select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE |
| 14 | select HAVE_SMI_HANDLER |
| 15 | select HAVE_USBDEBUG |
| 16 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
| 17 | select INTEL_LYNXPOINT_LP |
| Angel Pons | dbdd528 | 2021-06-14 12:14:48 +0200 | [diff] [blame] | 18 | select RTC |
| 19 | select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT |
| 20 | select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS |
| 21 | select SOUTHBRIDGE_INTEL_COMMON_RESET |
| 22 | select SOUTHBRIDGE_INTEL_COMMON_RTC |
| 23 | select SOUTHBRIDGE_INTEL_COMMON_SMBUS |
| 24 | select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 |
| 25 | select SPI_FLASH |
| Kyösti Mälkki | e8a3af1 | 2022-11-19 18:39:22 +0200 | [diff] [blame] | 26 | select TCO_SPACE_NOT_YET_SPLIT |
| Angel Pons | dbdd528 | 2021-06-14 12:14:48 +0200 | [diff] [blame] | 27 | |
| Angel Pons | dbdd528 | 2021-06-14 12:14:48 +0200 | [diff] [blame] | 28 | config EHCI_BAR |
| 29 | hex |
| 30 | default 0xd8000000 |
| 31 | |
| 32 | config SERIRQ_CONTINUOUS_MODE |
| 33 | bool |
| 34 | default y |
| 35 | help |
| 36 | If you set this option to y, the serial IRQ machine will be |
| 37 | operated in continuous mode. |
| 38 | |
| 39 | config PCIEXP_ASPM |
| 40 | bool |
| 41 | default y |
| 42 | |
| 43 | config PCIEXP_AER |
| 44 | bool |
| 45 | default y |
| 46 | |
| 47 | config PCIEXP_COMMON_CLOCK |
| 48 | bool |
| 49 | default y |
| 50 | |
| 51 | config PCIEXP_CLK_PM |
| 52 | bool |
| 53 | default y |
| 54 | |
| 55 | config PCIEXP_L1_SUB_STATE |
| 56 | bool |
| 57 | default y |
| 58 | |
| 59 | config SERIALIO_UART_CONSOLE |
| 60 | bool |
| 61 | default n |
| 62 | select DRIVERS_UART_8250MEM_32 |
| 63 | help |
| 64 | Selected by mainboards where SerialIO UARTs can be used to retrieve |
| 65 | coreboot logs. Boards also need to set UART_FOR_CONSOLE accordingly. |
| 66 | |
| 67 | config CONSOLE_UART_BASE_ADDRESS |
| 68 | default 0xd6000000 if SERIALIO_UART_CONSOLE |
| Matt DeVillier | ef72def | 2022-12-21 14:55:33 -0600 | [diff] [blame^] | 69 | |
| 70 | config DISABLE_ME_PCI |
| 71 | bool "Disable Intel ME PCI interface (MEI1)" |
| 72 | default y |
| 73 | help |
| 74 | Disable and hide the ME PCI interface during finalize stage of boot. |
| 75 | This will prevent the OS (and userspace apps) from interacting with |
| 76 | the ME via the PCI interface after boot. |