Tim Crawford | 8e3787e | 2022-09-29 12:11:34 -0600 | [diff] [blame] | 1 | chip soc/intel/tigerlake |
| 2 | # Power limits |
| 3 | register "power_limits_config[POWER_LIMITS_H_8_CORE]" = "{ |
| 4 | .tdp_pl1_override = 45, |
| 5 | .tdp_pl2_override = 90, |
| 6 | }" |
| 7 | register "power_limits_config[POWER_LIMITS_H_6_CORE]" = "{ |
| 8 | .tdp_pl1_override = 45, |
| 9 | .tdp_pl2_override = 90, |
| 10 | }" |
| 11 | |
| 12 | # Thermal |
| 13 | register "tcc_offset" = "10" |
| 14 | |
| 15 | device domain 0 on |
| 16 | subsystemid 0x1558 0x65f1 inherit |
| 17 | |
| 18 | device ref peg1 on |
| 19 | # PCIe PEG1 x16, Clock 9 (DGPU) |
| 20 | register "PcieClkSrcUsage[9]" = "0x41" |
| 21 | register "PcieClkSrcClkReq[9]" = "9" |
| 22 | chip soc/intel/common/block/pcie/rtd3 |
| 23 | register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # DGPU_PWR_EN |
| 24 | register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F8)" # DGPU_RST#_PCH |
| 25 | register "enable_delay_ms" = "16" |
| 26 | register "enable_off_delay_ms" = "4" |
| 27 | register "reset_delay_ms" = "10" |
| 28 | register "reset_off_delay_ms" = "4" |
| 29 | register "srcclk_pin" = "9" # PEG_CLKREQ# |
| 30 | device generic 0 on end |
| 31 | end |
| 32 | end |
| 33 | device ref peg0 on |
| 34 | # PCIe PEG0 x4, Clock 7 (SSD1) |
| 35 | register "PcieClkSrcUsage[7]" = "0x40" |
| 36 | register "PcieClkSrcClkReq[7]" = "7" |
| 37 | end |
| 38 | device ref tbt_pcie_rp0 on end # TYPEC1 |
| 39 | device ref north_xhci on # TYPEC1 |
| 40 | register "TcssXhciEn" = "1" |
| 41 | end |
| 42 | device ref tbt_dma0 on end # TYPEC1 |
| 43 | device ref south_xhci on |
Felix Singer | ee1fd54 | 2023-10-26 15:42:16 +0200 | [diff] [blame^] | 44 | register "usb2_ports" = "{ |
| 45 | [0] = USB2_PORT_MID(OC_SKIP), /* USB 3.2 Gen 1 (Left) */ |
| 46 | [2] = USB2_PORT_MID(OC_SKIP), /* USB 3.2 Gen 1 (Right 1) */ |
| 47 | [3] = USB2_PORT_MID(OC_SKIP), /* USB 3.2 Gen 1 (Right 2) */ |
| 48 | [4] = USB2_PORT_MID(OC_SKIP), /* Per-Key */ |
| 49 | [7] = USB2_PORT_MID(OC_SKIP), /* Camera */ |
| 50 | [8] = USB2_PORT_TYPE_C(OC_SKIP), /* TYPEC1 */ |
| 51 | [9] = USB2_PORT_MID(OC_SKIP), /* Fingerprint */ |
| 52 | [13] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */ |
| 53 | }" |
| 54 | register "usb3_ports" = "{ |
| 55 | [0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.2 Gen 1 (Left) */ |
| 56 | [2] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.2 Gen 1 (Right 1) */ |
| 57 | [3] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.2 Gen 1 (Right 2) */ |
| 58 | }" |
Tim Crawford | 8e3787e | 2022-09-29 12:11:34 -0600 | [diff] [blame] | 59 | end |
| 60 | device ref sata on |
| 61 | register "SataPortsEnable[1]" = "1" # SSD2 (SATA1A) |
| 62 | end |
| 63 | device ref pcie_rp5 on |
| 64 | # PCIe root port #5 x1, Clock 8 (GLAN) |
| 65 | register "PcieRpEnable[4]" = "1" |
| 66 | register "PcieRpLtrEnable[4]" = "1" |
| 67 | register "PcieClkSrcUsage[8]" = "4" |
| 68 | register "PcieClkSrcClkReq[8]" = "8" |
| 69 | end |
| 70 | device ref pcie_rp6 on |
| 71 | # PCIe root port #6 x1, Clock 10 (CARD) |
| 72 | register "PcieRpEnable[5]" = "1" |
| 73 | register "PcieRpLtrEnable[5]" = "1" |
| 74 | register "PcieClkSrcUsage[10]" = "5" |
| 75 | register "PcieClkSrcClkReq[10]" = "10" |
| 76 | end |
| 77 | device ref pcie_rp8 on |
| 78 | # PCIe root port #8 x1, Clock 2 (WLAN) |
| 79 | register "PcieRpEnable[7]" = "1" |
| 80 | register "PcieRpLtrEnable[7]" = "1" |
| 81 | register "PcieClkSrcUsage[2]" = "7" |
| 82 | register "PcieClkSrcClkReq[2]" = "2" |
| 83 | register "PcieRpSlotImplemented[7]" = "1" |
| 84 | end |
| 85 | device ref pcie_rp9 on |
| 86 | # PCIe root port #9 x4, Clock 6 (SSD2) |
| 87 | register "PcieRpEnable[8]" = "1" |
| 88 | register "PcieRpLtrEnable[8]" = "1" |
| 89 | register "PcieClkSrcUsage[6]" = "8" |
| 90 | register "PcieClkSrcClkReq[6]" = "6" |
| 91 | register "PcieRpSlotImplemented[8]" = "1" |
| 92 | end |
| 93 | device ref smbus on |
| 94 | chip drivers/i2c/tas5825m |
| 95 | register "id" = "0" |
| 96 | device i2c 4e on end # (8bit address: 0x9c) |
| 97 | end |
| 98 | end |
| 99 | end |
| 100 | end |