Jeremy Soller | 8065c6d | 2021-11-01 14:07:07 -0600 | [diff] [blame] | 1 | chip soc/intel/tigerlake |
| 2 | device domain 0 on |
| 3 | subsystemid 0x1558 0x5015 inherit |
| 4 | |
| 5 | device ref peg1 on |
| 6 | # PCIe PEG2 (remapped to PEG1 by FSP) x8, Clock 0 (DGPU) |
| 7 | register "PcieClkSrcUsage[0]" = "0x42" |
| 8 | register "PcieClkSrcClkReq[0]" = "0" |
| 9 | chip soc/intel/common/block/pcie/rtd3 |
| 10 | register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # DGPU_PWR_EN |
| 11 | register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F8)" # DGPU_RST#_PCH |
| 12 | register "enable_delay_ms" = "16" |
| 13 | register "enable_off_delay_ms" = "4" |
| 14 | register "reset_delay_ms" = "10" |
| 15 | register "reset_off_delay_ms" = "4" |
Tim Crawford | 2a404b5 | 2022-01-07 14:12:34 -0700 | [diff] [blame] | 16 | register "srcclk_pin" = "0" # GFX_CLKREQ0# |
Jeremy Soller | 8065c6d | 2021-11-01 14:07:07 -0600 | [diff] [blame] | 17 | device generic 0 on end |
| 18 | end |
| 19 | end |
Tim Crawford | 8e3787e | 2022-09-29 12:11:34 -0600 | [diff] [blame] | 20 | device ref igpu on |
| 21 | # DDIB is HDMI |
| 22 | register "DdiPortBConfig" = "DDI_PORT_CFG_NO_LFP" |
| 23 | register "DdiPortBHpd" = "1" |
| 24 | register "DdiPortBDdc" = "1" |
| 25 | end |
Jeremy Soller | 8065c6d | 2021-11-01 14:07:07 -0600 | [diff] [blame] | 26 | device ref peg0 on |
| 27 | # PCIe PEG0 x4, Clock 4 (SSD2) |
| 28 | register "PcieClkSrcUsage[4]" = "0x40" |
| 29 | register "PcieClkSrcClkReq[4]" = "4" |
| 30 | end |
| 31 | device ref south_xhci on |
Felix Singer | ee1fd54 | 2023-10-26 15:42:16 +0200 | [diff] [blame^] | 32 | register "usb2_ports" = "{ |
| 33 | [0] = USB2_PORT_MID(OC_SKIP), /* USB 3.2 Gen 1 (Right) */ |
| 34 | [1] = USB2_PORT_TYPE_C(OC_SKIP), /* USB 3.2 Gen 2 Type C (Right) */ |
| 35 | [3] = USB2_PORT_MID(OC_SKIP), /* USB 3.2 Gen 1 (Left) */ |
| 36 | [4] = USB2_PORT_MID(OC_SKIP), /* USB 2.0 (Left) */ |
| 37 | [5] = USB2_PORT_MID(OC_SKIP), /* Fingerprint */ |
| 38 | [7] = USB2_PORT_MID(OC_SKIP), /* Camera */ |
| 39 | [13] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */ |
| 40 | }" |
| 41 | register "usb3_ports" = "{ |
| 42 | [0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.2 Gen 2 (Right) */ |
| 43 | [1] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.2 Gen 2 Type C (Right) */ |
| 44 | [2] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.2 Gen 2 Type C (Right) */ |
| 45 | [3] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.2 Gen 1 (Left) */ |
| 46 | }" |
Jeremy Soller | 8065c6d | 2021-11-01 14:07:07 -0600 | [diff] [blame] | 47 | end |
| 48 | device ref sata on |
Felix Singer | ee1fd54 | 2023-10-26 15:42:16 +0200 | [diff] [blame^] | 49 | register "SataPortsEnable" = "{ |
| 50 | [0] = 1, /* HDD (SATA0B) */ |
| 51 | [1] = 1, /* SSD1 (SATA1A) */ |
| 52 | }" |
Jeremy Soller | 8065c6d | 2021-11-01 14:07:07 -0600 | [diff] [blame] | 53 | end |
| 54 | device ref pcie_rp5 on |
| 55 | # PCIe root port #5 x1, Clock 5 (GLAN) |
| 56 | register "PcieRpEnable[4]" = "1" |
| 57 | register "PcieRpLtrEnable[4]" = "1" |
| 58 | register "PcieClkSrcUsage[5]" = "4" |
| 59 | register "PcieClkSrcClkReq[5]" = "5" |
| 60 | end |
| 61 | device ref pcie_rp7 on |
| 62 | # PCIe root port #7 x1, Clock 7 (CARD) |
| 63 | register "PcieRpEnable[6]" = "1" |
| 64 | register "PcieRpLtrEnable[6]" = "1" |
| 65 | register "PcieClkSrcUsage[7]" = "6" |
| 66 | register "PcieClkSrcClkReq[7]" = "7" |
| 67 | end |
| 68 | device ref pcie_rp8 on |
| 69 | # PCIe root port #8 x1, Clock 8 (WLAN) |
| 70 | register "PcieRpEnable[7]" = "1" |
| 71 | register "PcieRpLtrEnable[7]" = "1" |
| 72 | register "PcieClkSrcUsage[8]" = "7" |
| 73 | register "PcieClkSrcClkReq[8]" = "8" |
Michael Niewöhner | 45b6080 | 2022-01-08 20:47:11 +0100 | [diff] [blame] | 74 | register "PcieRpSlotImplemented[7]" = "1" |
Jeremy Soller | 8065c6d | 2021-11-01 14:07:07 -0600 | [diff] [blame] | 75 | end |
| 76 | device ref pcie_rp9 on |
| 77 | # PCIe root port #9 x4, Clock 9 (SSD1) |
| 78 | register "PcieRpEnable[8]" = "1" |
| 79 | register "PcieRpLtrEnable[8]" = "1" |
| 80 | register "PcieClkSrcUsage[9]" = "8" |
| 81 | register "PcieClkSrcClkReq[9]" = "9" |
Michael Niewöhner | 45b6080 | 2022-01-08 20:47:11 +0100 | [diff] [blame] | 82 | register "PcieRpSlotImplemented[8]" = "1" |
Jeremy Soller | 8065c6d | 2021-11-01 14:07:07 -0600 | [diff] [blame] | 83 | end |
| 84 | end |
| 85 | end |