Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 2 | |
| 3 | #include "msrtool.h" |
| 4 | |
| 5 | int via_c7_probe(const struct targetdef *target, const struct cpuid_t *id) { |
| 6 | return ((VENDOR_CENTAUR == id->vendor) && |
| 7 | (0x6 == id->family) && ( |
| 8 | (0xa == id->model) || /* C7 A */ |
| 9 | (0xd == id->model) || /* C7 D */ |
| 10 | (0xf == id->model) /* Nano */ |
| 11 | )); |
| 12 | } |
| 13 | |
| 14 | const struct msrdef via_c7_msrs[] = { |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 15 | {0x10, MSRTYPE_RDWR, MSR2(0, 0), "IA32_TIME_STAMP_COUNTER", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 16 | { BITS_EOT } |
| 17 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 18 | {0x2a, MSRTYPE_RDWR, MSR2(0, 0), "EBL_CR_POWERON", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 19 | { BITS_EOT } |
| 20 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 21 | {0xc1, MSRTYPE_RDWR, MSR2(0, 0), "PERFCTR0", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 22 | { BITS_EOT } |
| 23 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 24 | {0xc2, MSRTYPE_RDWR, MSR2(0, 0), "PERFCTR1", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 25 | { BITS_EOT } |
| 26 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 27 | {0x11e, MSRTYPE_RDWR, MSR2(0, 0), "BBL_CR_CTL3", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 28 | { BITS_EOT } |
| 29 | }}, |
| 30 | /* if CPUID.0AH: EAX[15:8] > 0 */ |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 31 | {0x186, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERFEVTSEL0", |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 32 | "Performance Event Select Register 0", { |
| 33 | { 63, 32, RESERVED }, |
| 34 | { 31, 8, "CMASK", "R/W", PRESENT_HEX, { |
| 35 | /* When CMASK is not zero, the corresponding performance |
| 36 | * counter 0 increments each cycle if the event count |
| 37 | * is greater than or equal to the CMASK. |
| 38 | */ |
| 39 | { BITVAL_EOT } |
| 40 | }}, |
| 41 | { 23, 1, "INV", "R/W", PRESENT_BIN, { |
| 42 | { MSR1(0), "CMASK using as is" }, |
| 43 | { MSR1(1), "CMASK inerting" }, |
| 44 | { BITVAL_EOT } |
| 45 | }}, |
| 46 | { 22, 1, "EN", "R/W", PRESENT_BIN, { |
| 47 | { MSR1(0), "No commence counting" }, |
| 48 | { MSR1(1), "Commence counting" }, |
| 49 | { BITVAL_EOT } |
| 50 | }}, |
| 51 | { 21, 1, "AnyThread", "R/W", PRESENT_BIN, { |
| 52 | { BITVAL_EOT } |
| 53 | }}, |
| 54 | { 20, 1, "INT", "R/W", PRESENT_BIN, { |
| 55 | { MSR1(0), "Interrupt on counter overflow is disabled" }, |
| 56 | { MSR1(1), "Interrupt on counter overflow is enabled" }, |
| 57 | { BITVAL_EOT } |
| 58 | }}, |
| 59 | { 19, 1, "PC", "R/W", PRESENT_BIN, { |
| 60 | { MSR1(0), "Disabled pin control" }, |
| 61 | { MSR1(1), "Enabled pin control" }, |
| 62 | { BITVAL_EOT } |
| 63 | }}, |
| 64 | { 18, 1, "Edge", "R/W", PRESENT_BIN, { |
| 65 | { MSR1(0), "Disabled edge detection" }, |
| 66 | { MSR1(1), "Enabled edge detection" }, |
| 67 | { BITVAL_EOT } |
| 68 | }}, |
| 69 | { 17, 1, "OS", "R/W", PRESENT_BIN, { |
| 70 | { MSR1(0), "Nothing" }, |
| 71 | { MSR1(1), "Counts while in privilege level is ring 0" }, |
| 72 | { BITVAL_EOT } |
| 73 | }}, |
| 74 | { 16, 1, "USR", "R/W", PRESENT_BIN, { |
| 75 | { MSR1(0), "Nothing" }, |
| 76 | { MSR1(1), "Counts while in privilege level is not ring 0" }, |
| 77 | { BITVAL_EOT } |
| 78 | }}, |
| 79 | { 15, 8, "UMask", "R/W", PRESENT_HEX, { |
| 80 | /* Qualifies the microarchitectural condition |
| 81 | * to detect on the selected event logic. */ |
| 82 | { BITVAL_EOT } |
| 83 | }}, |
| 84 | { 7, 8, "Event Select", "R/W", PRESENT_HEX, { |
| 85 | /* Selects a performance event logic unit. */ |
| 86 | { BITVAL_EOT } |
| 87 | }}, |
| 88 | { BITS_EOT } |
| 89 | }}, |
| 90 | /* if CPUID.0AH: EAX[15:8] > 0 */ |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 91 | {0x187, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERFEVTSEL1", |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 92 | "Performance Event Select Register 1", { |
| 93 | { 63, 32, RESERVED }, |
| 94 | { 31, 8, "CMASK", "R/W", PRESENT_HEX, { |
| 95 | /* When CMASK is not zero, the corresponding performance |
| 96 | * counter 1 increments each cycle if the event count |
| 97 | * is greater than or equal to the CMASK. |
| 98 | */ |
| 99 | { BITVAL_EOT } |
| 100 | }}, |
| 101 | { 23, 1, "INV", "R/W", PRESENT_BIN, { |
| 102 | { MSR1(0), "CMASK using as is" }, |
| 103 | { MSR1(1), "CMASK inerting" }, |
| 104 | { BITVAL_EOT } |
| 105 | }}, |
| 106 | { 22, 1, "EN", "R/W", PRESENT_BIN, { |
| 107 | { MSR1(0), "No commence counting" }, |
| 108 | { MSR1(1), "Commence counting" }, |
| 109 | { BITVAL_EOT } |
| 110 | }}, |
| 111 | { 21, 1, "AnyThread", "R/W", PRESENT_BIN, { |
| 112 | { BITVAL_EOT } |
| 113 | }}, |
| 114 | { 20, 1, "INT", "R/W", PRESENT_BIN, { |
| 115 | { MSR1(0), "Interrupt on counter overflow is disabled" }, |
| 116 | { MSR1(1), "Interrupt on counter overflow is enabled" }, |
| 117 | { BITVAL_EOT } |
| 118 | }}, |
| 119 | { 19, 1, "PC", "R/W", PRESENT_BIN, { |
| 120 | { MSR1(0), "Disabled pin control" }, |
| 121 | { MSR1(1), "Enabled pin control" }, |
| 122 | { BITVAL_EOT } |
| 123 | }}, |
| 124 | { 18, 1, "Edge", "R/W", PRESENT_BIN, { |
| 125 | { MSR1(0), "Disabled edge detection" }, |
| 126 | { MSR1(1), "Enabled edge detection" }, |
| 127 | { BITVAL_EOT } |
| 128 | }}, |
| 129 | { 17, 1, "OS", "R/W", PRESENT_BIN, { |
| 130 | { MSR1(0), "Nothing" }, |
| 131 | { MSR1(1), "Counts while in privilege level is ring 0" }, |
| 132 | { BITVAL_EOT } |
| 133 | }}, |
| 134 | { 16, 1, "USR", "R/W", PRESENT_BIN, { |
| 135 | { MSR1(0), "Nothing" }, |
| 136 | { MSR1(1), "Counts while in privilege level is not ring 0" }, |
| 137 | { BITVAL_EOT } |
| 138 | }}, |
| 139 | { 15, 8, "UMask", "R/W", PRESENT_HEX, { |
| 140 | /* Qualifies the microarchitectural condition |
| 141 | * to detect on the selected event logic. */ |
| 142 | { BITVAL_EOT } |
| 143 | }}, |
| 144 | { 7, 8, "Event Select", "R/W", PRESENT_HEX, { |
| 145 | /* Selects a performance event logic unit. */ |
| 146 | { BITVAL_EOT } |
| 147 | }}, |
| 148 | { BITS_EOT } |
| 149 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 150 | {0x198, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_STATUS", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 151 | { 63, 8, "Lowest Supported Clock Ratio", "R/O", PRESENT_HEX, { |
| 152 | { BITVAL_EOT } |
| 153 | }}, |
| 154 | { 55, 8, "Lowest Supported Voltage", "R/O", PRESENT_HEX, { |
| 155 | { BITVAL_EOT } |
| 156 | }}, |
| 157 | { 47, 8, "Highest Supported Clock Ratio", "R/O", PRESENT_HEX, { |
| 158 | { BITVAL_EOT } |
| 159 | }}, |
| 160 | { 39, 8, "Highest Supported Voltage", "R/O", PRESENT_HEX, { |
| 161 | { BITVAL_EOT } |
| 162 | }}, |
| 163 | { 31, 8, "Lowest Clock Ratio", "R/O", PRESENT_HEX, { |
| 164 | { BITVAL_EOT } |
| 165 | }}, |
| 166 | { 23, 2, RESERVED }, |
| 167 | { 21, 2, "Performance Control MSR Transition", "R/O", PRESENT_HEX, { |
| 168 | { BITVAL_EOT } |
| 169 | }}, |
| 170 | { 19, 1, "Thermal Monitor 2 transition", "R/O", PRESENT_BIN, { |
| 171 | { BITVAL_EOT } |
| 172 | }}, |
| 173 | { 18, 1, "Thermal Monitor 2 transition", "R/O", PRESENT_BIN, { |
| 174 | { BITVAL_EOT } |
| 175 | }}, |
| 176 | { 17, 1, "Voltage Transition in progress", "R/O", PRESENT_BIN, { |
| 177 | { BITVAL_EOT } |
| 178 | }}, |
| 179 | { 16, 1, "Clock Ratio Transition in progress", "R/O", PRESENT_BIN, { |
| 180 | { BITVAL_EOT } |
| 181 | }}, |
| 182 | { 15, 8, "Current Clock Ratio", "R/W", PRESENT_HEX, { |
| 183 | { BITVAL_EOT } |
| 184 | }}, |
| 185 | { 7, 8, "16*x + 700 = Current voltage in mV", "R/W", PRESENT_HEX, { |
| 186 | { BITVAL_EOT } |
| 187 | }}, |
| 188 | { BITS_EOT } |
| 189 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 190 | {0x199, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_CTL", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 191 | { 63, 48, RESERVED }, |
| 192 | { 15, 8, "Desired Clock Ratio", "R/W", PRESENT_HEX, { |
| 193 | { BITVAL_EOT } |
| 194 | }}, |
| 195 | { 7, 8, "16*x + 700 = Desired voltage in mV", "R/W", PRESENT_HEX, { |
| 196 | { BITVAL_EOT } |
| 197 | }}, |
| 198 | { BITS_EOT } |
| 199 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 200 | {0x19a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_CLOCK_MODULATION", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 201 | { 63, 59, RESERVED }, |
| 202 | { 15, 8, "allows selection of the on-demand clock modulation duty cycle", "R/W", PRESENT_BIN, { |
| 203 | { MSR1(0), "Reserved" }, |
| 204 | { MSR1(1), "12.5%" }, |
| 205 | { MSR1(2), "25.0%" }, |
| 206 | { MSR1(3), "37.5%" }, |
| 207 | { MSR1(4), "50.0%" }, |
| 208 | { MSR1(5), "62.5%" }, |
| 209 | { MSR1(6), "75.0%" }, |
| 210 | { MSR1(7), "87.5%" }, |
| 211 | { BITVAL_EOT } |
| 212 | }}, |
| 213 | { 0, 1, RESERVED }, |
| 214 | { BITS_EOT } |
| 215 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 216 | {0x19b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_INTERRUPT", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 217 | { 63, 62, RESERVED }, |
| 218 | { 1, 1, "Enables APIC LVT interrupt on a low-to-high temp transition", "R/W", PRESENT_BIN, { |
| 219 | { BITVAL_EOT } |
| 220 | }}, |
| 221 | { 0, 1, "Enables APIC LVT interrupt on a high-to-low temp transition", "R/W", PRESENT_BIN, { |
| 222 | { BITVAL_EOT } |
| 223 | }}, |
| 224 | { BITS_EOT } |
| 225 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 226 | {0x19c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_STATUS", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 227 | { 63, 62, RESERVED }, |
| 228 | { 1, 1, "TCC assert detect", "R/O", PRESENT_BIN, { |
| 229 | { MSR1(0), "TCC not asserted" }, |
| 230 | { MSR1(1), "TCC asserted" }, |
| 231 | { BITVAL_EOT } |
| 232 | }}, |
| 233 | { 0, 1, "TCC trigger detect (Sticky bit, only cleared upon reset)", "R/O", PRESENT_BIN, { |
| 234 | { MSR1(0), "TCC not triggered" }, |
| 235 | { MSR1(1), "TCC triggered" }, |
| 236 | { BITVAL_EOT } |
| 237 | }}, |
| 238 | { BITS_EOT } |
| 239 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 240 | {0x19d, MSRTYPE_RDWR, MSR2(0, 0), "MSR_THERM2_CTL", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 241 | { 63, 47, RESERVED }, |
| 242 | { 16, 1, "Thermal Monitor enable", "R/W", PRESENT_HEX, { |
| 243 | { MSR1(0), "Thermal Monitor 1 enabled" }, |
| 244 | { MSR1(1), "Thermal Monitor 2 enabled" }, |
| 245 | { BITVAL_EOT } |
| 246 | }}, |
| 247 | { 15, 8, "Thermal Monitor 2 performance state clock ratio", "R/W", PRESENT_HEX, { |
| 248 | { BITVAL_EOT } |
| 249 | }}, |
| 250 | { 7, 8, "Thermal Monitor 2 performance state volatege", "R/W", PRESENT_HEX, { |
| 251 | { BITVAL_EOT } |
| 252 | }}, |
| 253 | { BITS_EOT } |
| 254 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 255 | {0x1a0, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MISC_ENABLES", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 256 | { 63, 43, RESERVED }, |
| 257 | { 20, 1, "PowerSaver lock", "R/W", PRESENT_BIN, { |
| 258 | { MSR1(0), "Bit 16 can be set and cleared." }, |
| 259 | { MSR1(1), "Bit 16 can only be cleared upon reset." }, |
| 260 | { BITVAL_EOT } |
| 261 | }}, |
| 262 | { 19, 3, RESERVED }, |
| 263 | { 16, 1, "Enhanced PowerSaver enable", "R/W", PRESENT_BIN, { |
| 264 | { MSR1(0), "Performance state changes disabled" }, |
| 265 | { MSR1(1), "Performance state changes enabled" }, |
| 266 | { BITVAL_EOT } |
| 267 | }}, |
| 268 | { 15, 5, RESERVED }, |
| 269 | { 10, 1, "PBE enable", "R/W", PRESENT_BIN, { |
| 270 | { MSR1(0), "FERR# legacy mode" }, |
| 271 | { MSR1(1), "Enables break events for APIC via FERR#" }, |
| 272 | { BITVAL_EOT } |
| 273 | }}, |
| 274 | { 9, 6, RESERVED }, |
| 275 | { 3, 1, "Thermal Monitor 2 enable", "R/W", PRESENT_BIN, { |
| 276 | { MSR1(0), "On-die clock throttling enabled" }, |
| 277 | { MSR1(1), "Thermal Monitor 1 or 2 enabled" }, |
| 278 | { BITVAL_EOT } |
| 279 | }}, |
| 280 | { 2, 3, RESERVED }, |
| 281 | { BITS_EOT } |
| 282 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 283 | {0x200, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE0", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 284 | { BITS_EOT } |
| 285 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 286 | {0x201, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK0", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 287 | { BITS_EOT } |
| 288 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 289 | {0x202, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE1", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 290 | { BITS_EOT } |
| 291 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 292 | {0x203, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK1", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 293 | { BITS_EOT } |
| 294 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 295 | {0x204, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE2", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 296 | { BITS_EOT } |
| 297 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 298 | {0x205, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK2", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 299 | { BITS_EOT } |
| 300 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 301 | {0x206, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE3", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 302 | { BITS_EOT } |
| 303 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 304 | {0x207, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK3", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 305 | { BITS_EOT } |
| 306 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 307 | {0x208, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE4", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 308 | { BITS_EOT } |
| 309 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 310 | {0x209, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK4", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 311 | { BITS_EOT } |
| 312 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 313 | {0x20a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE5", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 314 | { BITS_EOT } |
| 315 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 316 | {0x20b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK5", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 317 | { BITS_EOT } |
| 318 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 319 | {0x20c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE6", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 320 | { BITS_EOT } |
| 321 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 322 | {0x20d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK6", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 323 | { BITS_EOT } |
| 324 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 325 | {0x20e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE7", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 326 | { BITS_EOT } |
| 327 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 328 | {0x20f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK7", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 329 | { BITS_EOT } |
| 330 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 331 | {0x250, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX64K_00000", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 332 | { BITS_EOT } |
| 333 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 334 | {0x258, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_80000", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 335 | { BITS_EOT } |
| 336 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 337 | {0x259, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_A0000", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 338 | { BITS_EOT } |
| 339 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 340 | {0x268, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C0000", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 341 | { BITS_EOT } |
| 342 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 343 | {0x269, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C8000", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 344 | { BITS_EOT } |
| 345 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 346 | {0x26a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D0000", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 347 | { BITS_EOT } |
| 348 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 349 | {0x26b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D8000", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 350 | { BITS_EOT } |
| 351 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 352 | {0x26c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E0000", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 353 | { BITS_EOT } |
| 354 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 355 | {0x26d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E8000", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 356 | { BITS_EOT } |
| 357 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 358 | {0x26e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F0000", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 359 | { BITS_EOT } |
| 360 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 361 | {0x26f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F8000", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 362 | { BITS_EOT } |
| 363 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 364 | {0x2ff, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_DEF_TYPE", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 365 | { BITS_EOT } |
| 366 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 367 | {0x1107, MSRTYPE_RDWR, MSR2(0, 0), "FCR", |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 368 | "Feature Control Register", { |
| 369 | { 63, 55, RESERVED }, |
| 370 | { 8, 1, "Disables L2 Cache", "R/W", PRESENT_BIN, { |
| 371 | { MSR1(0), "L2 Cache enabled" }, |
| 372 | { MSR1(1), "L2 Cache disabled" }, |
| 373 | { BITVAL_EOT } |
| 374 | }}, |
| 375 | { 7, 6, RESERVED }, |
| 376 | { 1, 1, "Enables CPUID reporting CMPXCHG8B", "R/W", PRESENT_BIN, { |
| 377 | { MSR1(0), "Disabled CPUID reporting CMPXCHG8B" }, |
| 378 | { MSR1(1), "Enabled CPUID reporting CMPXCHG8B" }, |
| 379 | { BITVAL_EOT } |
| 380 | }}, |
| 381 | { 0, 1, RESERVED }, |
| 382 | { BITS_EOT } |
| 383 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 384 | {0x1108, MSRTYPE_RDWR, MSR2(0, 0), "FCR2", |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 385 | "Feature Control Register 2", { |
| 386 | { 63, 32, "Last 4 characters of Alternate Vendor ID string", "R/W", PRESENT_STR, { |
| 387 | { BITVAL_EOT } |
| 388 | }}, |
| 389 | { 31, 17, RESERVED }, |
| 390 | { 14, 1, "Use the Alternate Vendor ID string", "R/W", PRESENT_BIN, { |
| 391 | { MSR1(0), "The CPUID instruction vendor ID is CentaurHauls" }, |
| 392 | { MSR1(1), "The CPUID instruction returns the alternate Vendor ID" }, |
| 393 | { BITVAL_EOT } |
| 394 | }}, |
| 395 | { 13, 2, RESERVED }, |
| 396 | { 11, 4, "Family ID", "R/W", PRESENT_HEX, { |
| 397 | { BITVAL_EOT } |
| 398 | }}, |
| 399 | { 7, 4, "Model ID", "R/W", PRESENT_HEX, { |
| 400 | { BITVAL_EOT } |
| 401 | }}, |
| 402 | { 3, 4, RESERVED }, |
| 403 | { BITS_EOT } |
| 404 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 405 | {0x1109, MSRTYPE_WRONLY, MSR2(0, 0), "FCR3", |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 406 | "Feature Control Register 3", { |
| 407 | { 63, 32, "First 4 characters of Alternate Vendor ID string", "W/O", PRESENT_STR, { |
| 408 | { BITVAL_EOT } |
| 409 | }}, |
| 410 | { 31, 32, "Middle 4 characters of Alternate Vendor ID string", "W/O", PRESENT_STR, { |
| 411 | { BITVAL_EOT } |
| 412 | }}, |
| 413 | { BITS_EOT } |
| 414 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 415 | {0x1152, MSRTYPE_RDONLY, MSR2(0, 0), "FUSES", "Fuses", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 416 | { BITS_EOT } |
| 417 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 418 | {0x1153, MSRTYPE_RDONLY, MSR2(0, 0), "BRAND", |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 419 | "BRAND_1 XOR BRAND_2, (00b = C7-M, 01b = C7, 10b = Eden, 11b = Reserved)", { |
| 420 | { 63, 42, RESERVED }, |
| 421 | { 21, 2, "BRAND_1", "R/O", PRESENT_BIN, { |
| 422 | { BITVAL_EOT } |
| 423 | }}, |
| 424 | { 19, 2, "BRAND_2", "R/O", PRESENT_BIN, { |
| 425 | { BITVAL_EOT } |
| 426 | }}, |
| 427 | { 17, 18, RESERVED }, |
| 428 | { BITS_EOT } |
| 429 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 430 | {0x1160, MSRTYPE_RDWR, MSR2(0, 0), "UNK0", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 431 | { BITS_EOT } |
| 432 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 433 | {0x1161, MSRTYPE_RDWR, MSR2(0, 0), "UNK1", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 434 | { BITS_EOT } |
| 435 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 436 | {0x1164, MSRTYPE_RDWR, MSR2(0, 0), "THERM_THRESH_LOW", "(FUSES[6:4] * 5 + 65)", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 437 | { BITS_EOT } |
| 438 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 439 | {0x1165, MSRTYPE_RDWR, MSR2(0, 0), "THERM_THRESH_HI", "(FUSES[6:4] * 5 + 65) + 5", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 440 | { BITS_EOT } |
| 441 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 442 | {0x1166, MSRTYPE_RDWR, MSR2(0, 0), "THERM_THRESH_OVERSTRESS", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 443 | { BITS_EOT } |
| 444 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 445 | {0x1167, MSRTYPE_RDWR, MSR2(0, 0), "THERM_THRESH_USER_TRIP", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 446 | { BITS_EOT } |
| 447 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 448 | {0x1168, MSRTYPE_RDWR, MSR2(0, 0), "UNK2", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 449 | { BITS_EOT } |
| 450 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 451 | {0x116a, MSRTYPE_RDWR, MSR2(0, 0), "UNK3", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 452 | { BITS_EOT } |
| 453 | }}, |
Patrick Georgi | 5c65d00 | 2020-01-29 13:45:45 +0100 | [diff] [blame] | 454 | {0x116b, MSRTYPE_RDWR, MSR2(0, 0), "UNK4", "", { |
Lubomir Rintel | 6cc4dea | 2017-01-22 22:20:04 +0100 | [diff] [blame] | 455 | { BITS_EOT } |
| 456 | }}, |
| 457 | { MSR_EOT } |
| 458 | }; |