Angel Pons | c74dae9 | 2020-04-02 23:48:16 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <device/device.h> |
| 5 | #include <device/pci.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 6 | #include <device/pci_ops.h> |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 7 | #include <device/cardbus.h> |
| 8 | |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 9 | /* |
| 10 | * I don't think this code is quite correct but it is close. |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 11 | * Anyone with a cardbus bridge and a little time should be able |
| 12 | * to make it usable quickly. -- Eric Biederman 24 March 2005 |
| 13 | */ |
| 14 | |
| 15 | /* |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 16 | * IO should be max 256 bytes. However, since we may have a P2P bridge below |
| 17 | * a cardbus bridge, we need 4K. |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 18 | */ |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 19 | #define CARDBUS_IO_SIZE 4096 |
| 20 | #define CARDBUS_MEM_SIZE (32 * 1024 * 1024) |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 21 | |
Elyes HAOUAS | e18cbea | 2018-05-02 21:20:59 +0200 | [diff] [blame] | 22 | static void cardbus_record_bridge_resource(struct device *dev, resource_t moving, |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 23 | resource_t min_size, unsigned int index, unsigned long type) |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 24 | { |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 25 | struct resource *resource; |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 26 | unsigned long gran; |
| 27 | resource_t step; |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 28 | |
| 29 | /* Initialize the constraints on the current bus. */ |
Myles Watson | 03adcfd | 2010-06-07 16:51:11 +0000 | [diff] [blame] | 30 | resource = NULL; |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 31 | if (!moving) |
| 32 | return; |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 33 | |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 34 | resource = new_resource(dev, index); |
| 35 | resource->size = 0; |
| 36 | gran = 0; |
| 37 | step = 1; |
| 38 | while ((moving & step) == 0) { |
| 39 | gran += 1; |
| 40 | step <<= 1; |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 41 | } |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 42 | resource->gran = gran; |
| 43 | resource->align = gran; |
| 44 | resource->limit = moving | (step - 1); |
| 45 | resource->flags = type; |
| 46 | |
| 47 | /* Don't let the minimum size exceed what we can put in the resource. */ |
| 48 | if ((min_size - 1) > resource->limit) |
| 49 | min_size = resource->limit + 1; |
| 50 | |
| 51 | resource->size = min_size; |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 52 | } |
| 53 | |
Elyes HAOUAS | e18cbea | 2018-05-02 21:20:59 +0200 | [diff] [blame] | 54 | static void cardbus_size_bridge_resource(struct device *dev, unsigned int index) |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 55 | { |
| 56 | struct resource *resource; |
| 57 | resource_t min_size; |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 58 | |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 59 | resource = find_resource(dev, index); |
| 60 | if (resource) { |
| 61 | min_size = resource->size; |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 62 | /* |
Elyes HAOUAS | 394ec02 | 2018-08-07 12:23:43 +0200 | [diff] [blame] | 63 | * Always allocate at least the minimum size to a |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 64 | * cardbus bridge in case a new card is plugged in. |
| 65 | */ |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 66 | if (resource->size < min_size) |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 67 | resource->size = min_size; |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 68 | } |
| 69 | } |
| 70 | |
Elyes HAOUAS | e18cbea | 2018-05-02 21:20:59 +0200 | [diff] [blame] | 71 | void cardbus_read_resources(struct device *dev) |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 72 | { |
| 73 | resource_t moving_base, moving_limit, moving; |
| 74 | unsigned long type; |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 75 | u16 ctl; |
Ronald G. Minnich | 43225bc | 2005-11-22 00:07:02 +0000 | [diff] [blame] | 76 | |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 77 | /* See if needs a card control registers base address. */ |
Ronald G. Minnich | 43225bc | 2005-11-22 00:07:02 +0000 | [diff] [blame] | 78 | |
| 79 | pci_get_resource(dev, PCI_BASE_ADDRESS_0); |
| 80 | |
| 81 | compact_resources(dev); |
| 82 | |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 83 | /* See which bridge I/O resources are implemented. */ |
| 84 | moving_base = pci_moving_config32(dev, PCI_CB_IO_BASE_0); |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 85 | moving_limit = pci_moving_config32(dev, PCI_CB_IO_LIMIT_0); |
| 86 | moving = moving_base & moving_limit; |
| 87 | |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 88 | /* Initialize the I/O space constraints on the current bus. */ |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 89 | cardbus_record_bridge_resource(dev, moving, CARDBUS_IO_SIZE, |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 90 | PCI_CB_IO_BASE_0, IORESOURCE_IO); |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 91 | cardbus_size_bridge_resource(dev, PCI_CB_IO_BASE_0); |
| 92 | |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 93 | /* See which bridge I/O resources are implemented. */ |
| 94 | moving_base = pci_moving_config32(dev, PCI_CB_IO_BASE_1); |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 95 | moving_limit = pci_moving_config32(dev, PCI_CB_IO_LIMIT_1); |
| 96 | moving = moving_base & moving_limit; |
| 97 | |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 98 | /* Initialize the I/O space constraints on the current bus. */ |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 99 | cardbus_record_bridge_resource(dev, moving, CARDBUS_IO_SIZE, |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 100 | PCI_CB_IO_BASE_1, IORESOURCE_IO); |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 101 | |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 102 | /* If I can, enable prefetch for mem0. */ |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 103 | ctl = pci_read_config16(dev, PCI_CB_BRIDGE_CONTROL); |
| 104 | ctl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; |
| 105 | ctl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1; |
| 106 | ctl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; |
| 107 | pci_write_config16(dev, PCI_CB_BRIDGE_CONTROL, ctl); |
| 108 | ctl = pci_read_config16(dev, PCI_CB_BRIDGE_CONTROL); |
| 109 | |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 110 | /* See which bridge memory resources are implemented. */ |
| 111 | moving_base = pci_moving_config32(dev, PCI_CB_MEMORY_BASE_0); |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 112 | moving_limit = pci_moving_config32(dev, PCI_CB_MEMORY_LIMIT_0); |
| 113 | moving = moving_base & moving_limit; |
| 114 | |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 115 | /* Initialize the memory space constraints on the current bus. */ |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 116 | type = IORESOURCE_MEM; |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 117 | if (ctl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 118 | type |= IORESOURCE_PREFETCH; |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 119 | cardbus_record_bridge_resource(dev, moving, CARDBUS_MEM_SIZE, |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 120 | PCI_CB_MEMORY_BASE_0, type); |
| 121 | if (type & IORESOURCE_PREFETCH) |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 122 | cardbus_size_bridge_resource(dev, PCI_CB_MEMORY_BASE_0); |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 123 | |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 124 | /* See which bridge memory resources are implemented. */ |
| 125 | moving_base = pci_moving_config32(dev, PCI_CB_MEMORY_BASE_1); |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 126 | moving_limit = pci_moving_config32(dev, PCI_CB_MEMORY_LIMIT_1); |
| 127 | moving = moving_base & moving_limit; |
| 128 | |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 129 | /* Initialize the memory space constraints on the current bus. */ |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 130 | cardbus_record_bridge_resource(dev, moving, CARDBUS_MEM_SIZE, |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 131 | PCI_CB_MEMORY_BASE_1, IORESOURCE_MEM); |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 132 | cardbus_size_bridge_resource(dev, PCI_CB_MEMORY_BASE_1); |
| 133 | |
| 134 | compact_resources(dev); |
| 135 | } |
| 136 | |
Elyes HAOUAS | e18cbea | 2018-05-02 21:20:59 +0200 | [diff] [blame] | 137 | void cardbus_enable_resources(struct device *dev) |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 138 | { |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 139 | u16 ctrl; |
| 140 | |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 141 | ctrl = pci_read_config16(dev, PCI_CB_BRIDGE_CONTROL); |
Myles Watson | 894a347 | 2010-06-09 22:41:35 +0000 | [diff] [blame] | 142 | ctrl |= (dev->link_list->bridge_ctrl & ( |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 143 | PCI_BRIDGE_CTL_NO_ISA | |
| 144 | PCI_BRIDGE_CTL_VGA | |
| 145 | PCI_BRIDGE_CTL_MASTER_ABORT | |
| 146 | PCI_BRIDGE_CTL_BUS_RESET)); |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 147 | /* Error check */ |
Kyösti Mälkki | 382e216 | 2019-09-21 16:19:32 +0300 | [diff] [blame] | 148 | ctrl |= (PCI_CB_BRIDGE_CTL_PARITY | PCI_CB_BRIDGE_CTL_SERR); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 149 | printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl); |
Kyösti Mälkki | 0bca050 | 2019-09-21 16:21:47 +0300 | [diff] [blame] | 150 | pci_write_config16(dev, PCI_CB_BRIDGE_CONTROL, ctrl); |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 151 | |
| 152 | pci_dev_enable_resources(dev); |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 153 | } |
| 154 | |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 155 | struct device_operations default_cardbus_ops_bus = { |
| 156 | .read_resources = cardbus_read_resources, |
| 157 | .set_resources = pci_dev_set_resources, |
| 158 | .enable_resources = cardbus_enable_resources, |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 159 | .scan_bus = pci_scan_bridge, |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 160 | .reset_bus = pci_bus_reset, |
| 161 | }; |