| Frans Hendriks | ed52e3d | 2019-07-15 08:48:55 +0200 | [diff] [blame^] | 1 | # |
| 2 | # This file is part of the coreboot project. |
| 3 | # |
| 4 | # Copyright (C) 2019 Eltan B.V. |
| 5 | # |
| 6 | # This program is free software; you can redistribute it and/or modify |
| 7 | # it under the terms of the GNU General Public License as published by |
| 8 | # the Free Software Foundation; version 2 of the License. |
| 9 | # |
| 10 | # This program is distributed in the hope that it will be useful, |
| 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | # GNU General Public License for more details. |
| 14 | # |
| 15 | |
| 16 | # |
| 17 | # 8 Gb DDR3 (1600 MHz 11-11-11) Micron MT41K512M16HA-125:A |
| 18 | # |
| 19 | # SINGLE DIE |
| 20 | # |
| 21 | |
| 22 | # 512MBx16 64Mx16x8 ( 8 bank, 16 Rows, 10 Col, 2 KB page size ) |
| 23 | # 5-6-7-8-9-10-11 |
| 24 | # DDR3L-1600 |
| 25 | # tCk 1.25ns |
| 26 | # tRCD 13.75ns |
| 27 | # tRP 13.75ns |
| 28 | # tRAS 35ns |
| 29 | # tRC 48.75ns |
| 30 | # CL-tRCD-tRP 11-11-11 |
| 31 | |
| 32 | # 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage |
| 33 | # bits[3:0]: 3 = 384 SPD Bytes Used |
| 34 | # bits[6:4]: 1 = 256 SPD Bytes Total |
| 35 | # bit7 : 0 = CRC covers bytes 0 ~ 128 |
| 36 | 23 |
| 37 | |
| 38 | # 1 SPD Revision |
| 39 | # 0x10 = Revision 1.0 |
| 40 | 10 |
| 41 | |
| 42 | # 2 Key Byte / DRAM Device Type |
| 43 | # bits[7:0]: 0x0c = DDR3 SDRAM |
| 44 | 0B |
| 45 | |
| 46 | # 3 Key Byte / Module Type |
| 47 | # bits[3:0]: 3 = SODIMM |
| 48 | # bits[6:4]: 0 = Not hybrid |
| 49 | # bits[7]: 0 = Not hybrid |
| 50 | 03 |
| 51 | |
| 52 | # 4 SDRAM CHIP Density and Banks |
| 53 | # bits[3:0]: 5 = 8 Gigabits Total SDRAM capacity per chip |
| 54 | # bits[6:4]: 0 = 3 (8 banks) |
| 55 | # bits[7]: reserverd |
| 56 | 05 |
| 57 | |
| 58 | # 5 SDRAM Addressing |
| 59 | # bits[2:0]: 1 = 10 Column Address Bits |
| 60 | # bits[5:3]: 4 = 16 Row Address Bits |
| 61 | # bits[7:6]: 0 = reserved |
| 62 | 21 |
| 63 | |
| 64 | # 6 Module Nominal Voltage |
| 65 | # bits[0]: 0 = 1.5V operable |
| 66 | # bits[1]: 1 = 1.35V operable |
| 67 | # bits[2]: 0 = NOT 1.25V operable |
| 68 | # bits[7:3]: reserved |
| 69 | 02 |
| 70 | |
| 71 | # 7 Module Organization |
| 72 | # bits[2:0]: 010b = 16 bits SDRAM device |
| 73 | # bits[5:3]: 000b = 1 ranks |
| 74 | # bits[7:6]: reserved |
| 75 | 02 |
| 76 | |
| 77 | # 8 Module Memory Bus width |
| 78 | # bits[2:0]: 3 = 64 bits pirmary bus width |
| 79 | # bits[4:3]: 0 = 0 bits bus witdth extension |
| 80 | # bits[7:5]: reserved |
| 81 | 03 |
| 82 | |
| 83 | # 9 Fine Timebase (FTB) dividend / divisor |
| 84 | # bits[3:0]: 1 = Divisor |
| 85 | # bits[7:4]: 1 = Dividend |
| 86 | 11 |
| 87 | |
| 88 | # 10 Medium Timebase (MTB) dividend |
| 89 | # bits[7:0]: 0 = 1 (timebase 0.125ns) |
| 90 | 01 |
| 91 | |
| 92 | # 11 Medium Timebase (MTB) divisor |
| 93 | # bits[7:0]: 8 (timebase 0.125ns) |
| 94 | 08 |
| 95 | |
| 96 | # 12 SDRAM Minimum cycle time (tCKmin) |
| 97 | # 0xA tCK = 1.25ns (DDR3-1600 (800 MHz clock)) |
| 98 | 0A |
| 99 | |
| 100 | # 13 Reserved |
| 101 | 00 |
| 102 | |
| 103 | # 14 CAS Latencies supported, Least Significate Byte |
| 104 | # Support 5,6,7,8,9,10,11 |
| 105 | FE |
| 106 | |
| 107 | # 15 CAS Latencies supported, Most Significate Byte |
| 108 | # No supporting CL 12-18 |
| 109 | 00 |
| 110 | |
| 111 | # 16 Minimum CAS Latency Time (tAAmin) |
| 112 | # 0x69 tAA = 13.125ns (offset = 00) DDR3-1600K downbin |
| 113 | 69 |
| 114 | |
| 115 | # 17 Minimum Write Recovery Time (tWRmin) |
| 116 | # 0x78 tWR = 15 ns |
| 117 | 78 |
| 118 | |
| 119 | # 18 Minimum RAS to CAS Delay Time (tRCDmin) |
| 120 | # 0x69 tRCD = 13.125ns (offset 00) DDR3-1600K downbin |
| 121 | 69 |
| 122 | |
| 123 | # 19 Minimum Row Active to Row Active Delay Time (tRRDmin) |
| 124 | # 0x3C tRRD = 7.5ns DDR3-1600, 2KB |
| 125 | 3C |
| 126 | |
| 127 | # 20 Minimum Row Precharge Delay Time (tRPmin) |
| 128 | # 0x69 tRP = 13.125ns (offset 00) DDR3-1600K downbin |
| 129 | 69 |
| 130 | |
| 131 | # 21 Upper Nibble for tRAS and tRC |
| 132 | # 3:0 : 1 higher tRAS = 35ns |
| 133 | # 7:0 : 1 higher tRC = 48.125ns |
| 134 | 11 |
| 135 | |
| 136 | # 22 Minimum Active to Precharge Delay Time (tRASmin), Least Significant byte |
| 137 | # lower 0x118 : tRAS = 35ns DDR3-1600 |
| 138 | 18 |
| 139 | |
| 140 | # 23 Minimum Active to Precharge Delay Time (tRCmin), Most Significant byte |
| 141 | # lower 0x181 : tRC = 48.125ns (offset 00) DDR3-1600K downbin |
| 142 | 81 |
| 143 | |
| 144 | # 24 Minimum Refresh Recovery Delay time (tRFCmin), Least Significant byte |
| 145 | # lower 0xAF0 : tRFC = 350ns 8 Gb |
| 146 | F0 |
| 147 | |
| 148 | # 25 Minimum Refresh Recovery Delay time (tRFCmin), Most Significant byte |
| 149 | # higher 0xAF0 : tRFC = 350ns 8 Gb |
| 150 | 0A |
| 151 | |
| 152 | # 26 tWTRmin |
| 153 | # 0x3C : tWTR = 7.5 ns (DDR3) |
| 154 | 3C |
| 155 | |
| 156 | # 27 tRTPmin |
| 157 | # 0x3C : tRTP = 7.5 ns (DDR3) |
| 158 | 3C |
| 159 | |
| 160 | # 28 Upper Nibble for tFAW |
| 161 | # Bit [3:0] : 1 = higher 0x140 tFAW = 40ns |
| 162 | 01 |
| 163 | |
| 164 | # 29 tFAWmin Lower |
| 165 | # lower 0x140 : tFAW = 40ns |
| 166 | 40 |
| 167 | |
| 168 | # 30 SDRAM Optional Features |
| 169 | # byte [0] : 1 = RZQ/6 is support |
| 170 | # byte [1] : 1 = RZQ/7 is supported |
| 171 | # byte [7] : 1 = DLL-Off Mode support |
| 172 | 83 |
| 173 | |
| 174 | # 31 Thermal options |
| 175 | # byte [0] : 1 = 0 - 95C |
| 176 | # byte [2] : 1 = Auto Self Refresh (ASR) is supported |
| 177 | # byte [7] : 1 = Partial Array Self Refres (PASR) is supported |
| 178 | 85 |
| 179 | |
| 180 | # 32 Module Thermal support |
| 181 | # byte [0] : 0 = Thermal sensor accuracy undefined |
| 182 | # byte [7] : 0 = No thermal sensor |
| 183 | 00 |
| 184 | |
| 185 | # 33 SDRAM device type |
| 186 | # byte [1:0] : 00b = Signal Loading not specified |
| 187 | # byte [6:4] : 000b = Die count not specified |
| 188 | # byte [7] : 1 = Non-Standard Device |
| 189 | 80 |
| 190 | |
| 191 | # 34 Fine tCKmin |
| 192 | # 0x00 tCK = 1.25ns (DDR3-1600 (800 MHz clock)) |
| 193 | 00 |
| 194 | |
| 195 | # 35 Fine tAAmin |
| 196 | # 0x00 tAA = 13.125ns (tAAmin offset = 00) DDR3-1600K downbin |
| 197 | 00 |
| 198 | |
| 199 | # 36 Fine tRCDmin |
| 200 | # 0x00 tRCD = 13.125ns DDR3-1600K downbin |
| 201 | 00 |
| 202 | |
| 203 | # 37 Fine tRPmin |
| 204 | # 0x00 tRP = 13.125ns (offset 00) DDR3-1600K downbin |
| 205 | 00 |
| 206 | |
| 207 | # 38 Fine tRCmin |
| 208 | # 0x00 tRC = 48.125ns (offset 00) DDR3-1600K downbin |
| 209 | 00 |
| 210 | |
| 211 | # 39-59 reserved, general section |
| 212 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |
| 213 | 00 00 00 00 00 |
| 214 | |
| 215 | # 60-116 Module specific section |
| 216 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |
| 217 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |
| 218 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |
| 219 | 00 00 00 00 00 00 00 00 00 |
| 220 | |
| 221 | # 117-118 Module Manufacturer |
| 222 | 80 2C |
| 223 | |
| 224 | # 119 Module Manufacturing Location |
| 225 | 01 |
| 226 | |
| 227 | # 120-121 Module Manufacturing Date |
| 228 | 13 0A |
| 229 | |
| 230 | # 122-125 Module Serial number |
| 231 | 00 00 00 00 |
| 232 | |
| 233 | # 126-127 SPD CRC |
| 234 | 00 00 |
| 235 | |
| 236 | # 128-145 Module Part number |
| 237 | 4D 54 34 31 4B 35 31 32 4D 31 36 48 41 2D 31 32 |
| 238 | 35 00 |
| 239 | |
| 240 | # 145-146 Module revision code |
| 241 | 00 00 |
| 242 | |
| 243 | # 148-149 DRAM Manufacturer ID code |
| 244 | 80 2C |
| 245 | |
| 246 | # 150-175 Manufacturer Specific Data |
| 247 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |
| 248 | 00 00 00 00 00 00 00 00 00 00 |
| 249 | |
| 250 | # 176-255 Open for Customer Use |
| 251 | |
| 252 | # 176 - 255 |
| 253 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |
| 254 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |
| 255 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |
| 256 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |
| 257 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |