Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007 - 2009 coresystems GmbH |
| 5 | * Copyright (C) 2014 - 2017 Intel Corporation. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | */ |
| 17 | |
| 18 | #include "../include/soc/iomap.h" |
| 19 | |
| 20 | Name(_HID,EISAID("PNP0A08")) // PCIe |
| 21 | Name(_CID,EISAID("PNP0A03")) // PCI |
| 22 | |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 23 | Name(_BBN, 0) |
| 24 | |
| 25 | Device (MCHC) |
| 26 | { |
| 27 | Name(_ADR, 0x00000000) // 0:0.0 |
| 28 | |
| 29 | OperationRegion(MCHP, PCI_Config, 0x00, 0x100) |
| 30 | Field (MCHP, DWordAcc, NoLock, Preserve) |
| 31 | { |
| 32 | Offset (0x48), // MCHBAR |
| 33 | MHEN, 1, // Enable |
| 34 | , 13, // |
| 35 | MHBR, 22, // MCHBAR |
| 36 | |
| 37 | Offset (0x60), // PCIe BAR |
| 38 | PXEN, 1, // Enable |
| 39 | PXSZ, 2, // BAR size |
| 40 | , 23, // |
| 41 | PXBR, 10, // PCIe BAR |
| 42 | |
| 43 | Offset (0xa8), // Top of Upper Memory |
| 44 | TUUD, 64, |
| 45 | |
| 46 | Offset (0xb8), // TSEGMB |
| 47 | TSEG, 32, |
| 48 | |
| 49 | Offset (0xbc), // Top of Low Used Memory |
| 50 | TLUD, 32, |
| 51 | } |
| 52 | } |
| 53 | |
| 54 | // Current Resource Settings |
| 55 | |
| 56 | Name (MCRS, ResourceTemplate() |
| 57 | { |
| 58 | // Bus Numbers |
| 59 | WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, |
| 60 | 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) |
| 61 | |
| 62 | // IO Region 0 |
| 63 | DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
| 64 | 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) |
| 65 | |
| 66 | // PCI Config Space |
| 67 | Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) |
| 68 | |
| 69 | // IO Region 1 |
| 70 | DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
| 71 | 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) |
| 72 | |
| 73 | // VGA memory (0xa0000-0xbffff) |
| 74 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 75 | Cacheable, ReadWrite, |
| 76 | 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, |
| 77 | 0x00020000,,, ASEG) |
| 78 | |
| 79 | // RAM (0xc0000-0xdffff) |
| 80 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 81 | Cacheable, ReadWrite, |
| 82 | 0x00000000, 0x000c0000, 0x000dffff, 0x00000000, |
| 83 | 0x00020000,,, OPR0) |
| 84 | |
| 85 | // PCI Memory Region (Top of memory-PCIEXBAR) |
| 86 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 87 | NonCacheable, ReadWrite, |
| 88 | 0x00000000, 0x00000000, 0xfebfffff, 0x00000000, |
| 89 | 0xfec00000,,, PM01) |
| 90 | |
| 91 | #ifdef ENABLE_TPM |
| 92 | // TPM Area (0xfed40000-0xfed44fff) |
| 93 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 94 | Cacheable, ReadWrite, |
| 95 | 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, |
| 96 | 0x00005000,,, TPMR) |
| 97 | #endif |
| 98 | |
| 99 | // PCI Memory Region (TOUUD - 64G) |
| 100 | QWORDMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 101 | NonCacheable, ReadWrite, |
| 102 | 0x00000000, 0x00000000, 0x1ffffffff, 0x00000000, |
| 103 | 0x200000000,,, PM02) |
| 104 | |
| 105 | }) // End MCRS |
| 106 | |
| 107 | Method (_CRS, 0, Serialized) |
| 108 | { |
| 109 | // Find PCI resource area in MCRS |
| 110 | CreateDwordField(MCRS, ^PM01._MIN, PMIN) |
| 111 | CreateDwordField(MCRS, ^PM01._MAX, PMAX) |
| 112 | CreateDwordField(MCRS, ^PM01._LEN, PLEN) |
| 113 | |
| 114 | // MMIO Low is saved in NVS |
| 115 | Store (\MMOB, PMIN) |
| 116 | Store (\MMOL, PMAX) |
| 117 | Add (Subtract (PMAX, PMIN), 1, PLEN) |
| 118 | |
| 119 | // Find PCI resource area in MCRS |
| 120 | CreateQWordField(MCRS, ^PM02._MIN, P2MN) |
| 121 | CreateQWordField(MCRS, ^PM02._MAX, P2MX) |
| 122 | CreateQWordField(MCRS, ^PM02._LEN, P2LN) |
| 123 | |
| 124 | // MMIO High is saved in NVS |
| 125 | Store(\MMHB, P2MN) |
| 126 | Store(\MMHL, P2MX) |
| 127 | Add(Subtract(P2MX,P2MN),1,P2LN) |
| 128 | |
| 129 | Return (MCRS) |
| 130 | } // End _CRS |
| 131 | |
| 132 | /* PCI Device Resource Consumption */ |
| 133 | Device (PDRC) |
| 134 | { |
| 135 | Name (_HID, EISAID("PNP0C02")) |
| 136 | Name (_UID, 1) |
| 137 | |
| 138 | Name (PDRS, ResourceTemplate() { |
| 139 | // PCIEXBAR memory range |
Kyösti Mälkki | 503d324 | 2019-03-05 07:54:28 +0200 | [diff] [blame] | 140 | Memory32Fixed(ReadOnly, CONFIG_MMCONF_BASE_ADDRESS, 0x10000000) |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 141 | // TSEG |
| 142 | Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, TSMB) |
| 143 | }) |
| 144 | |
| 145 | // Current Resource Settings |
| 146 | Method (_CRS, 0, Serialized) |
| 147 | { |
| 148 | // Fix up 32-bit TSEG |
| 149 | CreateDWordField(PDRS, ^TSMB._BAS, TSMN) |
| 150 | Store(\TSGB, TSMN) |
| 151 | CreateDWordField(PDRS, ^TSMB._LEN, TSLN) |
| 152 | Store(\TSSZ, TSLN) |
| 153 | Return(PDRS) |
| 154 | } |
| 155 | } |
| 156 | |
| 157 | // Global Registers |
| 158 | Device (GREG) { |
| 159 | Name (_ADR, 0x00040000) |
| 160 | } |
| 161 | |
| 162 | // Root Complex Event Collector |
| 163 | Device (RCEC) { |
| 164 | Name (_ADR, 0x00050000) |
| 165 | } |
| 166 | |
| 167 | // Virtual root port 2 |
| 168 | Device (VRP2) { |
| 169 | Name (_ADR, 0x00060000) |
Stephen Douthit | ecb0e40 | 2019-08-05 11:53:35 -0400 | [diff] [blame^] | 170 | |
| 171 | Method (_PRT) |
| 172 | { |
| 173 | Return (IRQM (6)) |
| 174 | } |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 175 | } |