Ravi Sarawadi | e02fd83 | 2022-05-08 00:27:31 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
| 3 | OperationRegion (DPME, SystemMemory, BASE(_ADR), 0x100) |
| 4 | Field (DPME, AnyAcc, NoLock, Preserve) |
| 5 | { |
| 6 | VDID, 32, |
| 7 | Offset(0x84), /* 0x84, DMA CFG PM CAP */ |
| 8 | PMST, 2, /* 1:0, PM_STATE */ |
| 9 | , 6, |
| 10 | PMEE, 1, /* 8, PME_EN */ |
| 11 | , 6, |
| 12 | PMES, 1, /* 15, PME_STATUS */ |
| 13 | Offset(0xC8), /* 0xC8, TBT NVM FW Revision */ |
Ravi Sarawadi | ebd4c3d | 2023-10-26 13:25:35 -0700 | [diff] [blame^] | 14 | , 31, |
Ravi Sarawadi | e02fd83 | 2022-05-08 00:27:31 -0700 | [diff] [blame] | 15 | INFR, 1, /* TBT NVM FW Ready */ |
| 16 | Offset(0xEC), /* 0xEC, TBT TO PCIE Register */ |
| 17 | TB2P, 32, /* TBT to PCIe */ |
| 18 | P2TB, 32, /* PCIe to TBT */ |
| 19 | Offset(0xFC), /* 0xFC, DMA RTD3 Force Power */ |
| 20 | DD3E, 1, /* 0:0 DMA RTD3 Enable */ |
| 21 | DFPE, 1, /* 1:1 DMA Force Power */ |
| 22 | , 22, |
| 23 | DMAD, 8 /* 31:24 DMA Active Delay */ |
| 24 | } |
| 25 | |
| 26 | Name (STAT, 0x1) /* Variable to save power state 1 - D0, 0 - D3C */ |
| 27 | |
| 28 | Method (_S0W, 0x0) |
| 29 | { |
Sean Rhodes | e24d9d6 | 2023-04-17 20:42:47 +0100 | [diff] [blame] | 30 | #if CONFIG(D3COLD_SUPPORT) |
Sean Rhodes | 53048c2a | 2023-08-25 13:46:08 +0100 | [diff] [blame] | 31 | Return (0x04) |
Sean Rhodes | e24d9d6 | 2023-04-17 20:42:47 +0100 | [diff] [blame] | 32 | #else |
Sean Rhodes | 53048c2a | 2023-08-25 13:46:08 +0100 | [diff] [blame] | 33 | Return (0x03) |
Sean Rhodes | e24d9d6 | 2023-04-17 20:42:47 +0100 | [diff] [blame] | 34 | #endif // D3COLD_SUPPORT |
Ravi Sarawadi | e02fd83 | 2022-05-08 00:27:31 -0700 | [diff] [blame] | 35 | } |
| 36 | |
Sean Rhodes | 53048c2a | 2023-08-25 13:46:08 +0100 | [diff] [blame] | 37 | /* |
| 38 | * Get power resources that are dependent on this device for Operating System Power Management |
| 39 | * to put the device in the D0 device state |
| 40 | */ |
Ravi Sarawadi | e02fd83 | 2022-05-08 00:27:31 -0700 | [diff] [blame] | 41 | Method (_PR0) |
| 42 | { |
Sean Rhodes | e24d9d6 | 2023-04-17 20:42:47 +0100 | [diff] [blame] | 43 | #if CONFIG(D3COLD_SUPPORT) |
Ravi Sarawadi | e02fd83 | 2022-05-08 00:27:31 -0700 | [diff] [blame] | 44 | If (DUID == 0) { |
| 45 | Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) |
| 46 | } Else { |
| 47 | Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) |
| 48 | } |
Sean Rhodes | e24d9d6 | 2023-04-17 20:42:47 +0100 | [diff] [blame] | 49 | #else |
| 50 | If (DUID == 0) { |
| 51 | Return (Package() { \_SB.PCI0.TBT0 }) |
| 52 | } Else { |
| 53 | Return (Package() { \_SB.PCI0.TBT1 }) |
| 54 | } |
Sean Rhodes | 53048c2a | 2023-08-25 13:46:08 +0100 | [diff] [blame] | 55 | #endif // D3COLD_SUPPORT |
Ravi Sarawadi | e02fd83 | 2022-05-08 00:27:31 -0700 | [diff] [blame] | 56 | } |
| 57 | |
| 58 | Method (_PR3) |
| 59 | { |
Sean Rhodes | e24d9d6 | 2023-04-17 20:42:47 +0100 | [diff] [blame] | 60 | #if CONFIG(D3COLD_SUPPORT) |
Ravi Sarawadi | e02fd83 | 2022-05-08 00:27:31 -0700 | [diff] [blame] | 61 | If (DUID == 0) { |
| 62 | Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) |
| 63 | } Else { |
| 64 | Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) |
| 65 | } |
Sean Rhodes | e24d9d6 | 2023-04-17 20:42:47 +0100 | [diff] [blame] | 66 | #else |
| 67 | If (DUID == 0) { |
| 68 | Return (Package() { \_SB.PCI0.TBT0 }) |
| 69 | } Else { |
| 70 | Return (Package() { \_SB.PCI0.TBT1 }) |
| 71 | } |
| 72 | #endif // D3COLD_SUPPORT |
Ravi Sarawadi | e02fd83 | 2022-05-08 00:27:31 -0700 | [diff] [blame] | 73 | } |
| 74 | |
| 75 | /* |
| 76 | * RTD3 Exit Method to bring TBT controller out of RTD3 mode. |
| 77 | */ |
| 78 | Method (D3CX, 0, Serialized) |
| 79 | { |
Sean Rhodes | 53048c2a | 2023-08-25 13:46:08 +0100 | [diff] [blame] | 80 | DD3E = 0x00 /* Disable DMA RTD3 */ |
| 81 | STAT = 0x01 |
Ravi Sarawadi | e02fd83 | 2022-05-08 00:27:31 -0700 | [diff] [blame] | 82 | } |
| 83 | |
| 84 | /* |
| 85 | * RTD3 Entry method to enable TBT controller RTD3 mode. |
| 86 | */ |
| 87 | Method (D3CE, 0, Serialized) |
| 88 | { |
Sean Rhodes | 53048c2a | 2023-08-25 13:46:08 +0100 | [diff] [blame] | 89 | DD3E = 0x01 /* Enable DMA RTD3 */ |
| 90 | STAT = 0x00 |
Ravi Sarawadi | e02fd83 | 2022-05-08 00:27:31 -0700 | [diff] [blame] | 91 | } |
| 92 | |
| 93 | /* |
| 94 | * Variable to skip TCSS/TBT D3 cold; 1+: Skip D3CE, 0 - Enable D3CE |
| 95 | * TCSS D3 Cold and TBT RTD3 is only available when system power state is in S0. |
| 96 | */ |
| 97 | Name (SD3C, 0) |
| 98 | |
| 99 | Method (_DSW, 3) |
| 100 | { |
| 101 | /* If entering Sx (Arg1 > 1), need to skip TCSS D3Cold & TBT RTD3/D3Cold. */ |
| 102 | SD3C = Arg1 |
| 103 | } |
| 104 | |
| 105 | Method (_PRW, 0) |
| 106 | { |
| 107 | Return (Package() { 0x6D, 4 }) |
| 108 | } |