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review.coreboot.org / coreboot / ebabfadcec7807d4e472fcf7fb6707a21201614e / . / src / soc / broadcom / cygnus / shmoo_and28.c
blob: aba3cf39909d4bd8dff20898d72c8b7e7ef003a0 [file] [log] [blame]
Icarus Chaud5f551a2015-02-13 15:16:37 -0800[diff] [blame]1/*
2* Copyright (C) 2015 Broadcom Corporation
3*
4* This program is free software; you can redistribute it and/or
5* modify it under the terms of the GNU General Public License as
6* published by the Free Software Foundation version 2.
7*
8* This program is distributed "as is" WITHOUT ANY WARRANTY of any
9* kind, whether express or implied; without even the implied warranty
10* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11* GNU General Public License for more details.
12*/
13
14
15#include <string.h>
16#include <soc/config.h>
17#include <soc/reg_utils.h>
18
19#define SOC_IF_ERROR_RETURN(x) (x)
20#define sal_memset(x,y,z) memset(x,y,z)
21#define sal_usleep(x) udelay(x)
22
23/* BEGIN: TEMPORARY */
24#ifndef BCM_AND28_SUPPORT
25#define BCM_AND28_SUPPORT
26#endif
27/* END: TEMPORARY */
28
29#if IS_ENABLED(CONFIG_CYGNUS_PRINT_SHMOO_DEBUG)
30#define PLOT_SUPPORT
31#endif
32
33#ifdef BCM_AND28_SUPPORT
34#include <soc/shmoo_and28/shmoo_and28.h>
35#include <soc/shmoo_and28/phy_reg_access.h>
36#include <soc/shmoo_and28/ydc_ddr_bist.h>
37
38#ifdef PHY_AND28_E2
39#include <soc/shmoo_and28/phy_and28_e2.h>
40#else
41#error "Phy_AND version is not defined."
42#endif
43#endif
44
45and28_shmoo_dram_info_t *shmoo_dram_info_ptr;
46static and28_shmoo_dram_info_t shmoo_dram_info;
47static and28_shmoo_container_t shmoo_container = {0};
48
49#if (SHMOO_AND28_DRAM_TYPE == SHMOO_AND28_DRAM_TYPE_DDR3)
50const uint32 shmoo_order_and28_ddr3[SHMOO_AND28_DDR3_SEQUENCE_COUNT] =
51{
52 SHMOO_AND28_RD_EN,
53 SHMOO_AND28_RD_EXTENDED,
54 SHMOO_AND28_WR_EXTENDED,
55 SHMOO_AND28_ADDR_EXTENDED,
56 SHMOO_AND28_CTRL_EXTENDED
57};
58#endif
59
60#if (SHMOO_AND28_DRAM_TYPE == SHMOO_AND28_DRAM_TYPE_DDR3L)
61const uint32 shmoo_order_and28_ddr3l[SHMOO_AND28_DDR3L_SEQUENCE_COUNT] =
62{
63 SHMOO_AND28_RD_EN,
64 SHMOO_AND28_RD_EXTENDED,
65 SHMOO_AND28_WR_EXTENDED,
66 SHMOO_AND28_ADDR_EXTENDED,
67 SHMOO_AND28_CTRL_EXTENDED
68};
69#endif
70
71/* Local function prototype */
72uint32 _shmoo_and28_check_dram(int phy_ndx);
73int _and28_calculate_step_size(int unit, int phy_ndx, and28_step_size_t *ssPtr);
74int _and28_zq_calibration(int unit, int phy_ndx);
75int _soc_and28_shmoo_phy_cfg_pll(int unit, int phy_ndx);
76
77uint32
78_shmoo_and28_check_dram(int phy_ndx)
79{
80 return ((shmoo_dram_info_ptr->dram_bitmap >> phy_ndx) & 0x1);
81}
82
83static int
84_initialize_bist(int unit, int phy_ndx, int bit, and28_shmoo_container_t *scPtr)
85{
86 ydc_ddr_bist_info_t bist_info;
87
88 switch ((*scPtr).shmooType) {
89 case SHMOO_AND28_RD_EN:
90 bist_info.write_weight = 255;
91 bist_info.read_weight = 255;
92 bist_info.bist_timer_us = 0;
93 bist_info.bist_num_actions = 510;
94 bist_info.bist_start_address = 0x00000000;
95 bist_info.bist_end_address = 0x00FFFFFF;
96 bist_info.mpr_mode = 0;
97 bist_info.prbs_mode = 1;
98 break;
99 case SHMOO_AND28_RD_EXTENDED:
100 bist_info.write_weight = 255;
101 bist_info.read_weight = 255;
102 bist_info.bist_timer_us = 0;
103 bist_info.bist_num_actions = 510;
104 bist_info.bist_start_address = 0x00000000;
105 bist_info.bist_end_address = 0x00FFFFFF;
106 bist_info.mpr_mode = 0;
107 bist_info.prbs_mode = 1;
108 break;
109 case SHMOO_AND28_WR_EXTENDED:
110 bist_info.write_weight = 255;
111 bist_info.read_weight = 255;
112 bist_info.bist_timer_us = 0;
113 bist_info.bist_num_actions = 510;
114 bist_info.bist_start_address = 0x00000000;
115 bist_info.bist_end_address = 0x00FFFFFF;
116 bist_info.mpr_mode = 0;
117 bist_info.prbs_mode = 1;
118 break;
119 case SHMOO_AND28_ADDR_EXTENDED:
120 bist_info.write_weight = 255;
121 bist_info.read_weight = 255;
122 bist_info.bist_timer_us = 0;
123 bist_info.bist_num_actions = 510;
124 bist_info.bist_start_address = 0x00000000;
125 bist_info.bist_end_address = 0x00FFFFFF;
126 bist_info.mpr_mode = 0;
127 bist_info.prbs_mode = 1;
128 break;
129 case SHMOO_AND28_CTRL_EXTENDED:
130 bist_info.write_weight = 255;
131 bist_info.read_weight = 255;
132 bist_info.bist_timer_us = 0;
133 bist_info.bist_num_actions = 510;
134 bist_info.bist_start_address = 0x00000000;
135 bist_info.bist_end_address = 0x00FFFFFF;
136 bist_info.mpr_mode = 0;
137 bist_info.prbs_mode = 1;
138 break;
139 default:
140 printf("Unsupported shmoo type: %02u\n", (*scPtr).shmooType);
141 return SOC_E_FAIL;
142 }
143
144 return soc_ydc_ddr_bist_config_set(unit, phy_ndx, &bist_info);
145}
146
147static int
148_run_bist(int unit, int phy_ndx, and28_shmoo_container_t *scPtr, and28_shmoo_error_array_t *seaPtr)
149{
150 ydc_ddr_bist_err_cnt_t be;
151
152 switch ((*scPtr).shmooType) {
153 case SHMOO_AND28_RD_EN:
154 SOC_IF_ERROR_RETURN(soc_ydc_ddr_bist_run(unit, phy_ndx, &be));
155
156 if(shmoo_dram_info_ptr->interface_bitwidth == 16)
157 {
158 (*seaPtr)[0] = (((be.bist_err_occur) >> 16) | (be.bist_err_occur)) & 0xFFFF;
159 }
160 else
161 {
162 (*seaPtr)[0] = be.bist_err_occur;
163 }
164 break;
165 case SHMOO_AND28_RD_EXTENDED:
166 SOC_IF_ERROR_RETURN(soc_ydc_ddr_bist_run(unit, phy_ndx, &be));
167
168 if(shmoo_dram_info_ptr->interface_bitwidth == 16)
169 {
170 (*seaPtr)[0] = (((be.bist_err_occur) >> 16) | (be.bist_err_occur)) & 0xFFFF;
171 }
172 else
173 {
174 (*seaPtr)[0] = be.bist_err_occur;
175 }
176 break;
177 case SHMOO_AND28_WR_EXTENDED:
178 SOC_IF_ERROR_RETURN(soc_ydc_ddr_bist_run(unit, phy_ndx, &be));
179
180 if(shmoo_dram_info_ptr->interface_bitwidth == 16)
181 {
182 (*seaPtr)[0] = (((be.bist_err_occur) >> 16) | (be.bist_err_occur)) & 0xFFFF;
183 }
184 else
185 {
186 (*seaPtr)[0] = be.bist_err_occur;
187 }
188 break;
189 case SHMOO_AND28_ADDR_EXTENDED:
190 SOC_IF_ERROR_RETURN(soc_ydc_ddr_bist_run(unit, phy_ndx, &be));
191
192 if(shmoo_dram_info_ptr->interface_bitwidth == 16)
193 {
194 (*seaPtr)[0] = (((be.bist_err_occur) >> 16) | (be.bist_err_occur)) & 0xFFFF;
195 }
196 else
197 {
198 (*seaPtr)[0] = be.bist_err_occur;
199 }
200 break;
201 case SHMOO_AND28_CTRL_EXTENDED:
202 SOC_IF_ERROR_RETURN(soc_ydc_ddr_bist_run(unit, phy_ndx, &be));
203
204 if(shmoo_dram_info_ptr->interface_bitwidth == 16)
205 {
206 (*seaPtr)[0] = (((be.bist_err_occur) >> 16) | (be.bist_err_occur)) & 0xFFFF;
207 }
208 else
209 {
210 (*seaPtr)[0] = be.bist_err_occur;
211 }
212 break;
213 default:
214 printf("Unsupported shmoo type: %02u\n", (*scPtr).shmooType);
215 return SOC_E_FAIL;
216 }
217
218 return SOC_E_NONE;
219}
220
221static int
222_shmoo_and28_rd_en(int unit, int phy_ndx, and28_shmoo_container_t *scPtr)
223{
224 uint32 x;
225 uint32 y;
226 uint32 jump;
227 uint32 yCapMin;
228 uint32 yCapMax;
229 uint32 xStart;
230 uint32 data;
231 and28_shmoo_error_array_t sea;
232
233 yCapMin = 0;
234 yCapMax = (*scPtr).sizeY;
235 jump = (*scPtr).yJump;
236 xStart = 0;
237
238 (*scPtr).engageUIshift = 0;
239 (*scPtr).yCapMin = yCapMin;
240 (*scPtr).yCapMax = yCapMax;
241 (*scPtr).shmooType = SHMOO_AND28_RD_EN;
242
243 _initialize_bist(unit, phy_ndx, -1, scPtr);
244
245 for(y = yCapMin; y < yCapMax; y++)
246 {
247 data = 0;
248 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQ0P, FORCE, 1);
249 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQ0P, VDL_STEP, y << jump);
250 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P, data);
251 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N, data);
252 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P, data);
253 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N, data);
254 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P, data);
255 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N, data);
256 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P, data);
257 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N, data);
258 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P, data);
259 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N, data);
260 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P, data);
261 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N, data);
262 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P, data);
263 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N, data);
264 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P, data);
265 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N, data);
266 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP, data);
267 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN, data);
268 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
269 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP, data);
270 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN, data);
271 #endif
272 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P, data);
273 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N, data);
274 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P, data);
275 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N, data);
276 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P, data);
277 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N, data);
278 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P, data);
279 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N, data);
280 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P, data);
281 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N, data);
282 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P, data);
283 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N, data);
284 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P, data);
285 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N, data);
286 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P, data);
287 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N, data);
288 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP, data);
289 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN, data);
290 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
291 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP, data);
292 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN, data);
293 #endif
294
295 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
296 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
297 {
298 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P, data);
299 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N, data);
300 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P, data);
301 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N, data);
302 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P, data);
303 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N, data);
304 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P, data);
305 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N, data);
306 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P, data);
307 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N, data);
308 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P, data);
309 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N, data);
310 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P, data);
311 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N, data);
312 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P, data);
313 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N, data);
314 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP, data);
315 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN, data);
316 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
317 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP, data);
318 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN, data);
319 #endif
320 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P, data);
321 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N, data);
322 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P, data);
323 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N, data);
324 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P, data);
325 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N, data);
326 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P, data);
327 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N, data);
328 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P, data);
329 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N, data);
330 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P, data);
331 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N, data);
332 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P, data);
333 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N, data);
334 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P, data);
335 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N, data);
336 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP, data);
337 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN, data);
338 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
339 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP, data);
340 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN, data);
341 #endif
342 }
343 #endif
344
345 for(x = 0; x < (*scPtr).sizeX; x++)
346 {
347 data = 0;
348 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
349 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, x);
350
351 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, data);
352 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, data);
353 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1, data);
354 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1, data);
355
356 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
357 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
358 {
359 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, data);
360 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, data);
361 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1, data);
362 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1, data);
363 }
364 #endif
365
366 data = 0;
367 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, READ_FIFO_CLEAR, CLEAR, 1);
368 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_CLEAR, data);
369 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_CLEAR, data);
370
371 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
372 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
373 {
374 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_READ_FIFO_CLEAR, data);
375 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_READ_FIFO_CLEAR, data);
376 }
377 #endif
378
379 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
380
381 _run_bist(unit, phy_ndx, scPtr, &sea);
382
383 (*scPtr).result2D[x + xStart] = sea[0];
384 }
385
386 xStart += (*scPtr).sizeX;
387 }
388
389 return SOC_E_NONE;
390}
391
392static int
393_shmoo_and28_wr_extended(int unit, int phy_ndx, and28_shmoo_container_t *scPtr)
394{
395 uint32 x;
396 uint32 data;
397 and28_shmoo_error_array_t sea;
398
399 (*scPtr).engageUIshift = 0;
400 (*scPtr).sizeY = 1;
401 (*scPtr).yCapMin = 0;
402 (*scPtr).yCapMax = 1;
403 (*scPtr).shmooType = SHMOO_AND28_WR_EXTENDED;
404
405 _initialize_bist(unit, phy_ndx, -1, scPtr);
406
407 for(x = 0; x < (*scPtr).sizeX; x++)
408 {
409 data = 0;
410 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_WR_DQ0, FORCE, 1);
411 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_WR_DQ0, VDL_STEP, x);
412
413 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0, data);
414 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1, data);
415 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2, data);
416 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3, data);
417 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4, data);
418 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5, data);
419 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6, data);
420 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7, data);
421 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM, data);
422 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
423 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC, data);
424 #endif
425 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0, data);
426 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1, data);
427 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2, data);
428 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3, data);
429 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4, data);
430 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5, data);
431 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6, data);
432 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7, data);
433 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM, data);
434 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
435 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC, data);
436 #endif
437
438 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
439 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
440 {
441 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0, data);
442 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1, data);
443 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2, data);
444 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3, data);
445 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4, data);
446 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5, data);
447 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6, data);
448 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7, data);
449 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM, data);
450 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
451 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC, data);
452 #endif
453 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0, data);
454 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1, data);
455 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2, data);
456 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3, data);
457 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4, data);
458 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5, data);
459 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6, data);
460 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7, data);
461 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM, data);
462 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
463 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC, data);
464 #endif
465 }
466 #endif
467
468 data = 0;
469 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, READ_FIFO_CLEAR, CLEAR, 1);
470 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_CLEAR, data);
471 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_CLEAR, data);
472
473 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
474 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
475 {
476 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_READ_FIFO_CLEAR, data);
477 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_READ_FIFO_CLEAR, data);
478 }
479 #endif
480
481 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
482
483 _run_bist(unit, phy_ndx, scPtr, &sea);
484
485 (*scPtr).result2D[x] = sea[0];
486 }
487
488 return SOC_E_NONE;
489}
490
491static int
492_shmoo_and28_rd_extended(int unit, int phy_ndx, and28_shmoo_container_t *scPtr)
493{
494 uint32 x;
495 uint32 y;
496 uint32 yCapMin;
497 uint32 yCapMax;
498 uint32 xStart;
499 uint32 data, temp;
500 uint32 rd_dqs_pos0, rd_dqs_pos1, rd_en_pos0, rd_en_pos1, rd_dqs_delta0, rd_dqs_delta1;
501 uint32 rd_dq_fail_count0, rd_dq_fail_count1;
502 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
503 uint32 rd_dqs_pos2, rd_dqs_pos3, rd_en_pos2, rd_en_pos3, rd_dqs_delta2, rd_dqs_delta3;
504 uint32 rd_dq_fail_count2, rd_dq_fail_count3;
505 #endif
506 and28_shmoo_error_array_t sea;
507
508 yCapMin = 16;
509 yCapMax = 49;
510 xStart = 0;
511
512 (*scPtr).engageUIshift = 0;
513 (*scPtr).sizeY = SHMOO_AND28_MAX_VREF_RANGE;
514 (*scPtr).yCapMin = yCapMin;
515 (*scPtr).yCapMax = yCapMax;
516 (*scPtr).yJump = 0;
517 (*scPtr).shmooType = SHMOO_AND28_RD_EXTENDED;
518
519 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP, &data);
520 rd_dqs_pos0 = DDR_PHY_GET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, VDL_STEP);
521
522 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP, &data);
523 rd_dqs_pos1 = DDR_PHY_GET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_DQSP, VDL_STEP);
524
525 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
526 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
527 {
528 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP, &data);
529 rd_dqs_pos2 = DDR_PHY_GET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_DQSP, VDL_STEP);
530
531 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP, &data);
532 rd_dqs_pos3 = DDR_PHY_GET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_DQSP, VDL_STEP);
533 }
534 #endif
535
536 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, &data);
537 rd_en_pos0 = DDR_PHY_GET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP);
538
539 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, &data);
540 rd_en_pos1 = DDR_PHY_GET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP);
541
542 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
543 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
544 {
545 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, &data);
546 rd_en_pos2 = DDR_PHY_GET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP);
547
548 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, &data);
549 rd_en_pos3 = DDR_PHY_GET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP);
550 }
551 #endif
552
553 _initialize_bist(unit, phy_ndx, -1, scPtr);
554
555 x = 0;
556 data = 0;
557 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, FORCE, 1);
558 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, VDL_STEP, x);
559
560 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP, data);
561 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN, data);
562 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP, data);
563 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN, data);
564
565 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
566 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
567 {
568 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP, data);
569 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN, data);
570 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP, data);
571 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN, data);
572 }
573 #endif
574
575 rd_dqs_delta0 = x - rd_dqs_pos0;
576 rd_dqs_delta1 = x - rd_dqs_pos1;
577
578 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
579 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
580 {
581 rd_dqs_delta2 = x - rd_dqs_pos2;
582 rd_dqs_delta3 = x - rd_dqs_pos3;
583 }
584 #endif
585
586 temp = rd_en_pos0 + rd_dqs_delta0;
587 data = 0;
588 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
589 if(temp & 0x80000000)
590 {
591 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0);
592 }
593 else if(temp >= SHMOO_AND28_MAX_VDL_LENGTH)
594 {
595 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
596 }
597 else
598 {
599 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp);
600 }
601 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, data);
602 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1, data);
603
604 temp = rd_en_pos1 + rd_dqs_delta1;
605 data = 0;
606 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
607 if(temp & 0x80000000)
608 {
609 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0);
610 }
611 else if(temp >= SHMOO_AND28_MAX_VDL_LENGTH)
612 {
613 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
614 }
615 else
616 {
617 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp);
618 }
619 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, data);
620 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1, data);
621
622 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
623 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
624 {
625 temp = rd_en_pos2 + rd_dqs_delta2;
626 data = 0;
627 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
628 if(temp & 0x80000000)
629 {
630 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0);
631 }
632 else if(temp >= SHMOO_AND28_MAX_VDL_LENGTH)
633 {
634 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
635 }
636 else
637 {
638 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp);
639 }
640 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, data);
641 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1, data);
642
643 temp = rd_en_pos3 + rd_dqs_delta3;
644 data = 0;
645 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
646 if(temp & 0x80000000)
647 {
648 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0);
649 }
650 else if(temp >= SHMOO_AND28_MAX_VDL_LENGTH)
651 {
652 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
653 }
654 else
655 {
656 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp);
657 }
658 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, data);
659 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1, data);
660 }
661 #endif
662
663 rd_dq_fail_count0 = 0;
664 rd_dq_fail_count1 = 0;
665 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
666 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
667 {
668 rd_dq_fail_count2 = 0;
669 rd_dq_fail_count3 = 0;
670 }
671 #endif
672
673 for(x = 0; x < (*scPtr).sizeX; x++)
674 {
675 data = 0;
676 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQ0P, FORCE, 1);
677 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQ0P, VDL_STEP, x);
678 if(rd_dq_fail_count0 <= SHMOO_AND28_RD_DQ_FAIL_CAP)
679 {
680 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P, data);
681 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N, data);
682 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P, data);
683 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N, data);
684 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P, data);
685 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N, data);
686 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P, data);
687 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N, data);
688 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P, data);
689 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N, data);
690 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P, data);
691 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N, data);
692 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P, data);
693 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N, data);
694 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P, data);
695 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N, data);
696 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP, data);
697 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN, data);
698 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
699 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP, data);
700 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN, data);
701 #endif
702 }
703 if(rd_dq_fail_count1 <= SHMOO_AND28_RD_DQ_FAIL_CAP)
704 {
705 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P, data);
706 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N, data);
707 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P, data);
708 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N, data);
709 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P, data);
710 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N, data);
711 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P, data);
712 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N, data);
713 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P, data);
714 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N, data);
715 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P, data);
716 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N, data);
717 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P, data);
718 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N, data);
719 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P, data);
720 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N, data);
721 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP, data);
722 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN, data);
723 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
724 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP, data);
725 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN, data);
726 #endif
727 }
728
729 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
730 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
731 {
732 if(rd_dq_fail_count2 <= SHMOO_AND28_RD_DQ_FAIL_CAP)
733 {
734 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P, data);
735 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N, data);
736 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P, data);
737 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N, data);
738 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P, data);
739 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N, data);
740 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P, data);
741 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N, data);
742 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P, data);
743 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N, data);
744 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P, data);
745 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N, data);
746 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P, data);
747 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N, data);
748 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P, data);
749 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N, data);
750 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP, data);
751 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN, data);
752 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
753 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP, data);
754 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN, data);
755 #endif
756 }
757 if(rd_dq_fail_count3 <= SHMOO_AND28_RD_DQ_FAIL_CAP)
758 {
759 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P, data);
760 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N, data);
761 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P, data);
762 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N, data);
763 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P, data);
764 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N, data);
765 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P, data);
766 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N, data);
767 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P, data);
768 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N, data);
769 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P, data);
770 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N, data);
771 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P, data);
772 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N, data);
773 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P, data);
774 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N, data);
775 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP, data);
776 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN, data);
777 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
778 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP, data);
779 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN, data);
780 #endif
781 }
782 }
783 #endif
784
785 data = 0;
786 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, READ_FIFO_CLEAR, CLEAR, 1);
787 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_CLEAR, data);
788 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_CLEAR, data);
789
790 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
791 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
792 {
793 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_READ_FIFO_CLEAR, data);
794 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_READ_FIFO_CLEAR, data);
795 }
796 #endif
797
798 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
799
800 _run_bist(unit, phy_ndx, scPtr, &sea);
801
802 if((sea[0] & 0x000000FF) == 0x000000FF)
803 {
804 rd_dq_fail_count0++;
805 }
806 if((sea[0] & 0x0000FF00) == 0x0000FF00)
807 {
808 rd_dq_fail_count1++;
809 }
810
811 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
812 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
813 {
814 if((sea[0] & 0x00FF0000) == 0x00FF0000)
815 {
816 rd_dq_fail_count2++;
817 }
818 if((sea[0] & 0xFF000000) == 0xFF000000)
819 {
820 rd_dq_fail_count3++;
821 }
822 }
823 #endif
824
825 if((rd_dq_fail_count0 > SHMOO_AND28_RD_DQ_FAIL_CAP) && (rd_dq_fail_count1 > SHMOO_AND28_RD_DQ_FAIL_CAP))
826 {
827 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
828 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
829 {
830 if((rd_dq_fail_count2 > SHMOO_AND28_RD_DQ_FAIL_CAP) && (rd_dq_fail_count3 > SHMOO_AND28_RD_DQ_FAIL_CAP))
831 {
832 break;
833 }
834 }
835 else
836 {
837 break;
838 }
839 #else
840 break;
841 #endif
842 }
843 }
844
845 for(y = yCapMin; y < yCapMax; y++)
846 {
847 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL, &data);
848 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VREF_DAC_CONTROL, DAC0, y);
849 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VREF_DAC_CONTROL, DAC1, y);
850 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL, data);
851
852 for(x = 0; x < (*scPtr).sizeX; x++)
853 {
854 data = 0;
855 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, FORCE, 1);
856 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, VDL_STEP, x);
857
858 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP, data);
859 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN, data);
860 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP, data);
861 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN, data);
862
863 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
864 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
865 {
866 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP, data);
867 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN, data);
868 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP, data);
869 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN, data);
870 }
871 #endif
872
873 rd_dqs_delta0 = x - rd_dqs_pos0;
874 rd_dqs_delta1 = x - rd_dqs_pos1;
875
876 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
877 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
878 {
879 rd_dqs_delta2 = x - rd_dqs_pos2;
880 rd_dqs_delta3 = x - rd_dqs_pos3;
881 }
882 #endif
883
884 temp = rd_en_pos0 + rd_dqs_delta0;
885 data = 0;
886 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
887 if(temp & 0x80000000)
888 {
889 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0);
890 }
891 else if(temp >= SHMOO_AND28_MAX_VDL_LENGTH)
892 {
893 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
894 }
895 else
896 {
897 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp);
898 }
899 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, data);
900 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1, data);
901
902 temp = rd_en_pos1 + rd_dqs_delta1;
903 data = 0;
904 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
905 if(temp & 0x80000000)
906 {
907 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0);
908 }
909 else if(temp >= SHMOO_AND28_MAX_VDL_LENGTH)
910 {
911 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
912 }
913 else
914 {
915 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp);
916 }
917 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, data);
918 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1, data);
919
920 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
921 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
922 {
923 temp = rd_en_pos2 + rd_dqs_delta2;
924 data = 0;
925 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
926 if(temp & 0x80000000)
927 {
928 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0);
929 }
930 else if(temp >= SHMOO_AND28_MAX_VDL_LENGTH)
931 {
932 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
933 }
934 else
935 {
936 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp);
937 }
938 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, data);
939 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1, data);
940
941 temp = rd_en_pos3 + rd_dqs_delta3;
942 data = 0;
943 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
944 if(temp & 0x80000000)
945 {
946 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0);
947 }
948 else if(temp >= SHMOO_AND28_MAX_VDL_LENGTH)
949 {
950 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
951 }
952 else
953 {
954 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp);
955 }
956 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, data);
957 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1, data);
958 }
959 #endif
960
961 data = 0;
962 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, READ_FIFO_CLEAR, CLEAR, 1);
963 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_CLEAR, data);
964 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_CLEAR, data);
965
966 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
967 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
968 {
969 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_READ_FIFO_CLEAR, data);
970 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_READ_FIFO_CLEAR, data);
971 }
972 #endif
973
974 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
975
976 _run_bist(unit, phy_ndx, scPtr, &sea);
977
978 (*scPtr).result2D[x + xStart] = sea[0];
979 }
980
981 xStart += (*scPtr).sizeX;
982 }
983
984 return SOC_E_NONE;
985}
986
987static int
988_shmoo_and28_addr_extended(int unit, int phy_ndx, and28_shmoo_container_t *scPtr)
989{
990 uint32 x;
991 uint32 data;
992 and28_shmoo_error_array_t sea;
993
994 (*scPtr).engageUIshift = 0;
995 (*scPtr).sizeY = 1;
996 (*scPtr).yCapMin = 0;
997 (*scPtr).yCapMax = 1;
998 (*scPtr).shmooType = SHMOO_AND28_ADDR_EXTENDED;
999
1000 _initialize_bist(unit, phy_ndx, -1, scPtr);
1001
1002 for(x = 0; x < (*scPtr).sizeX; x++)
1003 {
1004 data = 0;
1005 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VDL_CONTROL_AD00, FORCE, 1);
1006 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VDL_CONTROL_AD00, VDL_STEP, x);
1007
1008 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00, data);
1009 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01, data);
1010 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02, data);
1011 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03, data);
1012 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04, data);
1013 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05, data);
1014 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06, data);
1015 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07, data);
1016 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08, data);
1017 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09, data);
1018
1019 data = 0;
1020 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, READ_FIFO_CLEAR, CLEAR, 1);
1021 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_CLEAR, data);
1022 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_CLEAR, data);
1023
1024 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
1025 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
1026 {
1027 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_READ_FIFO_CLEAR, data);
1028 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_READ_FIFO_CLEAR, data);
1029 }
1030 #endif
1031
1032 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
1033
1034 _run_bist(unit, phy_ndx, scPtr, &sea);
1035
1036 (*scPtr).result2D[x] = sea[0];
1037 }
1038
1039 return SOC_E_NONE;
1040}
1041
1042static int
1043_shmoo_and28_ctrl_extended(int unit, int phy_ndx, and28_shmoo_container_t *scPtr)
1044{
1045 uint32 x;
1046 uint32 data;
1047 and28_shmoo_error_array_t sea;
1048
1049 (*scPtr).engageUIshift = 0;
1050 (*scPtr).sizeY = 1;
1051 (*scPtr).yCapMin = 0;
1052 (*scPtr).yCapMax = 1;
1053 (*scPtr).shmooType = SHMOO_AND28_CTRL_EXTENDED;
1054
1055 _initialize_bist(unit, phy_ndx, -1, scPtr);
1056
1057 for(x = 0; x < (*scPtr).sizeX; x++)
1058 {
1059 data = 0;
1060 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VDL_CONTROL_AD00, FORCE, 1);
1061 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VDL_CONTROL_AD00, VDL_STEP, x);
1062
1063 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10, data);
1064 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11, data);
1065 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12, data);
1066 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13, data);
1067 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14, data);
1068 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15, data);
1069 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0, data);
1070 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1, data);
1071 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2, data);
1072 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0, data);
1073 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1, data);
1074 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2, data);
1075 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0, data);
1076 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1, data);
1077 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR, data);
1078 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N, data);
1079 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N, data);
1080 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE, data);
1081 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N, data);
1082 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT, data);
1083 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N, data);
1084
1085 data = 0;
1086 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, READ_FIFO_CLEAR, CLEAR, 1);
1087 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_CLEAR, data);
1088 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_CLEAR, data);
1089
1090 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
1091 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
1092 {
1093 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_READ_FIFO_CLEAR, data);
1094 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_READ_FIFO_CLEAR, data);
1095 }
1096 #endif
1097
1098 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
1099
1100 _run_bist(unit, phy_ndx, scPtr, &sea);
1101
1102 (*scPtr).result2D[x] = sea[0];
1103 }
1104
1105 return SOC_E_NONE;
1106}
1107
1108static int
1109_shmoo_and28_do(int unit, int phy_ndx, and28_shmoo_container_t *scPtr)
1110{
1111 switch ((*scPtr).shmooType) {
1112 case SHMOO_AND28_RD_EN:
1113 return _shmoo_and28_rd_en(unit, phy_ndx, scPtr);
1114 case SHMOO_AND28_RD_EXTENDED:
1115 return _shmoo_and28_rd_extended(unit, phy_ndx, scPtr);
1116 case SHMOO_AND28_WR_EXTENDED:
1117 return _shmoo_and28_wr_extended(unit, phy_ndx, scPtr);
1118 case SHMOO_AND28_ADDR_EXTENDED:
1119 return _shmoo_and28_addr_extended(unit, phy_ndx, scPtr);
1120 case SHMOO_AND28_CTRL_EXTENDED:
1121 if(!SHMOO_AND28_QUICK_SHMOO_CTRL_EXTENDED)
1122 {
1123 return _shmoo_and28_ctrl_extended(unit, phy_ndx, scPtr);
1124 }
1125 break;
1126 default:
1127 printf("Unsupported shmoo type: %02u\n", (*scPtr).shmooType);
1128 return SOC_E_FAIL;
1129 }
1130 return SOC_E_NONE;
1131}
1132
1133static int
1134_calib_2D(int unit, int phy_ndx, and28_shmoo_container_t *scPtr, uint32 calibMode, uint32 calibPos)
1135{
1136 uint32 x;
1137 uint32 y;
1138 uint32 xStart;
1139 uint32 sizeX;
1140 uint32 calibStart;
1141 uint32 yCapMin;
1142 uint32 yCapMax;
1143 uint32 i;
1144 uint32 iter;
1145 uint32 shiftAmount;
1146 uint32 dataMask;
1147 int32 passStart;
1148 int32 failStart;
1149 int32 passStartSeen;
1150 int32 failStartSeen;
1151 int32 passLength;
1152 int32 maxPassStart;
1153 int32 maxPassLength;
1154 int32 maxMidPointX;
1155 uint32 maxPassLengthArray[SHMOO_AND28_WORD];
1156
1157 xStart = 0;
1158 sizeX = (*scPtr).sizeX;
1159 calibStart = (*scPtr).calibStart;
1160 yCapMin = (*scPtr).yCapMin;
1161 yCapMax = (*scPtr).yCapMax;
1162
1163 switch(calibMode)
1164 {
1165 case SHMOO_AND28_BIT:
1166 iter = shmoo_dram_info_ptr->interface_bitwidth;
1167 shiftAmount = 0;
1168 dataMask = 0x1;
1169 break;
1170 case SHMOO_AND28_BYTE:
1171 iter = shmoo_dram_info_ptr->interface_bitwidth >> 3;
1172 shiftAmount = 3;
1173 dataMask = 0xFF;
1174 break;
1175 case SHMOO_AND28_HALFWORD:
1176 iter = shmoo_dram_info_ptr->interface_bitwidth >> 4;
1177 shiftAmount = 4;
1178 dataMask = 0xFFFF;
1179 break;
1180 case SHMOO_AND28_WORD:
1181 iter = 1;
1182 shiftAmount = 5;
1183 dataMask = 0xFFFFFFFF;
1184 break;
1185 default:
1186 printf("Unsupported 2D calibration mode: %02u\n", calibMode);
1187 return SOC_E_FAIL;
1188 }
1189
1190 for(i = 0; i < iter; i++)
1191 {
1192 (*scPtr).resultData[i] = 0;
1193 maxPassLengthArray[i] = 0;
1194 }
1195
1196 for(y = yCapMin; y < yCapMax; y++)
1197 {
1198 for(i = 0; i < iter; i++)
1199 {
1200 passStart = -1;
1201 failStart = -1;
1202 passLength = -1;
1203 passStartSeen = -1;
1204 failStartSeen = -1;
1205 maxPassStart = -2;
1206 maxPassLength = -2;
1207 maxMidPointX = -2;
1208 for(x = calibStart; x < sizeX; x++)
1209 {
1210 if(((*scPtr).result2D[xStart + x] >> (i << shiftAmount)) & dataMask)
1211 { /* FAIL */
1212 if(failStart < 0) {
1213 failStart = x;
1214 if(maxPassLength < passLength)
1215 {
1216 maxPassStart = passStart;
1217 maxPassLength = passLength;
1218 }
1219 passStart = -1;
1220 passLength = -1;
1221 if((failStartSeen < 0) && (maxPassLength > 0))
1222 {
1223 failStartSeen = x;
1224 }
1225 }
1226 }
1227 else
1228 { /* PASS */
1229 if(passStart < 0)
1230 {
1231 passStart = x;
1232 passLength = 1;
1233 failStart = -1;
1234 if((passStartSeen < 0) && (passLength < x))
1235 {
1236 passStartSeen = x;
1237 }
1238 }
1239 else
1240 {
1241 passLength++;
1242 }
1243
1244 if(x == sizeX - 1)
1245 {
1246 if(maxPassLength < passLength)
1247 {
1248 maxPassStart = passStart;
1249 maxPassLength = passLength;
1250 }
1251 }
1252 }
1253 }
1254
1255 switch (calibPos) {
1256 case SHMOO_AND28_CALIB_FAIL_START:
1257 case SHMOO_AND28_CALIB_RISING_EDGE:
1258 if(failStartSeen > 0)
1259 {
1260 maxMidPointX = failStartSeen;
1261 (*scPtr).resultData[i] = (y << 16) | (maxMidPointX & 0xFFFF);
1262 }
1263 break;
1264 case SHMOO_AND28_CALIB_PASS_START:
1265 case SHMOO_AND28_CALIB_FALLING_EDGE:
1266 if(passStartSeen > 0)
1267 {
1268 maxMidPointX = passStartSeen;
1269 (*scPtr).resultData[i] = (y << 16) | (maxMidPointX & 0xFFFF);
1270 }
1271 break;
1272 case SHMOO_AND28_CALIB_CENTER_PASS:
1273 if((maxPassLength > 0) && (maxPassLengthArray[i] < maxPassLength))
1274 {
1275 maxMidPointX = (maxPassStart + maxPassStart + maxPassLength) >> 1;
1276 (*scPtr).resultData[i] = (y << 16) | (maxMidPointX & 0xFFFF);
1277 maxPassLengthArray[i] = maxPassLength;
1278 }
1279 break;
1280 case SHMOO_AND28_CALIB_VDL_ZERO:
1281 maxMidPointX = 0;
1282 (*scPtr).resultData[i] = (y << 16) | (maxMidPointX & 0xFFFF);
1283 break;
1284 default:
1285 printf("Unsupported calibration position: %02u\n", calibPos);
1286 return SOC_E_FAIL;
1287 }
1288 }
1289 xStart += sizeX;
1290 }
1291
1292 (*scPtr).calibMode = calibMode;
1293 (*scPtr).calibPos = calibPos;
1294
1295 return SOC_E_NONE;
1296}
1297
1298static int
1299_shmoo_and28_calib_2D(int unit, int phy_ndx, and28_shmoo_container_t *scPtr)
1300{
1301 switch ((*scPtr).shmooType) {
1302 case SHMOO_AND28_RD_EN:
1303 return _calib_2D(unit, phy_ndx, scPtr, SHMOO_AND28_BYTE, SHMOO_AND28_CALIB_CENTER_PASS);
1304 case SHMOO_AND28_RD_EXTENDED:
1305 return _calib_2D(unit, phy_ndx, scPtr, SHMOO_AND28_BYTE, SHMOO_AND28_CALIB_CENTER_PASS);
1306 case SHMOO_AND28_WR_EXTENDED:
1307 return _calib_2D(unit, phy_ndx, scPtr, SHMOO_AND28_BYTE, SHMOO_AND28_CALIB_CENTER_PASS);
1308 case SHMOO_AND28_ADDR_EXTENDED:
1309 return _calib_2D(unit, phy_ndx, scPtr, SHMOO_AND28_WORD, SHMOO_AND28_CALIB_CENTER_PASS);
1310 case SHMOO_AND28_CTRL_EXTENDED:
1311 if(!SHMOO_AND28_QUICK_SHMOO_CTRL_EXTENDED)
1312 {
1313 return _calib_2D(unit, phy_ndx, scPtr, SHMOO_AND28_WORD, SHMOO_AND28_CALIB_CENTER_PASS);
1314 }
1315 break;
1316 default:
1317 printf("Unsupported shmoo type: %02u\n", (*scPtr).shmooType);
1318 return SOC_E_FAIL;
1319 }
1320 return SOC_E_NONE;
1321}
1322
1323static int
1324_shmoo_and28_set_new_step(int unit, int phy_ndx, and28_shmoo_container_t *scPtr)
1325{
1326 uint32 calibMode;
1327/* uint32 engageUIshift; */
1328 uint32 val, yVal;
1329 uint32 data, temp;
1330 uint32 rd_dqs_pos0, rd_dqs_pos1, rd_en_pos0, rd_en_pos1, rd_dqs_delta0, rd_dqs_delta1;
1331 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
1332 uint32 rd_dqs_pos2, rd_dqs_pos3, rd_en_pos2, rd_en_pos3, rd_dqs_delta2, rd_dqs_delta3;
1333 #endif
1334
1335 calibMode = (*scPtr).calibMode;
1336/* engageUIshift = (*scPtr).engageUIshift; */
1337
1338 switch ((*scPtr).shmooType) {
1339 case SHMOO_AND28_RD_EN:
1340 switch(calibMode)
1341 {
1342 case SHMOO_AND28_BIT:
1343 printf("Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n", (*scPtr).shmooType, calibMode);
1344 return SOC_E_FAIL;
1345 case SHMOO_AND28_BYTE:
1346 data = 0;
1347 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
1348 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, (*scPtr).resultData[0] & 0xFFFF);
1349
1350 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, data);
1351 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1, data);
1352
1353 data = 0;
1354 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
1355 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, (*scPtr).resultData[1] & 0xFFFF);
1356
1357 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, data);
1358 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1, data);
1359
1360 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
1361 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
1362 {
1363 data = 0;
1364 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
1365 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, (*scPtr).resultData[2] & 0xFFFF);
1366
1367 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, data);
1368 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1, data);
1369
1370 data = 0;
1371 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
1372 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, (*scPtr).resultData[3] & 0xFFFF);
1373
1374 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, data);
1375 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1, data);
1376 }
1377 #endif
1378
1379 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
1380 break;
1381 case SHMOO_AND28_HALFWORD:
1382 data = 0;
1383 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
1384 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, (*scPtr).resultData[0] & 0xFFFF);
1385
1386 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, data);
1387 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1, data);
1388 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, data);
1389 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1, data);
1390
1391 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
1392 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
1393 {
1394 data = 0;
1395 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
1396 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, (*scPtr).resultData[1] & 0xFFFF);
1397
1398 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, data);
1399 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1, data);
1400 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, data);
1401 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1, data);
1402 }
1403 #endif
1404
1405 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
1406 break;
1407 case SHMOO_AND28_WORD:
1408 data = 0;
1409 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
1410 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, (*scPtr).resultData[0] & 0xFFFF);
1411
1412 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, data);
1413 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1, data);
1414 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, data);
1415 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1, data);
1416
1417 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
1418 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
1419 {
1420 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, data);
1421 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1, data);
1422 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, data);
1423 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1, data);
1424 }
1425 #endif
1426
1427 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
1428 break;
1429 default:
1430 printf("Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n", (*scPtr).shmooType, calibMode);
1431 return SOC_E_FAIL;
1432 }
1433 break;
1434 case SHMOO_AND28_RD_EXTENDED:
1435 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP, &data);
1436 rd_dqs_pos0 = DDR_PHY_GET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, VDL_STEP);
1437
1438 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP, &data);
1439 rd_dqs_pos1 = DDR_PHY_GET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_DQSP, VDL_STEP);
1440
1441 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
1442 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
1443 {
1444 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP, &data);
1445 rd_dqs_pos2 = DDR_PHY_GET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_DQSP, VDL_STEP);
1446
1447 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP, &data);
1448 rd_dqs_pos3 = DDR_PHY_GET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_DQSP, VDL_STEP);
1449 }
1450 #endif
1451
1452 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, &data);
1453 rd_en_pos0 = DDR_PHY_GET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP);
1454
1455 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, &data);
1456 rd_en_pos1 = DDR_PHY_GET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP);
1457
1458 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
1459 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
1460 {
1461 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, &data);
1462 rd_en_pos2 = DDR_PHY_GET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP);
1463
1464 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, &data);
1465 rd_en_pos3 = DDR_PHY_GET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP);
1466 }
1467 #endif
1468
1469 switch(calibMode)
1470 {
1471 case SHMOO_AND28_BIT:
1472 printf("Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n", (*scPtr).shmooType, calibMode);
1473 return SOC_E_FAIL;
1474 case SHMOO_AND28_BYTE:
1475 val = (*scPtr).resultData[0] & 0xFFFF;
1476 rd_dqs_delta0 = val - rd_dqs_pos0;
1477 data = 0;
1478 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, FORCE, 1);
1479 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, VDL_STEP, val);
1480
1481 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP, data);
1482 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN, data);
1483
1484 temp = rd_en_pos0 + rd_dqs_delta0;
1485 data = 0;
1486 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
1487 if(temp & 0x80000000)
1488 {
1489 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0);
1490 }
1491 else if(temp >= SHMOO_AND28_MAX_VDL_LENGTH)
1492 {
1493 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
1494 }
1495 else
1496 {
1497 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp);
1498 }
1499 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, data);
1500 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1, data);
1501
1502 val = (*scPtr).resultData[1] & 0xFFFF;
1503 rd_dqs_delta1 = val - rd_dqs_pos1;
1504 data = 0;
1505 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_DQSP, FORCE, 1);
1506 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_DQSP, VDL_STEP, val);
1507
1508 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP, data);
1509 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN, data);
1510
1511 temp = rd_en_pos1 + rd_dqs_delta1;
1512 data = 0;
1513 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
1514 if(temp & 0x80000000)
1515 {
1516 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0);
1517 }
1518 else if(temp >= SHMOO_AND28_MAX_VDL_LENGTH)
1519 {
1520 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
1521 }
1522 else
1523 {
1524 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp);
1525 }
1526 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, data);
1527 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1, data);
1528
1529 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
1530 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
1531 {
1532 val = (*scPtr).resultData[2] & 0xFFFF;
1533 rd_dqs_delta2 = val - rd_dqs_pos2;
1534 data = 0;
1535 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_DQSP, FORCE, 1);
1536 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_DQSP, VDL_STEP, val);
1537
1538 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP, data);
1539 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN, data);
1540
1541 temp = rd_en_pos2 + rd_dqs_delta2;
1542 data = 0;
1543 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
1544 if(temp & 0x80000000)
1545 {
1546 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0);
1547 }
1548 else if(temp >= SHMOO_AND28_MAX_VDL_LENGTH)
1549 {
1550 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
1551 }
1552 else
1553 {
1554 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp);
1555 }
1556 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, data);
1557 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1, data);
1558
1559 val = (*scPtr).resultData[3] & 0xFFFF;
1560 rd_dqs_delta3 = val - rd_dqs_pos3;
1561 data = 0;
1562 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_DQSP, FORCE, 1);
1563 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_DQSP, VDL_STEP, val);
1564
1565 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP, data);
1566 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN, data);
1567
1568 temp = rd_en_pos3 + rd_dqs_delta3;
1569 data = 0;
1570 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
1571 if(temp & 0x80000000)
1572 {
1573 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0);
1574 }
1575 else if(temp >= SHMOO_AND28_MAX_VDL_LENGTH)
1576 {
1577 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
1578 }
1579 else
1580 {
1581 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp);
1582 }
1583 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, data);
1584 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1, data);
1585 }
1586 #endif
1587
1588 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
1589 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
1590 {
1591 yVal = ((((*scPtr).resultData[0] >> 16) & 0xFFFF) + (((*scPtr).resultData[1] >> 16) & 0xFFFF)
1592 + (((*scPtr).resultData[2] >> 16) & 0xFFFF) + (((*scPtr).resultData[3] >> 16) & 0xFFFF)) >> 2;
1593 }
1594 else
1595 {
1596 yVal = ((((*scPtr).resultData[0] >> 16) & 0xFFFF) + (((*scPtr).resultData[1] >> 16) & 0xFFFF)) >> 1;
1597 }
1598 #else
1599 yVal = ((((*scPtr).resultData[0] >> 16) & 0xFFFF) + (((*scPtr).resultData[1] >> 16) & 0xFFFF)) >> 1;
1600 #endif
1601 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL, &data);
1602 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VREF_DAC_CONTROL, DAC0, yVal);
1603 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VREF_DAC_CONTROL, DAC1, yVal);
1604 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL, data);
1605
1606 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
1607 break;
1608 case SHMOO_AND28_HALFWORD:
1609 val = (*scPtr).resultData[0] & 0xFFFF;
1610 rd_dqs_delta0 = val - rd_dqs_pos0;
1611 rd_dqs_delta1 = val - rd_dqs_pos1;
1612 data = 0;
1613 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, FORCE, 1);
1614 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, VDL_STEP, val);
1615
1616 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP, data);
1617 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN, data);
1618 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP, data);
1619 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN, data);
1620
1621 temp = rd_en_pos0 + rd_dqs_delta0;
1622 data = 0;
1623 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
1624 if(temp & 0x80000000)
1625 {
1626 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0);
1627 }
1628 else if(temp >= SHMOO_AND28_MAX_VDL_LENGTH)
1629 {
1630 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
1631 }
1632 else
1633 {
1634 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp);
1635 }
1636 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, data);
1637 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1, data);
1638
1639 temp = rd_en_pos1 + rd_dqs_delta1;
1640 data = 0;
1641 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
1642 if(temp & 0x80000000)
1643 {
1644 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0);
1645 }
1646 else if(temp >= SHMOO_AND28_MAX_VDL_LENGTH)
1647 {
1648 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
1649 }
1650 else
1651 {
1652 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp);
1653 }
1654 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, data);
1655 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1, data);
1656
1657 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
1658 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
1659 {
1660 val = (*scPtr).resultData[1] & 0xFFFF;
1661 rd_dqs_delta2 = val - rd_dqs_pos2;
1662 rd_dqs_delta3 = val - rd_dqs_pos3;
1663 data = 0;
1664 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_DQSP, FORCE, 1);
1665 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_DQSP, VDL_STEP, val);
1666
1667 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP, data);
1668 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN, data);
1669 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP, data);
1670 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN, data);
1671
1672 temp = rd_en_pos2 + rd_dqs_delta2;
1673 data = 0;
1674 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
1675 if(temp & 0x80000000)
1676 {
1677 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0);
1678 }
1679 else if(temp >= SHMOO_AND28_MAX_VDL_LENGTH)
1680 {
1681 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
1682 }
1683 else
1684 {
1685 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp);
1686 }
1687 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, data);
1688 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1, data);
1689
1690 temp = rd_en_pos3 + rd_dqs_delta3;
1691 data = 0;
1692 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
1693 if(temp & 0x80000000)
1694 {
1695 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0);
1696 }
1697 else if(temp >= SHMOO_AND28_MAX_VDL_LENGTH)
1698 {
1699 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
1700 }
1701 else
1702 {
1703 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp);
1704 }
1705 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, data);
1706 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1, data);
1707 }
1708 #endif
1709
1710 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
1711 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
1712 {
1713 yVal = ((((*scPtr).resultData[0] >> 16) & 0xFFFF) + (((*scPtr).resultData[1] >> 16) & 0xFFFF)) >> 1;
1714 }
1715 else
1716 {
1717 yVal = ((*scPtr).resultData[0] >> 16) & 0xFFFF;
1718 }
1719 #else
1720 yVal = ((*scPtr).resultData[0] >> 16) & 0xFFFF;
1721 #endif
1722 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL, &data);
1723 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VREF_DAC_CONTROL, DAC0, yVal);
1724 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VREF_DAC_CONTROL, DAC1, yVal);
1725 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL, data);
1726
1727 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
1728 break;
1729 case SHMOO_AND28_WORD:
1730 val = (*scPtr).resultData[0] & 0xFFFF;
1731 rd_dqs_delta0 = val - rd_dqs_pos0;
1732 rd_dqs_delta1 = val - rd_dqs_pos1;
1733 data = 0;
1734 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, FORCE, 1);
1735 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, VDL_STEP, val);
1736
1737 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP, data);
1738 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN, data);
1739 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP, data);
1740 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN, data);
1741
1742 temp = rd_en_pos0 + rd_dqs_delta0;
1743 data = 0;
1744 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
1745 if(temp & 0x80000000)
1746 {
1747 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0);
1748 }
1749 else if(temp >= SHMOO_AND28_MAX_VDL_LENGTH)
1750 {
1751 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
1752 }
1753 else
1754 {
1755 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp);
1756 }
1757 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, data);
1758 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1, data);
1759
1760 temp = rd_en_pos1 + rd_dqs_delta1;
1761 data = 0;
1762 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
1763 if(temp & 0x80000000)
1764 {
1765 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0);
1766 }
1767 else if(temp >= SHMOO_AND28_MAX_VDL_LENGTH)
1768 {
1769 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
1770 }
1771 else
1772 {
1773 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp);
1774 }
1775 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, data);
1776 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1, data);
1777
1778 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
1779 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
1780 {
1781 rd_dqs_delta2 = val - rd_dqs_pos2;
1782 rd_dqs_delta3 = val - rd_dqs_pos3;
1783
1784 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP, data);
1785 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN, data);
1786 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP, data);
1787 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN, data);
1788
1789 temp = rd_en_pos2 + rd_dqs_delta2;
1790 data = 0;
1791 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
1792 if(temp & 0x80000000)
1793 {
1794 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0);
1795 }
1796 else if(temp >= SHMOO_AND28_MAX_VDL_LENGTH)
1797 {
1798 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
1799 }
1800 else
1801 {
1802 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp);
1803 }
1804 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, data);
1805 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1, data);
1806
1807 temp = rd_en_pos3 + rd_dqs_delta3;
1808 data = 0;
1809 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
1810 if(temp & 0x80000000)
1811 {
1812 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0);
1813 }
1814 else if(temp >= SHMOO_AND28_MAX_VDL_LENGTH)
1815 {
1816 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
1817 }
1818 else
1819 {
1820 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp);
1821 }
1822 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, data);
1823 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1, data);
1824 }
1825 #endif
1826
1827 yVal = ((*scPtr).resultData[0] >> 16) & 0xFFFF;
1828 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL, &data);
1829 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VREF_DAC_CONTROL, DAC0, yVal);
1830 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VREF_DAC_CONTROL, DAC1, yVal);
1831 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL, data);
1832
1833 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
1834 break;
1835 default:
1836 printf("Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n", (*scPtr).shmooType, calibMode);
1837 return SOC_E_FAIL;
1838 }
1839 break;
1840 case SHMOO_AND28_WR_EXTENDED:
1841 switch(calibMode)
1842 {
1843 case SHMOO_AND28_BIT:
1844 printf("Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n", (*scPtr).shmooType, calibMode);
1845 return SOC_E_FAIL;
1846 case SHMOO_AND28_BYTE:
1847 data = 0;
1848 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_WR_DQ0, FORCE, 1);
1849 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_WR_DQ0, VDL_STEP, (*scPtr).resultData[0] & 0xFFFF);
1850
1851 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0, data);
1852 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1, data);
1853 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2, data);
1854 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3, data);
1855 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4, data);
1856 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5, data);
1857 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6, data);
1858 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7, data);
1859 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM, data);
1860 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
1861 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC, data);
1862 #endif
1863
1864 data = 0;
1865 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_WR_DQ0, FORCE, 1);
1866 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_WR_DQ0, VDL_STEP, (*scPtr).resultData[1] & 0xFFFF);
1867
1868 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0, data);
1869 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1, data);
1870 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2, data);
1871 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3, data);
1872 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4, data);
1873 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5, data);
1874 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6, data);
1875 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7, data);
1876 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM, data);
1877 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
1878 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC, data);
1879 #endif
1880
1881 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
1882 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
1883 {
1884 data = 0;
1885 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_WR_DQ0, FORCE, 1);
1886 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_WR_DQ0, VDL_STEP, (*scPtr).resultData[2] & 0xFFFF);
1887
1888 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0, data);
1889 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1, data);
1890 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2, data);
1891 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3, data);
1892 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4, data);
1893 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5, data);
1894 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6, data);
1895 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7, data);
1896 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM, data);
1897 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
1898 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC, data);
1899 #endif
1900
1901 data = 0;
1902 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_WR_DQ0, FORCE, 1);
1903 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_WR_DQ0, VDL_STEP, (*scPtr).resultData[3] & 0xFFFF);
1904
1905 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0, data);
1906 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1, data);
1907 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2, data);
1908 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3, data);
1909 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4, data);
1910 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5, data);
1911 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6, data);
1912 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7, data);
1913 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM, data);
1914 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
1915 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC, data);
1916 #endif
1917 }
1918 #endif
1919
1920 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
1921 break;
1922 case SHMOO_AND28_HALFWORD:
1923 data = 0;
1924 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_WR_DQ0, FORCE, 1);
1925 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_WR_DQ0, VDL_STEP, (*scPtr).resultData[0] & 0xFFFF);
1926
1927 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0, data);
1928 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1, data);
1929 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2, data);
1930 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3, data);
1931 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4, data);
1932 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5, data);
1933 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6, data);
1934 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7, data);
1935 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM, data);
1936 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
1937 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC, data);
1938 #endif
1939 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0, data);
1940 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1, data);
1941 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2, data);
1942 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3, data);
1943 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4, data);
1944 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5, data);
1945 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6, data);
1946 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7, data);
1947 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM, data);
1948 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
1949 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC, data);
1950 #endif
1951
1952 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
1953 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
1954 {
1955 data = 0;
1956 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_WR_DQ0, FORCE, 1);
1957 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_WR_DQ0, VDL_STEP, (*scPtr).resultData[1] & 0xFFFF);
1958
1959 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0, data);
1960 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1, data);
1961 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2, data);
1962 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3, data);
1963 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4, data);
1964 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5, data);
1965 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6, data);
1966 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7, data);
1967 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM, data);
1968 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
1969 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC, data);
1970 #endif
1971 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0, data);
1972 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1, data);
1973 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2, data);
1974 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3, data);
1975 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4, data);
1976 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5, data);
1977 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6, data);
1978 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7, data);
1979 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM, data);
1980 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
1981 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC, data);
1982 #endif
1983 }
1984 #endif
1985
1986 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
1987 break;
1988 case SHMOO_AND28_WORD:
1989 data = 0;
1990 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_WR_DQ0, FORCE, 1);
1991 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_WR_DQ0, VDL_STEP, (*scPtr).resultData[0] & 0xFFFF);
1992
1993 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0, data);
1994 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1, data);
1995 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2, data);
1996 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3, data);
1997 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4, data);
1998 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5, data);
1999 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6, data);
2000 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7, data);
2001 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM, data);
2002 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
2003 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC, data);
2004 #endif
2005 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0, data);
2006 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1, data);
2007 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2, data);
2008 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3, data);
2009 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4, data);
2010 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5, data);
2011 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6, data);
2012 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7, data);
2013 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM, data);
2014 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
2015 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC, data);
2016 #endif
2017
2018 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
2019 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
2020 {
2021 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0, data);
2022 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1, data);
2023 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2, data);
2024 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3, data);
2025 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4, data);
2026 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5, data);
2027 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6, data);
2028 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7, data);
2029 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM, data);
2030 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
2031 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC, data);
2032 #endif
2033 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0, data);
2034 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1, data);
2035 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2, data);
2036 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3, data);
2037 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4, data);
2038 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5, data);
2039 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6, data);
2040 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7, data);
2041 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM, data);
2042 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
2043 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC, data);
2044 #endif
2045 }
2046 #endif
2047
2048 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
2049 break;
2050 default:
2051 printf("Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n", (*scPtr).shmooType, calibMode);
2052 return SOC_E_FAIL;
2053 }
2054 break;
2055 case SHMOO_AND28_ADDR_EXTENDED:
2056 switch(calibMode)
2057 {
2058 case SHMOO_AND28_BIT:
2059 printf("Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n", (*scPtr).shmooType, calibMode);
2060 return SOC_E_FAIL;
2061 case SHMOO_AND28_BYTE:
2062 printf("Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n", (*scPtr).shmooType, calibMode);
2063 return SOC_E_FAIL;
2064 case SHMOO_AND28_HALFWORD:
2065 printf("Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n", (*scPtr).shmooType, calibMode);
2066 return SOC_E_FAIL;
2067 case SHMOO_AND28_WORD:
2068 data = 0;
2069 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VDL_CONTROL_AD00, FORCE, 1);
2070 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VDL_CONTROL_AD00, VDL_STEP, (*scPtr).resultData[0] & 0xFFFF);
2071
2072 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00, data);
2073 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01, data);
2074 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02, data);
2075 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03, data);
2076 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04, data);
2077 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05, data);
2078 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06, data);
2079 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07, data);
2080 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08, data);
2081 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09, data);
2082 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
2083 break;
2084 default:
2085 printf("Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n", (*scPtr).shmooType, calibMode);
2086 return SOC_E_FAIL;
2087 }
2088 break;
2089 case SHMOO_AND28_CTRL_EXTENDED:
2090 if(SHMOO_AND28_QUICK_SHMOO_CTRL_EXTENDED)
2091 {
2092 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00, &data);
2093 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VDL_CONTROL_AD00, FORCE, 1);
2094
2095 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10, data);
2096 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11, data);
2097 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12, data);
2098 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13, data);
2099 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14, data);
2100 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15, data);
2101 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0, data);
2102 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1, data);
2103 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2, data);
2104 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0, data);
2105 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1, data);
2106 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2, data);
2107 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0, data);
2108 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1, data);
2109 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR, data);
2110 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N, data);
2111 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N, data);
2112 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE, data);
2113 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N, data);
2114 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT, data);
2115 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N, data);
2116 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
2117 }
2118 else
2119 {
2120 switch(calibMode)
2121 {
2122 case SHMOO_AND28_BIT:
2123 printf("Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n", (*scPtr).shmooType, calibMode);
2124 return SOC_E_FAIL;
2125 case SHMOO_AND28_BYTE:
2126 printf("Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n", (*scPtr).shmooType, calibMode);
2127 return SOC_E_FAIL;
2128 case SHMOO_AND28_HALFWORD:
2129 printf("Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n", (*scPtr).shmooType, calibMode);
2130 return SOC_E_FAIL;
2131 case SHMOO_AND28_WORD:
2132 data = 0;
2133 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VDL_CONTROL_AD00, FORCE, 1);
2134 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VDL_CONTROL_AD00, VDL_STEP, (*scPtr).resultData[0] & 0xFFFF);
2135
2136 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10, data);
2137 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11, data);
2138 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12, data);
2139 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13, data);
2140 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14, data);
2141 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15, data);
2142 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0, data);
2143 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1, data);
2144 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2, data);
2145 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0, data);
2146 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1, data);
2147 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2, data);
2148 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0, data);
2149 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1, data);
2150 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR, data);
2151 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N, data);
2152 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N, data);
2153 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE, data);
2154 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N, data);
2155 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT, data);
2156 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N, data);
2157 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
2158 break;
2159 default:
2160 printf("Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n", (*scPtr).shmooType, calibMode);
2161 return SOC_E_FAIL;
2162 }
2163 }
2164 break;
2165 default:
2166 printf("Unsupported shmoo type: %02u\n", (*scPtr).shmooType);
2167 return SOC_E_FAIL;
2168 }
2169
2170 data = 0;
2171 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, READ_FIFO_CLEAR, CLEAR, 1);
2172 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_CLEAR, data);
2173 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_CLEAR, data);
2174
2175 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
2176 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
2177 {
2178 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_READ_FIFO_CLEAR, data);
2179 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_READ_FIFO_CLEAR, data);
2180 }
2181 #endif
2182
2183 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
2184
2185 return SOC_E_NONE;
2186}
2187
2188#ifdef PLOT_SUPPORT
2189static int
2190_plot(int unit, int phy_ndx, and28_shmoo_container_t *scPtr, uint32 plotMode)
2191{
2192 uint32 x;
2193 uint32 y;
2194 uint32 xStart;
2195 uint32 sizeX;
2196 uint32 sizeY;
2197 uint32 yCapMin;
2198 uint32 yCapMax;
2199 uint32 yJump;
2200 uint32 i;
2201 uint32 ui;
2202 uint32 iter;
2203 uint32 shiftAmount;
2204 uint32 dataMask;
2205 uint32 calibMode;
2206 uint32 calibPos;
2207 uint32 calibStart;
2208 uint32 engageUIshift;
2209 uint32 step1000;
2210 uint32 size1000UI;
2211 uint32 calibShiftAmount;
2212 uint32 maxMidPointX;
2213 uint32 maxMidPointY;
2214 char str0[SHMOO_AND28_STRING_LENGTH];
2215 char str1[SHMOO_AND28_STRING_LENGTH];
2216 char str2[SHMOO_AND28_STRING_LENGTH];
2217 char pass_low[2];
2218 char fail_high[2];
2219 char outOfSearch[2];
2220
2221 outOfSearch[0] = ' ';
2222 outOfSearch[1] = 0;
2223
2224 sizeX = (*scPtr).sizeX;
2225 sizeY = (*scPtr).sizeY;
2226 yCapMin = (*scPtr).yCapMin;
2227 yCapMax = (*scPtr).yCapMax;
2228 yJump = (*scPtr).yJump;
2229 calibMode = (*scPtr).calibMode;
2230 calibPos = (*scPtr).calibPos;
2231 calibStart = (*scPtr).calibStart;
2232 engageUIshift = (*scPtr).engageUIshift;
2233 step1000 = (*scPtr).step1000;
2234 size1000UI = (*scPtr).size1000UI;
2235
2236 switch (calibPos) {
2237 case SHMOO_AND28_CALIB_RISING_EDGE:
2238 case SHMOO_AND28_CALIB_FALLING_EDGE:
2239 pass_low[0] = '_';
2240 pass_low[1] = 0;
2241 fail_high[0] = '|';
2242 fail_high[1] = 0;
2243 break;
2244 case SHMOO_AND28_CALIB_CENTER_PASS:
2245 case SHMOO_AND28_CALIB_PASS_START:
2246 case SHMOO_AND28_CALIB_FAIL_START:
2247 case SHMOO_AND28_CALIB_VDL_ZERO:
2248 pass_low[0] = '+';
2249 pass_low[1] = 0;
2250 fail_high[0] = '-';
2251 fail_high[1] = 0;
2252 break;
2253 default:
2254 printf("Unsupported calibration position: %02u\n", calibPos);
2255 return SOC_E_FAIL;
2256 }
2257
2258 printf("\n\n");
2259
2260 switch(plotMode)
2261 {
2262 case SHMOO_AND28_BIT:
2263 iter = shmoo_dram_info_ptr->interface_bitwidth;
2264 shiftAmount = 0;
2265 dataMask = 0x1;
2266 switch(calibMode)
2267 {
2268 case SHMOO_AND28_BIT:
2269 calibShiftAmount = 0;
2270 break;
2271 case SHMOO_AND28_BYTE:
2272 calibShiftAmount = 3;
2273 break;
2274 case SHMOO_AND28_HALFWORD:
2275 calibShiftAmount = 4;
2276 break;
2277 case SHMOO_AND28_WORD:
2278 calibShiftAmount = 5;
2279 break;
2280 default:
2281 printf("Unsupported calibration mode during plot: %02u\n", calibMode);
2282 return SOC_E_FAIL;
2283 }
2284 break;
2285 case SHMOO_AND28_BYTE:
2286 iter = shmoo_dram_info_ptr->interface_bitwidth >> 3;
2287 shiftAmount = 3;
2288 dataMask = 0xFF;
2289 switch(calibMode)
2290 {
2291 case SHMOO_AND28_BIT:
2292 printf("WARNING: Plot mode coerced from byte mode to bit mode\n");
2293 iter = shmoo_dram_info_ptr->interface_bitwidth;
2294 shiftAmount = 0;
2295 dataMask = 0x1;
2296 calibShiftAmount = 0;
2297 break;
2298 case SHMOO_AND28_BYTE:
2299 calibShiftAmount = 0;
2300 break;
2301 case SHMOO_AND28_HALFWORD:
2302 calibShiftAmount = 1;
2303 break;
2304 case SHMOO_AND28_WORD:
2305 calibShiftAmount = 2;
2306 break;
2307 default:
2308 printf("Unsupported calibration mode during plot: %02u\n", calibMode);
2309 return SOC_E_FAIL;
2310 }
2311 break;
2312 case SHMOO_AND28_HALFWORD:
2313 iter = shmoo_dram_info_ptr->interface_bitwidth >> 4;
2314 shiftAmount = 4;
2315 dataMask = 0xFFFF;
2316 switch(calibMode)
2317 {
2318 case SHMOO_AND28_BIT:
2319 printf("WARNING: Plot mode coerced from halfword mode to bit mode\n");
2320 iter = 32;
2321 shiftAmount = 0;
2322 dataMask = 0x1;
2323 calibShiftAmount = 0;
2324 break;
2325 case SHMOO_AND28_BYTE:
2326 printf("WARNING: Plot mode coerced from halfword mode to byte mode\n");
2327 iter = 4;
2328 shiftAmount = 3;
2329 dataMask = 0xFF;
2330 calibShiftAmount = 0;
2331 break;
2332 case SHMOO_AND28_HALFWORD:
2333 calibShiftAmount = 0;
2334 break;
2335 case SHMOO_AND28_WORD:
2336 calibShiftAmount = 1;
2337 break;
2338 default:
2339 printf("Unsupported calibration mode during plot: %02u\n", calibMode);
2340 return SOC_E_FAIL;
2341 }
2342 break;
2343 case SHMOO_AND28_WORD:
2344 iter = 1;
2345 shiftAmount = 5;
2346 dataMask = 0xFFFFFFFF;
2347 switch(calibMode)
2348 {
2349 case SHMOO_AND28_BIT:
2350 printf("WARNING: Plot mode coerced from word mode to bit mode\n");
2351 iter = 32;
2352 shiftAmount = 0;
2353 dataMask = 0x1;
2354 calibShiftAmount = 0;
2355 break;
2356 case SHMOO_AND28_BYTE:
2357 printf("WARNING: Plot mode coerced from word mode to byte mode\n");
2358 iter = 4;
2359 shiftAmount = 3;
2360 dataMask = 0xFF;
2361 calibShiftAmount = 0;
2362 break;
2363 case SHMOO_AND28_HALFWORD:
2364 printf("WARNING: Plot mode coerced from word mode to halfword mode\n");
2365 iter = 2;
2366 shiftAmount = 4;
2367 dataMask = 0xFFFF;
2368 calibShiftAmount = 0;
2369 break;
2370 case SHMOO_AND28_WORD:
2371 calibShiftAmount = 0;
2372 break;
2373 default:
2374 printf("Unsupported calibration mode during plot: %02u\n", calibMode);
2375 return SOC_E_FAIL;
2376 }
2377 break;
2378 default:
2379 printf("Unsupported plot mode: %02u\n", plotMode);
2380 return SOC_E_FAIL;
2381 }
2382/*
2383 if(engageUIshift)
2384 { */
2385 ui = 0;
2386
2387 for(x = 0; x < sizeX; x++)
2388 {
2389 if((ui < SHMOO_AND28_MAX_VISIBLE_UI_COUNT) && (x > (*scPtr).endUI[ui]))
2390 {
2391 str0[x] = ' ';
2392 str1[x] = ' ';
2393 str2[x] = ' ';
2394 ui++;
2395 }
2396 else
2397 {
2398 str0[x] = '0' + (x / 100);
2399 str1[x] = '0' + ((x % 100) / 10);
2400 str2[x] = '0' + (x % 10);
2401 }
2402 }
2403/* }
2404 else
2405 {
2406 for(x = 0; x < sizeX; x++)
2407 {
2408 str0[x] = '0' + (x / 100);
2409 str1[x] = '0' + ((x % 100) / 10);
2410 str2[x] = '0' + (x % 10);
2411 }
2412 } */
2413
2414 str0[x] = 0;
2415 str1[x] = 0;
2416 str2[x] = 0;
2417
2418 for(i = 0; i < iter; i++)
2419 {
2420 xStart = 0;
2421 maxMidPointX = (*scPtr).resultData[i >> calibShiftAmount] & 0xFFFF;
2422 maxMidPointY = ((*scPtr).resultData[i >> calibShiftAmount] >> 16) & 0xFFFF;
2423
2424 if((sizeY > 1) || (i == 0))
2425 {
2426 printf("***** Interface.......: %3d\n", phy_ndx);
2427 printf(" **** VDL step size...: %3u.%03u ps\n", (step1000 / 1000), (step1000 % 1000));
2428 printf(" **** UI size.........: %3u.%03u steps\n", (size1000UI / 1000), (size1000UI % 1000));
2429
2430 switch((*scPtr).shmooType)
2431 {
2432 case SHMOO_AND28_RD_EN:
2433 printf(" **** Shmoo type......: RD_EN\n");
2434 break;
2435 case SHMOO_AND28_RD_EXTENDED:
2436 printf(" **** Shmoo type......: RD_EXTENDED\n");
2437 break;
2438 case SHMOO_AND28_WR_EXTENDED:
2439 printf(" **** Shmoo type......: WR_EXTENDED\n");
2440 break;
2441 case SHMOO_AND28_ADDR_EXTENDED:
2442 printf(" **** Shmoo type......: ADDR_EXTENDED\n");
2443 break;
2444 case SHMOO_AND28_CTRL_EXTENDED:
2445 printf(" **** Shmoo type......: CTRL_EXTENDED\n");
2446 printf(" *** Quick Shmoo.....: Off\n");
2447 break;
2448 default:
2449 printf("Unsupported shmoo type: %02u\n", (*scPtr).shmooType);
2450 return SOC_E_FAIL;
2451 }
2452
2453 if(engageUIshift)
2454 {
2455 printf(" *** UI shift........: On\n");
2456 }
2457 else
2458 {
2459 printf(" *** UI shift........: Off or N/A\n");
2460 }
2461 }
2462
2463 if(sizeY > 1)
2464 {
2465 switch(calibMode)
2466 {
2467 case SHMOO_AND28_BIT:
2468 printf(" *** Calib mode......: 2D Bit-wise\n");
2469 break;
2470 case SHMOO_AND28_BYTE:
2471 printf(" *** Calib mode......: 2D Byte-wise\n");
2472 break;
2473 case SHMOO_AND28_HALFWORD:
2474 printf(" *** Calib mode......: 2D Halfword-wise\n");
2475 break;
2476 case SHMOO_AND28_WORD:
2477 printf(" *** Calib mode......: 2D Word-wise\n");
2478 break;
2479 default:
2480 printf("Unsupported calibration mode during plot: %02u\n", calibMode);
2481 return SOC_E_FAIL;
2482 }
2483
2484 switch(plotMode)
2485 {
2486 case SHMOO_AND28_BIT:
2487 printf(" *** Plot mode.......: 2D Bit-wise\n");
2488 printf(" ** Bit.............: %03u\n", i);
2489 break;
2490 case SHMOO_AND28_BYTE:
2491 printf(" *** Plot mode.......: 2D Byte-wise\n");
2492 printf(" ** Byte............: %03u\n", i);
2493 break;
2494 case SHMOO_AND28_HALFWORD:
2495 printf(" *** Plot mode.......: 2D Halfword-wise\n");
2496 printf(" ** Halfword........: %03u\n", i);
2497 break;
2498 case SHMOO_AND28_WORD:
2499 printf(" *** Plot mode.......: 2D Word-wise\n");
2500 printf(" ** Word............: %03u\n", i);
2501 break;
2502 default:
2503 printf("Unsupported plot mode: %02u\n", plotMode);
2504 return SOC_E_FAIL;
2505 }
2506
2507 printf(" * Center X........: %03u\n", maxMidPointX);
2508 printf(" * Center Y........: %03u\n", maxMidPointY);
2509 printf(" %s\n", str0);
2510 printf(" %s\n", str1);
2511 printf(" %s\n", str2);
2512
2513 for(y = yCapMin; y < yCapMax; y++)
2514 {
2515 printf(" %03u ", y << yJump);
2516
2517 for(x = 0; x < calibStart; x++)
2518 {
2519 printf("%s", outOfSearch);
2520 }
2521
2522 for(x = calibStart; x < sizeX; x++)
2523 {
2524 if(((*scPtr).result2D[xStart + x] >> (i << shiftAmount)) & dataMask)
2525 { /* FAIL - RISING EDGE */
2526 if(x != maxMidPointX)
2527 { /* REGULAR FAIL */
2528 printf("%s", fail_high);
2529 }
2530 else
2531 { /* FAIL - RISING EDGE */
2532 if((calibPos == SHMOO_AND28_CALIB_RISING_EDGE) || (calibPos == SHMOO_AND28_CALIB_FAIL_START))
2533 { /* RISING EDGE */
2534 printf("X");
2535 }
2536 else
2537 { /* FAIL */
2538 printf("%s", fail_high);
2539 }
2540 }
2541 }
2542 else
2543 { /* PASS - MIDPOINT - FALLING EDGE */
2544 if(x != maxMidPointX)
2545 { /* REGULAR PASS */
2546 printf("%s", pass_low);
2547 }
2548 else
2549 { /* POTENTIAL MIDPOINT - FALLING EDGE */
2550 if(y == maxMidPointY)
2551 { /* MID POINT - FALLING EDGE */
2552 printf("X");
2553 }
2554 else
2555 { /* PASS */
2556 printf("%s", pass_low);
2557 }
2558 }
2559 }
2560 }
2561 printf("\n");
2562 xStart += sizeX;
2563 }
2564 printf("\n");
2565 }
2566 else
2567 {
2568 if(i == 0)
2569 {
2570 switch(calibMode)
2571 {
2572 case SHMOO_AND28_BIT:
2573 printf(" *** Calib mode......: 1D Bit-wise\n");
2574 break;
2575 case SHMOO_AND28_BYTE:
2576 printf(" *** Calib mode......: 1D Byte-wise\n");
2577 break;
2578 case SHMOO_AND28_HALFWORD:
2579 printf(" *** Calib mode......: 1D Halfword-wise\n");
2580 break;
2581 case SHMOO_AND28_WORD:
2582 printf(" *** Calib mode......: 1D Word-wise\n");
2583 break;
2584 default:
2585 printf("Unsupported calibration mode during plot: %02u\n", calibMode);
2586 return SOC_E_FAIL;
2587 }
2588
2589 switch(plotMode)
2590 {
2591 case SHMOO_AND28_BIT:
2592 printf(" *** Plot mode.......: 1D Bit-wise\n");
2593 break;
2594 case SHMOO_AND28_BYTE:
2595 printf(" *** Plot mode.......: 1D Byte-wise\n");
2596 break;
2597 case SHMOO_AND28_HALFWORD:
2598 printf(" *** Plot mode.......: 1D Halfword-wise\n");
2599 break;
2600 case SHMOO_AND28_WORD:
2601 printf(" *** Plot mode.......: 1D Word-wise\n");
2602 break;
2603 default:
2604 printf("Unsupported plot mode: %02u\n", plotMode);
2605 return SOC_E_FAIL;
2606 }
2607 printf(" %s\n", str0);
2608 printf(" %s\n", str1);
2609 printf(" %s\n", str2);
2610 }
2611
2612 printf(" %03u ", i);
2613
2614 for(x = 0; x < calibStart; x++)
2615 {
2616 printf("%s", outOfSearch);
2617 }
2618
2619 for(x = calibStart; x < sizeX; x++)
2620 {
2621 if(((*scPtr).result2D[x] >> (i << shiftAmount)) & dataMask)
2622 { /* FAIL - RISING EDGE */
2623 if(x != maxMidPointX)
2624 { /* REGULAR FAIL */
2625 printf("%s", fail_high);
2626 }
2627 else
2628 { /* FAIL - RISING EDGE */
2629 if((calibPos == SHMOO_AND28_CALIB_RISING_EDGE) || (calibPos == SHMOO_AND28_CALIB_FAIL_START))
2630 { /* RISING EDGE */
2631 printf("X");
2632 }
2633 else
2634 { /* FAIL */
2635 printf("%s", fail_high);
2636 }
2637 }
2638 }
2639 else
2640 { /* PASS - MIDPOINT - FALLING EDGE */
2641 if(x != maxMidPointX)
2642 { /* REGULAR PASS */
2643 printf("%s", pass_low);
2644 }
2645 else
2646 { /* MID POINT - FALLING EDGE */
2647 printf("X");
2648 }
2649 }
2650 }
2651 printf("\n");
2652 }
2653 }
2654 printf("\n");
2655
2656 return SOC_E_NONE;
2657}
2658
2659static int
2660_shmoo_and28_plot(int unit, int phy_ndx, and28_shmoo_container_t *scPtr)
2661{
2662 switch ((*scPtr).shmooType) {
2663 case SHMOO_AND28_RD_EN:
2664 return _plot(unit, phy_ndx, scPtr, SHMOO_AND28_BYTE);
2665 case SHMOO_AND28_RD_EXTENDED:
2666 return _plot(unit, phy_ndx, scPtr, SHMOO_AND28_BYTE);
2667 case SHMOO_AND28_WR_EXTENDED:
2668 return _plot(unit, phy_ndx, scPtr, SHMOO_AND28_BIT);
2669 case SHMOO_AND28_ADDR_EXTENDED:
2670 return _plot(unit, phy_ndx, scPtr, SHMOO_AND28_WORD);
2671 case SHMOO_AND28_CTRL_EXTENDED:
2672 if(!SHMOO_AND28_QUICK_SHMOO_CTRL_EXTENDED)
2673 {
2674 return _plot(unit, phy_ndx, scPtr, SHMOO_AND28_WORD);
2675 }
2676 else
2677 {
2678 printf("\n\n");
2679 printf("***** Interface.......: %3d\n", phy_ndx);
2680 printf(" **** Shmoo type......: CTRL_EXTENDED\n");
2681 printf(" *** Quick Shmoo.....: On\n");
2682 printf(" *** Plot............: Off\n");
2683 printf(" *** Copying.........: VDL_STEP\n");
2684 printf(" ** From............: AD00 - AD09\n");
2685 printf(" ** To..............: AD10 - WE_N\n");
2686 printf("\n");
2687 }
2688 break;
2689 default:
2690 printf("Unsupported shmoo type: %02u\n", (*scPtr).shmooType);
2691 return SOC_E_FAIL;
2692 }
2693 return SOC_E_NONE;
2694}
2695#endif
2696
2697int
2698_and28_calculate_step_size(int unit, int phy_ndx, and28_step_size_t *ssPtr)
2699{
2700 uint32 data;
2701 uint32 timeout;
2702
2703 if(shmoo_dram_info_ptr->sim_system_mode)
2704 {
2705 (*ssPtr).step1000 = 8000;
2706 (*ssPtr).size1000UI = 78125;
2707
2708 return SOC_E_NONE;
2709 }
2710
2711 data = 0;
2712 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE, data);
2713 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
2714
2715 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VDL_CALIBRATE, CALIB_ONCE, 1);
2716 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VDL_CALIBRATE, UPDATE_REGS, 0);
2717 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VDL_CALIBRATE, UPDATE_FAST, 0);
2718 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE, data);
2719 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
2720
2721 timeout = 2000;
2722 do
2723 {
2724 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1, &data);
2725
2726 if(DDR_PHY_GET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VDL_CALIB_STATUS1, CALIB_IDLE))
2727 {
2728 /* printf(" VDL calibration complete.\n"); */
2729 break;
2730 }
2731
2732 if (timeout == 0)
2733 {
2734 printf(" VDL calibration failed!!! (Timeout)\n");
2735 return SOC_E_TIMEOUT;
2736 }
2737
2738 timeout--;
2739 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
2740 }
2741 while(TRUE);
2742
2743 if(DDR_PHY_GET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VDL_CALIB_STATUS1, CALIB_LOCK_4B) == 0)
2744 {
2745 printf(" VDL calibration failed!!! (No lock)\n");
2746 return SOC_E_FAIL;
2747 }
2748
2749 (*ssPtr).size1000UI = DDR_PHY_GET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VDL_CALIB_STATUS1, CALIB_TOTAL_STEPS) * 500;
2750 (*ssPtr).step1000 = ((1000000000 / shmoo_dram_info_ptr->data_rate_mbps) * 1000) / ((*ssPtr).size1000UI);
2751
2752 data = 0;
2753 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE, data);
2754 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
2755
2756 return SOC_E_NONE;
2757}
2758
2759int
2760_and28_zq_calibration(int unit, int phy_ndx)
2761{
2762 int i;
2763 uint32 data;
2764 uint32 p_drive, n_drive;
2765 uint32 p_term, n_term;
2766 uint32 p_idle, n_idle;
2767
2768 p_drive = 16;
2769 n_drive = 16;
2770
2771 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL, &data);
2772 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, ZQ_CAL, ZQ_PCOMP_ENB, 1);
2773 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, ZQ_CAL, ZQ_NCOMP_ENB, 1);
2774 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL, data);
2775 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
2776
2777 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, ZQ_CAL, ZQ_IDDQ, 0);
2778 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, ZQ_CAL, ZQ_DRIVE_P, 0);
2779 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, ZQ_CAL, ZQ_DRIVE_N, 31);
2780 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL, data);
2781 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
2782
2783 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, ZQ_CAL, ZQ_PCOMP_ENB, 0);
2784 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, ZQ_CAL, ZQ_NCOMP_ENB, 1);
2785 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL, data);
2786 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
2787
2788 for(i = 0; i < SHMOO_AND28_MAX_ZQ_CAL_RANGE; i++)
2789 {
2790 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, ZQ_CAL, ZQ_DRIVE_P, i);
2791 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL, data);
2792 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
2793
2794 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL, &data);
2795 if(DDR_PHY_GET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, ZQ_CAL, ZQ_PCOMP_STATUS))
2796 {
2797 p_drive = i;
2798 break;
2799 }
2800 }
2801
2802 if(i == SHMOO_AND28_MAX_ZQ_CAL_RANGE)
2803 {
2804 printf(" WARNING: ZQ calibration error (P) - Manual IO programming required for correct operation\n");
2805 /* return SOC_E_FAIL; */
2806 }
2807
2808 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, ZQ_CAL, ZQ_PCOMP_ENB, 0);
2809 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, ZQ_CAL, ZQ_NCOMP_ENB, 0);
2810 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL, data);
2811 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
2812
2813 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, ZQ_CAL, ZQ_DRIVE_P, 31);
2814 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, ZQ_CAL, ZQ_DRIVE_N, 0);
2815 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL, data);
2816 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
2817
2818 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, ZQ_CAL, ZQ_PCOMP_ENB, 1);
2819 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, ZQ_CAL, ZQ_NCOMP_ENB, 0);
2820 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL, data);
2821 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
2822
2823 for(i = 0; i < SHMOO_AND28_MAX_ZQ_CAL_RANGE; i++)
2824 {
2825 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, ZQ_CAL, ZQ_DRIVE_N, i);
2826 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL, data);
2827 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
2828
2829 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL, &data);
2830 if(DDR_PHY_GET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, ZQ_CAL, ZQ_NCOMP_STATUS))
2831 {
2832 n_drive = i;
2833 break;
2834 }
2835 }
2836
2837 if(i == SHMOO_AND28_MAX_ZQ_CAL_RANGE)
2838 {
2839 printf(" WARNING: ZQ calibration error (N) - Manual IO programming required for correct operation\n");
2840 /* return SOC_E_FAIL; */
2841 }
2842
2843 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, ZQ_CAL, ZQ_PCOMP_ENB, 1);
2844 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, ZQ_CAL, ZQ_NCOMP_ENB, 1);
2845 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL, data);
2846 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
2847
2848 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, ZQ_CAL, ZQ_IDDQ, 0);
2849 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, ZQ_CAL, ZQ_DRIVE_P, 0);
2850 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, ZQ_CAL, ZQ_DRIVE_N, 0);
2851 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL, data);
2852 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
2853
2854 p_term = 6;
2855 n_term = 6;
2856
2857 p_idle = 0;
2858 n_idle = 0;
2859
2860 data = 0;
2861 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, DRIVE_PAD_CTL, ADDR_CTL_PD_IDLE_STRENGTH, p_idle);
2862 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, DRIVE_PAD_CTL, ADDR_CTL_ND_IDLE_STRENGTH, n_idle);
2863 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, DRIVE_PAD_CTL, ADDR_CTL_PD_TERM_STRENGTH, p_term);
2864 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, DRIVE_PAD_CTL, ADDR_CTL_ND_TERM_STRENGTH, n_term);
2865 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, DRIVE_PAD_CTL, ADDR_CTL_PD_STRENGTH, p_drive);
2866 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, DRIVE_PAD_CTL, ADDR_CTL_ND_STRENGTH, n_drive);
2867 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL, data);
2868
2869 data = 0;
2870 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
2871 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, DRIVE_PAD_CTL, BL_PD_IDLE_STRENGTH, p_idle);
2872 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, DRIVE_PAD_CTL, BL_ND_IDLE_STRENGTH, n_idle);
2873 #endif
2874 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, DRIVE_PAD_CTL, BL_PD_TERM_STRENGTH, p_term);
2875 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, DRIVE_PAD_CTL, BL_ND_TERM_STRENGTH, n_term);
2876 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, DRIVE_PAD_CTL, BL_PD_STRENGTH, p_drive);
2877 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, DRIVE_PAD_CTL, BL_ND_STRENGTH, n_drive);
2878
2879 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_DRIVE_PAD_CTL, data);
2880 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_DRIVE_PAD_CTL, data);
2881
2882 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
2883 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
2884 {
2885 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_DRIVE_PAD_CTL, data);
2886 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_DRIVE_PAD_CTL, data);
2887 }
2888 #endif
2889
2890 #ifdef PHY_AND28_F0
2891 data = 0;
2892 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, DQSP_DRIVE_PAD_CTL, BL_PD_TERM_STRENGTH, p_term);
2893 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, DQSP_DRIVE_PAD_CTL, BL_ND_TERM_STRENGTH, n_term);
2894 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, DQSP_DRIVE_PAD_CTL, BL_PD_STRENGTH, p_drive);
2895 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, DQSP_DRIVE_PAD_CTL, BL_ND_STRENGTH, n_drive);
2896
2897 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_DQSP_DRIVE_PAD_CTL, data);
2898 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_DQSN_DRIVE_PAD_CTL, data);
2899 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_DQSP_DRIVE_PAD_CTL, data);
2900 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_DQSN_DRIVE_PAD_CTL, data);
2901
2902 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
2903 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
2904 {
2905 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_DQSP_DRIVE_PAD_CTL, data);
2906 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_DQSN_DRIVE_PAD_CTL, data);
2907 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_DQSP_DRIVE_PAD_CTL, data);
2908 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_DQSN_DRIVE_PAD_CTL, data);
2909 }
2910 #endif
2911
2912 data = 0;
2913 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, ALERT_DRIVE_PAD_CTL, BL_PD_TERM_STRENGTH, p_term);
2914 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, ALERT_DRIVE_PAD_CTL, BL_ND_TERM_STRENGTH, n_term);
2915 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, ALERT_DRIVE_PAD_CTL, BL_PD_STRENGTH, p_drive);
2916 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, ALERT_DRIVE_PAD_CTL, BL_ND_STRENGTH, n_drive);
2917
2918 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_ALERT_DRIVE_PAD_CTL, data);
2919 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_ALERT_DRIVE_PAD_CTL, data);
2920
2921 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
2922 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
2923 {
2924 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_ALERT_DRIVE_PAD_CTL, data);
2925 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_ALERT_DRIVE_PAD_CTL, data);
2926 }
2927 #endif
2928 #endif
2929
2930 data = 0;
2931 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
2932 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, RD_EN_DRIVE_PAD_CTL, EDC_RD_EN_PD_STRENGTH, p_drive);
2933 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, RD_EN_DRIVE_PAD_CTL, EDC_RD_EN_ND_STRENGTH, n_drive);
2934 #endif
2935 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, RD_EN_DRIVE_PAD_CTL, BL_RD_EN_PD_STRENGTH, p_drive);
2936 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, RD_EN_DRIVE_PAD_CTL, BL_RD_EN_ND_STRENGTH, n_drive);
2937
2938 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL, data);
2939 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL, data);
2940
2941 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
2942 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
2943 {
2944 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL, data);
2945 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL, data);
2946 }
2947 #endif
2948
2949 printf(" P drive..........: 0x%02X\n", p_drive);
2950 printf(" N drive..........: 0x%02X\n", n_drive);
2951 printf(" P termination....: 0x%02X\n", p_term);
2952 printf(" N termination....: 0x%02X\n", n_term);
2953 printf(" P idle...........: 0x%02X\n", p_idle);
2954 printf(" N idle...........: 0x%02X\n", n_idle);
2955
2956 return SOC_E_NONE;
2957}
2958
2959static int
2960_shmoo_and28_entry(int unit, int phy_ndx, and28_shmoo_container_t *scPtr, uint32 mode)
2961{
2962 /* Mode 0: Sequential entry
2963 * Mode 1: Single entry
2964 */
2965
2966 uint32 i;
2967 uint32 data, temp;
2968 and28_step_size_t ss;
2969
2970 (*scPtr).calibStart = 0;
2971
2972 switch ((*scPtr).shmooType) {
2973 case SHMOO_AND28_RD_EN:
2974 /*A04*/ printf("R04. Configure reference voltage\n");
2975 /*R04*/ DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL, &data);
2976 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VREF_DAC_CONTROL, DAC0, 32);
2977 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VREF_DAC_CONTROL, DAC1, 32);
2978 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL, data);
2979 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
2980
2981 /*A08*/ printf("R08. ZQ calibration\n");
2982 /*R08*/ if(shmoo_dram_info_ptr->sim_system_mode)
2983 {
2984 printf(" Skipped for emulation\n");
2985
2986 goto SHMOO_AND28_RD_EN_ZQ_CALIBRATION_END;
2987 }
2988
2989 _and28_zq_calibration(unit, phy_ndx);
2990
2991 SHMOO_AND28_RD_EN_ZQ_CALIBRATION_END:
2992
2993 _and28_calculate_step_size(unit, phy_ndx, &ss);
2994 (*scPtr).step1000 = ss.step1000;
2995 (*scPtr).size1000UI = ss.size1000UI;
2996 temp = (ss.size1000UI * 3) / 1000; /* 300% */
2997 if(temp > SHMOO_AND28_MAX_VDL_LENGTH)
2998 {
2999 (*scPtr).sizeX = SHMOO_AND28_MAX_VDL_LENGTH;
3000 }
3001 else
3002 {
3003 (*scPtr).sizeX = temp;
3004 }
3005
3006 temp = (ss.size1000UI * 125) / 100000; /* 125% */
3007 (*scPtr).yJump = 2;
3008 temp = temp >> (*scPtr).yJump;
3009 if(temp > SHMOO_AND28_MAX_VREF_RANGE)
3010 {
3011 (*scPtr).sizeY = SHMOO_AND28_MAX_VREF_RANGE;
3012 }
3013 else
3014 {
3015 (*scPtr).sizeY = temp;
3016 }
3017
3018 for(i = 0; i < SHMOO_AND28_MAX_VISIBLE_UI_COUNT; i++)
3019 {
3020 (*scPtr).endUI[i] = ((i + 1) * (ss.size1000UI)) / 1000;
3021 }
3022
3023 data = 0;
3024 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, READ_CONTROL, MODE, 1);
3025 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, READ_CONTROL, RD_DATA_DLY, SHMOO_AND28_RD_DATA_DLY_INIT);
3026 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_READ_CONTROL, data);
3027 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_READ_CONTROL, data);
3028
3029 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
3030 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
3031 {
3032 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_READ_CONTROL, data);
3033 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_READ_CONTROL, data);
3034 }
3035 #endif
3036
3037 data = 0;
3038 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, RD_EN_DLY_CYC, FORCE, 1);
3039 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, RD_EN_DLY_CYC, CS0_CYCLES, SHMOO_AND28_RD_EN_CYC_INIT);
3040 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, RD_EN_DLY_CYC, CS1_CYCLES, SHMOO_AND28_RD_EN_CYC_INIT);
3041 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DLY_CYC, data);
3042 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DLY_CYC, data);
3043
3044 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
3045 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
3046 {
3047 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_RD_EN_DLY_CYC, data);
3048 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_RD_EN_DLY_CYC, data);
3049 }
3050 #endif
3051
3052 data = 0;
3053 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
3054 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_RD_EN_VDL_INIT);
3055 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, data);
3056 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, data);
3057
3058 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
3059 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
3060 {
3061 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, data);
3062 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, data);
3063 }
3064 #endif
3065
3066 data = 0;
3067 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS1, FORCE, 1);
3068 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS1, VDL_STEP, SHMOO_AND28_RD_EN_VDL_INIT);
3069 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1, data);
3070 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1, data);
3071
3072 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
3073 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
3074 {
3075 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1, data);
3076 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1, data);
3077 }
3078 #endif
3079
3080 data = 0;
3081 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQ0P, FORCE, 1);
3082 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQ0P, VDL_STEP, SHMOO_AND28_RD_DQ_VDL_INIT);
3083 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P, data);
3084 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N, data);
3085 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P, data);
3086 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N, data);
3087 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P, data);
3088 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N, data);
3089 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P, data);
3090 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N, data);
3091 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P, data);
3092 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N, data);
3093 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P, data);
3094 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N, data);
3095 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P, data);
3096 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N, data);
3097 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P, data);
3098 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N, data);
3099 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP, data);
3100 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN, data);
3101 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
3102 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP, data);
3103 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN, data);
3104 #endif
3105 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P, data);
3106 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N, data);
3107 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P, data);
3108 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N, data);
3109 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P, data);
3110 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N, data);
3111 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P, data);
3112 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N, data);
3113 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P, data);
3114 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N, data);
3115 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P, data);
3116 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N, data);
3117 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P, data);
3118 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N, data);
3119 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P, data);
3120 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N, data);
3121 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP, data);
3122 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN, data);
3123 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
3124 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP, data);
3125 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN, data);
3126 #endif
3127
3128 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
3129 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
3130 {
3131 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P, data);
3132 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N, data);
3133 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P, data);
3134 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N, data);
3135 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P, data);
3136 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N, data);
3137 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P, data);
3138 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N, data);
3139 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P, data);
3140 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N, data);
3141 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P, data);
3142 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N, data);
3143 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P, data);
3144 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N, data);
3145 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P, data);
3146 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N, data);
3147 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP, data);
3148 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN, data);
3149 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
3150 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP, data);
3151 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN, data);
3152 #endif
3153 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P, data);
3154 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N, data);
3155 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P, data);
3156 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N, data);
3157 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P, data);
3158 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N, data);
3159 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P, data);
3160 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N, data);
3161 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P, data);
3162 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N, data);
3163 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P, data);
3164 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N, data);
3165 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P, data);
3166 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N, data);
3167 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P, data);
3168 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N, data);
3169 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP, data);
3170 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN, data);
3171 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
3172 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP, data);
3173 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN, data);
3174 #endif
3175 }
3176 #endif
3177
3178 data = 0;
3179 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, FORCE, 1);
3180 temp = (((*scPtr).size1000UI * 3) / 4000) + SHMOO_AND28_RD_DQS_VDL_OFFSET; /* 75% + Offset */
3181 if(temp > SHMOO_AND28_MAX_VDL_LENGTH)
3182 {
3183 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
3184 }
3185 else
3186 {
3187 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, VDL_STEP, temp);
3188 }
3189 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP, data);
3190 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN, data);
3191 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP, data);
3192 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN, data);
3193
3194 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
3195 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
3196 {
3197 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP, data);
3198 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN, data);
3199 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP, data);
3200 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN, data);
3201 }
3202 #endif
3203
3204 data = 0;
3205 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, WR_CHAN_DLY_CYC, FORCE, 1);
3206 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, WR_CHAN_DLY_CYC, CYCLES, SHMOO_AND28_WR_CYC_INIT);
3207 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC, data);
3208 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC, data);
3209
3210 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
3211 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
3212 {
3213 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC, data);
3214 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC, data);
3215 }
3216 #endif
3217
3218 data = 0;
3219 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_WR_DQ0, FORCE, 1);
3220 temp = (*scPtr).size1000UI / 2000;
3221 if(temp > SHMOO_AND28_MAX_VDL_LENGTH)
3222 {
3223 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_WR_DQ0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
3224 }
3225 else
3226 {
3227 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_WR_DQ0, VDL_STEP, temp);
3228 }
3229 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0, data);
3230 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1, data);
3231 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2, data);
3232 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3, data);
3233 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4, data);
3234 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5, data);
3235 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6, data);
3236 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7, data);
3237 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM, data);
3238 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
3239 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC, data);
3240 #endif
3241 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0, data);
3242 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1, data);
3243 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2, data);
3244 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3, data);
3245 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4, data);
3246 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5, data);
3247 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6, data);
3248 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7, data);
3249 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM, data);
3250 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
3251 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC, data);
3252 #endif
3253
3254 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
3255 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
3256 {
3257 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0, data);
3258 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1, data);
3259 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2, data);
3260 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3, data);
3261 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4, data);
3262 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5, data);
3263 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6, data);
3264 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7, data);
3265 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM, data);
3266 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
3267 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC, data);
3268 #endif
3269 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0, data);
3270 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1, data);
3271 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2, data);
3272 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3, data);
3273 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4, data);
3274 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5, data);
3275 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6, data);
3276 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7, data);
3277 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM, data);
3278 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
3279 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC, data);
3280 #endif
3281 }
3282 #endif
3283
3284 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
3285 break;
3286 case SHMOO_AND28_RD_EXTENDED:
3287 _and28_calculate_step_size(unit, phy_ndx, &ss);
3288 (*scPtr).step1000 = ss.step1000;
3289 (*scPtr).size1000UI = ss.size1000UI;
3290 temp = (ss.size1000UI * 125) / 100000; /* 125% */
3291 if(temp > SHMOO_AND28_MAX_VDL_LENGTH)
3292 {
3293 (*scPtr).sizeX = SHMOO_AND28_MAX_VDL_LENGTH;
3294 }
3295 else
3296 {
3297 (*scPtr).sizeX = temp;
3298 }
3299
3300 for(i = 0; i < SHMOO_AND28_MAX_VISIBLE_UI_COUNT; i++)
3301 {
3302 (*scPtr).endUI[i] = ((i + 1) * (ss.size1000UI)) / 1000;
3303 }
3304 break;
3305 case SHMOO_AND28_WR_EXTENDED:
3306 _and28_calculate_step_size(unit, phy_ndx, &ss);
3307 (*scPtr).step1000 = ss.step1000;
3308 (*scPtr).size1000UI = ss.size1000UI;
3309 temp = (ss.size1000UI * 125) / 100000; /* 125% */
3310 if(temp > SHMOO_AND28_MAX_VDL_LENGTH)
3311 {
3312 (*scPtr).sizeX = SHMOO_AND28_MAX_VDL_LENGTH;
3313 }
3314 else
3315 {
3316 (*scPtr).sizeX = temp;
3317 }
3318
3319 for(i = 0; i < SHMOO_AND28_MAX_VISIBLE_UI_COUNT; i++)
3320 {
3321 (*scPtr).endUI[i] = ((i + 1) * (ss.size1000UI)) / 1000;
3322 }
3323 break;
3324 case SHMOO_AND28_ADDR_EXTENDED:
3325 _and28_calculate_step_size(unit, phy_ndx, &ss);
3326 (*scPtr).step1000 = ss.step1000;
3327 (*scPtr).size1000UI = ss.size1000UI;
3328 temp = (ss.size1000UI * 25) / 10000; /* 250% */
3329 if(temp > SHMOO_AND28_MAX_VDL_LENGTH)
3330 {
3331 (*scPtr).sizeX = SHMOO_AND28_MAX_VDL_LENGTH;
3332 }
3333 else
3334 {
3335 (*scPtr).sizeX = temp;
3336 }
3337
3338 for(i = 0; i < SHMOO_AND28_MAX_VISIBLE_UI_COUNT; i++)
3339 {
3340 (*scPtr).endUI[i] = ((i + 1) * (ss.size1000UI)) / 1000;
3341 }
3342 break;
3343 case SHMOO_AND28_CTRL_EXTENDED:
3344 _and28_calculate_step_size(unit, phy_ndx, &ss);
3345 (*scPtr).step1000 = ss.step1000;
3346 (*scPtr).size1000UI = ss.size1000UI;
3347 temp = (ss.size1000UI * 25) / 10000; /* 250% */
3348 if(temp > SHMOO_AND28_MAX_VDL_LENGTH)
3349 {
3350 (*scPtr).sizeX = SHMOO_AND28_MAX_VDL_LENGTH;
3351 }
3352 else
3353 {
3354 (*scPtr).sizeX = temp;
3355 }
3356
3357 for(i = 0; i < SHMOO_AND28_MAX_VISIBLE_UI_COUNT; i++)
3358 {
3359 (*scPtr).endUI[i] = ((i + 1) * (ss.size1000UI)) / 1000;
3360 }
3361 break;
3362 default:
3363 printf("Unsupported shmoo type: %02u\n", (*scPtr).shmooType);
3364 return SOC_E_FAIL;
3365 }
3366 return SOC_E_NONE;
3367}
3368
3369static int
3370_shmoo_and28_exit(int unit, int phy_ndx, and28_shmoo_container_t *scPtr, uint32 mode)
3371{
3372 /* Mode 0: Sequential exit
3373 * Mode 1: Single exit
3374 */
3375
3376 switch ((*scPtr).shmooType) {
3377 case SHMOO_AND28_RD_EN:
3378 break;
3379 case SHMOO_AND28_RD_EXTENDED:
3380 break;
3381 case SHMOO_AND28_WR_EXTENDED:
3382 break;
3383 case SHMOO_AND28_ADDR_EXTENDED:
3384 break;
3385 case SHMOO_AND28_CTRL_EXTENDED:
3386 break;
3387 default:
3388 printf("Unsupported shmoo type: %02u\n", (*scPtr).shmooType);
3389 return SOC_E_FAIL;
3390 }
3391
3392 return SOC_E_NONE;
3393}
3394
3395static int
3396_shmoo_and28_save(int unit, int phy_ndx, and28_shmoo_config_param_t *config_param)
3397{
3398 uint32 data;
3399
3400 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00, &data);
3401 (*config_param).control_regs_ad[0] = (uint16) data;
3402 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01, &data);
3403 (*config_param).control_regs_ad[1] = (uint16) data;
3404 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02, &data);
3405 (*config_param).control_regs_ad[2] = (uint16) data;
3406 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03, &data);
3407 (*config_param).control_regs_ad[3] = (uint16) data;
3408 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04, &data);
3409 (*config_param).control_regs_ad[4] = (uint16) data;
3410 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05, &data);
3411 (*config_param).control_regs_ad[5] = (uint16) data;
3412 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06, &data);
3413 (*config_param).control_regs_ad[6] = (uint16) data;
3414 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07, &data);
3415 (*config_param).control_regs_ad[7] = (uint16) data;
3416 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08, &data);
3417 (*config_param).control_regs_ad[8] = (uint16) data;
3418 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09, &data);
3419 (*config_param).control_regs_ad[9] = (uint16) data;
3420 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10, &data);
3421 (*config_param).control_regs_ad[10] = (uint16) data;
3422 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11, &data);
3423 (*config_param).control_regs_ad[11] = (uint16) data;
3424 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12, &data);
3425 (*config_param).control_regs_ad[12] = (uint16) data;
3426 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13, &data);
3427 (*config_param).control_regs_ad[13] = (uint16) data;
3428 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14, &data);
3429 (*config_param).control_regs_ad[14] = (uint16) data;
3430 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15, &data);
3431 (*config_param).control_regs_ad[15] = (uint16) data;
3432 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0, &data);
3433 (*config_param).control_regs_ba[0] = (uint16) data;
3434 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1, &data);
3435 (*config_param).control_regs_ba[1] = (uint16) data;
3436 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2, &data);
3437 (*config_param).control_regs_ba[2] = (uint16) data;
3438 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0, &data);
3439 (*config_param).control_regs_aux[0] = (uint16) data;
3440 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1, &data);
3441 (*config_param).control_regs_aux[1] = (uint16) data;
3442 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2, &data);
3443 (*config_param).control_regs_aux[2] = (uint16) data;
3444 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0, &data);
3445 (*config_param).control_regs_cs[0] = (uint16) data;
3446 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1, &data);
3447 (*config_param).control_regs_cs[1] = (uint16) data;
3448 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR, &data);
3449 (*config_param).control_regs_par = (uint16) data;
3450 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N, &data);
3451 (*config_param).control_regs_ras_n = (uint16) data;
3452 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N, &data);
3453 (*config_param).control_regs_cas_n = (uint16) data;
3454 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE, &data);
3455 (*config_param).control_regs_cke = (uint16) data;
3456 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N, &data);
3457 (*config_param).control_regs_rst_n = (uint16) data;
3458 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT, &data);
3459 (*config_param).control_regs_odt = (uint16) data;
3460 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N, &data);
3461 (*config_param).control_regs_we_n = (uint16) data;
3462 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL, &data);
3463 (*config_param).control_regs_vref_dac_control = data;
3464
3465 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
3466 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P, &data);
3467 #elif defined(PHY_AND28_F0)
3468 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS, &data);
3469 #endif
3470 (*config_param).wr_vdl_dqsp[0] = (uint16) data;
3471 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
3472 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N, &data);
3473 (*config_param).wr_vdl_dqsn[0] = (uint16) data;
3474 #endif
3475 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0, &data);
3476 (*config_param).wr_vdl_dq[0][0] = (uint16) data;
3477 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1, &data);
3478 (*config_param).wr_vdl_dq[0][1] = (uint16) data;
3479 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2, &data);
3480 (*config_param).wr_vdl_dq[0][2] = (uint16) data;
3481 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3, &data);
3482 (*config_param).wr_vdl_dq[0][3] = (uint16) data;
3483 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4, &data);
3484 (*config_param).wr_vdl_dq[0][4] = (uint16) data;
3485 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5, &data);
3486 (*config_param).wr_vdl_dq[0][5] = (uint16) data;
3487 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6, &data);
3488 (*config_param).wr_vdl_dq[0][6] = (uint16) data;
3489 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7, &data);
3490 (*config_param).wr_vdl_dq[0][7] = (uint16) data;
3491 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM, &data);
3492 (*config_param).wr_vdl_dm[0] = (uint16) data;
3493 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
3494 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC, &data);
3495 (*config_param).wr_vdl_edc[0] = (uint16) data;
3496 #endif
3497 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC, &data);
3498 (*config_param).wr_chan_dly_cyc[0] = (uint8) data;
3499
3500 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP, &data);
3501 (*config_param).rd_vdl_dqsp[0] = (uint16) data;
3502 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN, &data);
3503 (*config_param).rd_vdl_dqsn[0] = (uint16) data;
3504 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P, &data);
3505 (*config_param).rd_vdl_dqp[0][0] = (uint16) data;
3506 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P, &data);
3507 (*config_param).rd_vdl_dqp[0][1] = (uint16) data;
3508 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P, &data);
3509 (*config_param).rd_vdl_dqp[0][2] = (uint16) data;
3510 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P, &data);
3511 (*config_param).rd_vdl_dqp[0][3] = (uint16) data;
3512 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P, &data);
3513 (*config_param).rd_vdl_dqp[0][4] = (uint16) data;
3514 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P, &data);
3515 (*config_param).rd_vdl_dqp[0][5] = (uint16) data;
3516 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P, &data);
3517 (*config_param).rd_vdl_dqp[0][6] = (uint16) data;
3518 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P, &data);
3519 (*config_param).rd_vdl_dqp[0][7] = (uint16) data;
3520 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N, &data);
3521 (*config_param).rd_vdl_dqn[0][0] = (uint16) data;
3522 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N, &data);
3523 (*config_param).rd_vdl_dqn[0][1] = (uint16) data;
3524 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N, &data);
3525 (*config_param).rd_vdl_dqn[0][2] = (uint16) data;
3526 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N, &data);
3527 (*config_param).rd_vdl_dqn[0][3] = (uint16) data;
3528 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N, &data);
3529 (*config_param).rd_vdl_dqn[0][4] = (uint16) data;
3530 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N, &data);
3531 (*config_param).rd_vdl_dqn[0][5] = (uint16) data;
3532 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N, &data);
3533 (*config_param).rd_vdl_dqn[0][6] = (uint16) data;
3534 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N, &data);
3535 (*config_param).rd_vdl_dqn[0][7] = (uint16) data;
3536 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP, &data);
3537 (*config_param).rd_vdl_dmp[0] = (uint16) data;
3538 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN, &data);
3539 (*config_param).rd_vdl_dmn[0] = (uint16) data;
3540 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, &data);
3541 (*config_param).rd_en_vdl_cs[0][0] = (uint16) data;
3542 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, &data);
3543 (*config_param).rd_en_vdl_cs[0][1] = (uint16) data;
3544 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DLY_CYC, &data);
3545 (*config_param).rd_en_dly_cyc[0] = (uint16) data;
3546 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_READ_CONTROL, &data);
3547 (*config_param).rd_control[0] = (uint8) data;
3548
3549 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
3550 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P, &data);
3551 #elif defined(PHY_AND28_F0)
3552 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS, &data);
3553 #endif
3554 (*config_param).wr_vdl_dqsp[1] = (uint16) data;
3555 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
3556 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N, &data);
3557 (*config_param).wr_vdl_dqsn[1] = (uint16) data;
3558 #endif
3559 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0, &data);
3560 (*config_param).wr_vdl_dq[1][0] = (uint16) data;
3561 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1, &data);
3562 (*config_param).wr_vdl_dq[1][1] = (uint16) data;
3563 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2, &data);
3564 (*config_param).wr_vdl_dq[1][2] = (uint16) data;
3565 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3, &data);
3566 (*config_param).wr_vdl_dq[1][3] = (uint16) data;
3567 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4, &data);
3568 (*config_param).wr_vdl_dq[1][4] = (uint16) data;
3569 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5, &data);
3570 (*config_param).wr_vdl_dq[1][5] = (uint16) data;
3571 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6, &data);
3572 (*config_param).wr_vdl_dq[1][6] = (uint16) data;
3573 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7, &data);
3574 (*config_param).wr_vdl_dq[1][7] = (uint16) data;
3575 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM, &data);
3576 (*config_param).wr_vdl_dm[1] = (uint16) data;
3577 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
3578 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC, &data);
3579 (*config_param).wr_vdl_edc[1] = (uint16) data;
3580 #endif
3581 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC, &data);
3582 (*config_param).wr_chan_dly_cyc[1] = (uint8) data;
3583
3584 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP, &data);
3585 (*config_param).rd_vdl_dqsp[1] = (uint16) data;
3586 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN, &data);
3587 (*config_param).rd_vdl_dqsn[1] = (uint16) data;
3588 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P, &data);
3589 (*config_param).rd_vdl_dqp[1][0] = (uint16) data;
3590 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P, &data);
3591 (*config_param).rd_vdl_dqp[1][1] = (uint16) data;
3592 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P, &data);
3593 (*config_param).rd_vdl_dqp[1][2] = (uint16) data;
3594 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P, &data);
3595 (*config_param).rd_vdl_dqp[1][3] = (uint16) data;
3596 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P, &data);
3597 (*config_param).rd_vdl_dqp[1][4] = (uint16) data;
3598 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P, &data);
3599 (*config_param).rd_vdl_dqp[1][5] = (uint16) data;
3600 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P, &data);
3601 (*config_param).rd_vdl_dqp[1][6] = (uint16) data;
3602 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P, &data);
3603 (*config_param).rd_vdl_dqp[1][7] = (uint16) data;
3604 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N, &data);
3605 (*config_param).rd_vdl_dqn[1][0] = (uint16) data;
3606 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N, &data);
3607 (*config_param).rd_vdl_dqn[1][1] = (uint16) data;
3608 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N, &data);
3609 (*config_param).rd_vdl_dqn[1][2] = (uint16) data;
3610 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N, &data);
3611 (*config_param).rd_vdl_dqn[1][3] = (uint16) data;
3612 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N, &data);
3613 (*config_param).rd_vdl_dqn[1][4] = (uint16) data;
3614 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N, &data);
3615 (*config_param).rd_vdl_dqn[1][5] = (uint16) data;
3616 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N, &data);
3617 (*config_param).rd_vdl_dqn[1][6] = (uint16) data;
3618 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N, &data);
3619 (*config_param).rd_vdl_dqn[1][7] = (uint16) data;
3620 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP, &data);
3621 (*config_param).rd_vdl_dmp[1] = (uint16) data;
3622 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN, &data);
3623 (*config_param).rd_vdl_dmn[1] = (uint16) data;
3624 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, &data);
3625 (*config_param).rd_en_vdl_cs[1][0] = (uint16) data;
3626 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, &data);
3627 (*config_param).rd_en_vdl_cs[1][1] = (uint16) data;
3628 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DLY_CYC, &data);
3629 (*config_param).rd_en_dly_cyc[1] = (uint16) data;
3630 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_READ_CONTROL, &data);
3631 (*config_param).rd_control[1] = (uint8) data;
3632
3633 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
3634 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
3635 {
3636 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
3637 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P, &data);
3638 #elif defined(PHY_AND28_F0)
3639 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS, &data);
3640 #endif
3641 (*config_param).wr_vdl_dqsp[2] = (uint16) data;
3642 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
3643 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N, &data);
3644 (*config_param).wr_vdl_dqsn[2] = (uint16) data;
3645 #endif
3646 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0, &data);
3647 (*config_param).wr_vdl_dq[2][0] = (uint16) data;
3648 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1, &data);
3649 (*config_param).wr_vdl_dq[2][1] = (uint16) data;
3650 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2, &data);
3651 (*config_param).wr_vdl_dq[2][2] = (uint16) data;
3652 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3, &data);
3653 (*config_param).wr_vdl_dq[2][3] = (uint16) data;
3654 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4, &data);
3655 (*config_param).wr_vdl_dq[2][4] = (uint16) data;
3656 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5, &data);
3657 (*config_param).wr_vdl_dq[2][5] = (uint16) data;
3658 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6, &data);
3659 (*config_param).wr_vdl_dq[2][6] = (uint16) data;
3660 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7, &data);
3661 (*config_param).wr_vdl_dq[2][7] = (uint16) data;
3662 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM, &data);
3663 (*config_param).wr_vdl_dm[2] = (uint16) data;
3664 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
3665 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC, &data);
3666 (*config_param).wr_vdl_edc[2] = (uint16) data;
3667 #endif
3668 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC, &data);
3669 (*config_param).wr_chan_dly_cyc[2] = (uint8) data;
3670
3671 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP, &data);
3672 (*config_param).rd_vdl_dqsp[2] = (uint16) data;
3673 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN, &data);
3674 (*config_param).rd_vdl_dqsn[2] = (uint16) data;
3675 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P, &data);
3676 (*config_param).rd_vdl_dqp[2][0] = (uint16) data;
3677 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P, &data);
3678 (*config_param).rd_vdl_dqp[2][1] = (uint16) data;
3679 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P, &data);
3680 (*config_param).rd_vdl_dqp[2][2] = (uint16) data;
3681 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P, &data);
3682 (*config_param).rd_vdl_dqp[2][3] = (uint16) data;
3683 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P, &data);
3684 (*config_param).rd_vdl_dqp[2][4] = (uint16) data;
3685 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P, &data);
3686 (*config_param).rd_vdl_dqp[2][5] = (uint16) data;
3687 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P, &data);
3688 (*config_param).rd_vdl_dqp[2][6] = (uint16) data;
3689 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P, &data);
3690 (*config_param).rd_vdl_dqp[2][7] = (uint16) data;
3691 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N, &data);
3692 (*config_param).rd_vdl_dqn[2][0] = (uint16) data;
3693 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N, &data);
3694 (*config_param).rd_vdl_dqn[2][1] = (uint16) data;
3695 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N, &data);
3696 (*config_param).rd_vdl_dqn[2][2] = (uint16) data;
3697 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N, &data);
3698 (*config_param).rd_vdl_dqn[2][3] = (uint16) data;
3699 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N, &data);
3700 (*config_param).rd_vdl_dqn[2][4] = (uint16) data;
3701 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N, &data);
3702 (*config_param).rd_vdl_dqn[2][5] = (uint16) data;
3703 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N, &data);
3704 (*config_param).rd_vdl_dqn[2][6] = (uint16) data;
3705 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N, &data);
3706 (*config_param).rd_vdl_dqn[2][7] = (uint16) data;
3707 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP, &data);
3708 (*config_param).rd_vdl_dmp[2] = (uint16) data;
3709 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN, &data);
3710 (*config_param).rd_vdl_dmn[2] = (uint16) data;
3711 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, &data);
3712 (*config_param).rd_en_vdl_cs[2][0] = (uint16) data;
3713 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, &data);
3714 (*config_param).rd_en_vdl_cs[2][1] = (uint16) data;
3715 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_RD_EN_DLY_CYC, &data);
3716 (*config_param).rd_en_dly_cyc[2] = (uint16) data;
3717 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_READ_CONTROL, &data);
3718 (*config_param).rd_control[2] = (uint8) data;
3719
3720 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
3721 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P, &data);
3722 #elif defined(PHY_AND28_F0)
3723 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS, &data);
3724 #endif
3725 (*config_param).wr_vdl_dqsp[3] = (uint16) data;
3726 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
3727 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N, &data);
3728 (*config_param).wr_vdl_dqsn[3] = (uint16) data;
3729 #endif
3730 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0, &data);
3731 (*config_param).wr_vdl_dq[3][0] = (uint16) data;
3732 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1, &data);
3733 (*config_param).wr_vdl_dq[3][1] = (uint16) data;
3734 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2, &data);
3735 (*config_param).wr_vdl_dq[3][2] = (uint16) data;
3736 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3, &data);
3737 (*config_param).wr_vdl_dq[3][3] = (uint16) data;
3738 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4, &data);
3739 (*config_param).wr_vdl_dq[3][4] = (uint16) data;
3740 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5, &data);
3741 (*config_param).wr_vdl_dq[3][5] = (uint16) data;
3742 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6, &data);
3743 (*config_param).wr_vdl_dq[3][6] = (uint16) data;
3744 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7, &data);
3745 (*config_param).wr_vdl_dq[3][7] = (uint16) data;
3746 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM, &data);
3747 (*config_param).wr_vdl_dm[3] = (uint16) data;
3748 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
3749 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC, &data);
3750 (*config_param).wr_vdl_edc[3] = (uint16) data;
3751 #endif
3752 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC, &data);
3753 (*config_param).wr_chan_dly_cyc[3] = (uint8) data;
3754
3755 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP, &data);
3756 (*config_param).rd_vdl_dqsp[3] = (uint16) data;
3757 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN, &data);
3758 (*config_param).rd_vdl_dqsn[3] = (uint16) data;
3759 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P, &data);
3760 (*config_param).rd_vdl_dqp[3][0] = (uint16) data;
3761 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P, &data);
3762 (*config_param).rd_vdl_dqp[3][1] = (uint16) data;
3763 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P, &data);
3764 (*config_param).rd_vdl_dqp[3][2] = (uint16) data;
3765 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P, &data);
3766 (*config_param).rd_vdl_dqp[3][3] = (uint16) data;
3767 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P, &data);
3768 (*config_param).rd_vdl_dqp[3][4] = (uint16) data;
3769 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P, &data);
3770 (*config_param).rd_vdl_dqp[3][5] = (uint16) data;
3771 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P, &data);
3772 (*config_param).rd_vdl_dqp[3][6] = (uint16) data;
3773 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P, &data);
3774 (*config_param).rd_vdl_dqp[3][7] = (uint16) data;
3775 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N, &data);
3776 (*config_param).rd_vdl_dqn[3][0] = (uint16) data;
3777 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N, &data);
3778 (*config_param).rd_vdl_dqn[3][1] = (uint16) data;
3779 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N, &data);
3780 (*config_param).rd_vdl_dqn[3][2] = (uint16) data;
3781 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N, &data);
3782 (*config_param).rd_vdl_dqn[3][3] = (uint16) data;
3783 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N, &data);
3784 (*config_param).rd_vdl_dqn[3][4] = (uint16) data;
3785 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N, &data);
3786 (*config_param).rd_vdl_dqn[3][5] = (uint16) data;
3787 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N, &data);
3788 (*config_param).rd_vdl_dqn[3][6] = (uint16) data;
3789 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N, &data);
3790 (*config_param).rd_vdl_dqn[3][7] = (uint16) data;
3791 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP, &data);
3792 (*config_param).rd_vdl_dmp[3] = (uint16) data;
3793 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN, &data);
3794 (*config_param).rd_vdl_dmn[3] = (uint16) data;
3795 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, &data);
3796 (*config_param).rd_en_vdl_cs[3][0] = (uint16) data;
3797 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, &data);
3798 (*config_param).rd_en_vdl_cs[3][1] = (uint16) data;
3799 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_RD_EN_DLY_CYC, &data);
3800 (*config_param).rd_en_dly_cyc[3] = (uint16) data;
3801 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_READ_CONTROL, &data);
3802 (*config_param).rd_control[3] = (uint8) data;
3803 }
3804 #endif
3805
3806 return SOC_E_NONE;
3807}
3808
3809static int
3810_shmoo_and28_restore(int unit, int phy_ndx, and28_shmoo_config_param_t *config_param)
3811{
3812 uint32 data;
3813
3814 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[0]);
3815 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00, data);
3816 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[1]);
3817 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01, data);
3818 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[2]);
3819 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02, data);
3820 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[3]);
3821 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03, data);
3822 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[4]);
3823 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04, data);
3824 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[5]);
3825 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05, data);
3826 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[6]);
3827 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06, data);
3828 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[7]);
3829 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07, data);
3830 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[8]);
3831 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08, data);
3832 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[9]);
3833 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09, data);
3834 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[10]);
3835 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10, data);
3836 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[11]);
3837 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11, data);
3838 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[12]);
3839 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12, data);
3840 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[13]);
3841 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13, data);
3842 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[14]);
3843 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14, data);
3844 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[15]);
3845 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15, data);
3846 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ba[0]);
3847 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0, data);
3848 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ba[1]);
3849 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1, data);
3850 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ba[2]);
3851 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2, data);
3852 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_aux[0]);
3853 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0, data);
3854 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_aux[1]);
3855 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1, data);
3856 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_aux[2]);
3857 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2, data);
3858 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_cs[0]);
3859 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0, data);
3860 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_cs[1]);
3861 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1, data);
3862 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_par);
3863 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR, data);
3864 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ras_n);
3865 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N, data);
3866 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_cas_n);
3867 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N, data);
3868 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_cke);
3869 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE, data);
3870 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_rst_n);
3871 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N, data);
3872 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_odt);
3873 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT, data);
3874 data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_we_n);
3875 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N, data);
3876 data = SET_VREF_DAC_CONTROL((*config_param).control_regs_vref_dac_control);
3877 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL, data);
3878
3879 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dqsp[0]);
3880 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
3881 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P, data);
3882 #elif defined(PHY_AND28_F0)
3883 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS, data);
3884 #endif
3885 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
3886 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dqsn[0]);
3887 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N, data);
3888 #endif
3889 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[0][0]);
3890 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0, data);
3891 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[0][1]);
3892 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1, data);
3893 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[0][2]);
3894 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2, data);
3895 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[0][3]);
3896 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3, data);
3897 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[0][4]);
3898 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4, data);
3899 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[0][5]);
3900 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5, data);
3901 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[0][6]);
3902 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6, data);
3903 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[0][7]);
3904 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7, data);
3905 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dm[0]);
3906 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM, data);
3907 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
3908 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_edc[0]);
3909 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC, data);
3910 #endif
3911 data = SET_WR_CHAN_DLY_CYC_FORCE((uint32) (*config_param).wr_chan_dly_cyc[0]);
3912 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC, data);
3913
3914 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqsp[0]);
3915 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP, data);
3916 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqsn[0]);
3917 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN, data);
3918 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[0][0]);
3919 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P, data);
3920 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[0][1]);
3921 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P, data);
3922 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[0][2]);
3923 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P, data);
3924 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[0][3]);
3925 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P, data);
3926 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[0][4]);
3927 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P, data);
3928 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[0][5]);
3929 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P, data);
3930 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[0][6]);
3931 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P, data);
3932 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[0][7]);
3933 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P, data);
3934 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[0][0]);
3935 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N, data);
3936 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[0][1]);
3937 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N, data);
3938 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[0][2]);
3939 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N, data);
3940 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[0][3]);
3941 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N, data);
3942 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[0][4]);
3943 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N, data);
3944 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[0][5]);
3945 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N, data);
3946 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[0][6]);
3947 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N, data);
3948 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[0][7]);
3949 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N, data);
3950 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dmp[0]);
3951 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP, data);
3952 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dmn[0]);
3953 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN, data);
3954 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_en_vdl_cs[0][0]);
3955 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, data);
3956 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_en_vdl_cs[0][1]);
3957 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, data);
3958 data = SET_RD_EN_DLY_CYC_FORCE((uint32) (*config_param).rd_en_dly_cyc[0]);
3959 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DLY_CYC, data);
3960 data = SET_RD_CONTROL((uint32) (*config_param).rd_control[0]);
3961 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_READ_CONTROL, data);
3962
3963 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dqsp[1]);
3964 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
3965 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P, data);
3966 #elif defined(PHY_AND28_F0)
3967 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS, data);
3968 #endif
3969 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
3970 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dqsn[1]);
3971 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N, data);
3972 #endif
3973 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[1][0]);
3974 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0, data);
3975 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[1][1]);
3976 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1, data);
3977 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[1][2]);
3978 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2, data);
3979 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[1][3]);
3980 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3, data);
3981 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[1][4]);
3982 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4, data);
3983 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[1][5]);
3984 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5, data);
3985 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[1][6]);
3986 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6, data);
3987 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[1][7]);
3988 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7, data);
3989 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dm[1]);
3990 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM, data);
3991 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
3992 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_edc[1]);
3993 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC, data);
3994 #endif
3995 data = SET_WR_CHAN_DLY_CYC_FORCE((uint32) (*config_param).wr_chan_dly_cyc[1]);
3996 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC, data);
3997
3998 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqsp[1]);
3999 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP, data);
4000 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqsn[1]);
4001 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN, data);
4002 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[1][0]);
4003 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P, data);
4004 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[1][1]);
4005 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P, data);
4006 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[1][2]);
4007 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P, data);
4008 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[1][3]);
4009 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P, data);
4010 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[1][4]);
4011 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P, data);
4012 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[1][5]);
4013 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P, data);
4014 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[1][6]);
4015 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P, data);
4016 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[1][7]);
4017 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P, data);
4018 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[1][0]);
4019 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N, data);
4020 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[1][1]);
4021 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N, data);
4022 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[1][2]);
4023 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N, data);
4024 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[1][3]);
4025 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N, data);
4026 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[1][4]);
4027 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N, data);
4028 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[1][5]);
4029 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N, data);
4030 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[1][6]);
4031 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N, data);
4032 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[1][7]);
4033 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N, data);
4034 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dmp[1]);
4035 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP, data);
4036 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dmn[1]);
4037 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN, data);
4038 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_en_vdl_cs[1][0]);
4039 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, data);
4040 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_en_vdl_cs[1][1]);
4041 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, data);
4042 data = SET_RD_EN_DLY_CYC_FORCE((uint32) (*config_param).rd_en_dly_cyc[1]);
4043 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DLY_CYC, data);
4044 data = SET_RD_CONTROL((uint32) (*config_param).rd_control[1]);
4045 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_READ_CONTROL, data);
4046
4047 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
4048 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
4049 {
4050 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dqsp[2]);
4051 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
4052 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P, data);
4053 #elif defined(PHY_AND28_F0)
4054 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS, data);
4055 #endif
4056 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
4057 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dqsn[2]);
4058 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N, data);
4059 #endif
4060 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[2][0]);
4061 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0, data);
4062 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[2][1]);
4063 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1, data);
4064 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[2][2]);
4065 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2, data);
4066 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[2][3]);
4067 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3, data);
4068 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[2][4]);
4069 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4, data);
4070 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[2][5]);
4071 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5, data);
4072 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[2][6]);
4073 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6, data);
4074 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[2][7]);
4075 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7, data);
4076 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dm[2]);
4077 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM, data);
4078 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
4079 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_edc[2]);
4080 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC, data);
4081 #endif
4082 data = SET_WR_CHAN_DLY_CYC_FORCE((uint32) (*config_param).wr_chan_dly_cyc[2]);
4083 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC, data);
4084
4085 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqsp[2]);
4086 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP, data);
4087 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqsn[2]);
4088 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN, data);
4089 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[2][0]);
4090 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P, data);
4091 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[2][1]);
4092 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P, data);
4093 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[2][2]);
4094 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P, data);
4095 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[2][3]);
4096 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P, data);
4097 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[2][4]);
4098 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P, data);
4099 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[2][5]);
4100 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P, data);
4101 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[2][6]);
4102 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P, data);
4103 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[2][7]);
4104 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P, data);
4105 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[2][0]);
4106 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N, data);
4107 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[2][1]);
4108 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N, data);
4109 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[2][2]);
4110 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N, data);
4111 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[2][3]);
4112 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N, data);
4113 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[2][4]);
4114 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N, data);
4115 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[2][5]);
4116 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N, data);
4117 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[2][6]);
4118 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N, data);
4119 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[2][7]);
4120 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N, data);
4121 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dmp[2]);
4122 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP, data);
4123 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dmn[2]);
4124 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN, data);
4125 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_en_vdl_cs[2][0]);
4126 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, data);
4127 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_en_vdl_cs[2][1]);
4128 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, data);
4129 data = SET_RD_EN_DLY_CYC_FORCE((uint32) (*config_param).rd_en_dly_cyc[2]);
4130 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_RD_EN_DLY_CYC, data);
4131 data = SET_RD_CONTROL((uint32) (*config_param).rd_control[2]);
4132 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_READ_CONTROL, data);
4133
4134 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dqsp[3]);
4135 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
4136 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P, data);
4137 #elif defined(PHY_AND28_F0)
4138 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS, data);
4139 #endif
4140 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
4141 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dqsn[3]);
4142 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N, data);
4143 #endif
4144 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[3][0]);
4145 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0, data);
4146 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[3][1]);
4147 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1, data);
4148 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[3][2]);
4149 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2, data);
4150 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[3][3]);
4151 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3, data);
4152 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[3][4]);
4153 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4, data);
4154 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[3][5]);
4155 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5, data);
4156 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[3][6]);
4157 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6, data);
4158 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[3][7]);
4159 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7, data);
4160 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dm[3]);
4161 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM, data);
4162 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
4163 data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_edc[3]);
4164 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC, data);
4165 #endif
4166 data = SET_WR_CHAN_DLY_CYC_FORCE((uint32) (*config_param).wr_chan_dly_cyc[3]);
4167 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC, data);
4168
4169 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqsp[3]);
4170 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP, data);
4171 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqsn[3]);
4172 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN, data);
4173 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[3][0]);
4174 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P, data);
4175 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[3][1]);
4176 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P, data);
4177 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[3][2]);
4178 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P, data);
4179 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[3][3]);
4180 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P, data);
4181 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[3][4]);
4182 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P, data);
4183 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[3][5]);
4184 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P, data);
4185 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[3][6]);
4186 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P, data);
4187 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[3][7]);
4188 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P, data);
4189 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[3][0]);
4190 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N, data);
4191 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[3][1]);
4192 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N, data);
4193 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[3][2]);
4194 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N, data);
4195 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[3][3]);
4196 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N, data);
4197 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[3][4]);
4198 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N, data);
4199 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[3][5]);
4200 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N, data);
4201 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[3][6]);
4202 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N, data);
4203 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[3][7]);
4204 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N, data);
4205 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dmp[3]);
4206 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP, data);
4207 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dmn[3]);
4208 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN, data);
4209 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_en_vdl_cs[3][0]);
4210 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, data);
4211 data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_en_vdl_cs[3][1]);
4212 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, data);
4213 data = SET_RD_EN_DLY_CYC_FORCE((uint32) (*config_param).rd_en_dly_cyc[3]);
4214 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_RD_EN_DLY_CYC, data);
4215 data = SET_RD_CONTROL((uint32) (*config_param).rd_control[3]);
4216 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_READ_CONTROL, data);
4217 }
4218 #endif
4219
4220 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
4221
4222 data = 0;
4223 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, READ_FIFO_CLEAR, CLEAR, 1);
4224 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_CLEAR, data);
4225 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_CLEAR, data);
4226
4227 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
4228 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
4229 {
4230 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_READ_FIFO_CLEAR, data);
4231 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_READ_FIFO_CLEAR, data);
4232 }
4233 #endif
4234
4235 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
4236
4237 return SOC_E_NONE;
4238}
4239
4240/*
4241 * Function:
4242 * soc_and28_shmoo_ctl
4243 * Purpose:
4244 * Perform shmoo (PHY calibration) on specific DRC index.
4245 * Parameters:
4246 * unit - unit number
4247 * phy_ndx - DRC index to perform shmoo on.
4248 * shmoo_type - Selects shmoo sub-section to be performs (-1 for full shmoo)
4249 * stat - RFU
4250 * plot - Plot shmoo results when not equal to 0
4251 * action - Save/restore functionality
4252 * *config_param - PHY configuration saved/restored
4253 * Returns:
4254 * SOC_E_XXX
4255 * This routine may be called after a device is attached
4256 * or whenever a chip reset is required.
4257 */
4258
4259int
4260soc_and28_shmoo_ctl(int unit, int phy_ndx, int shmoo_type, int stat, int plot, int action, and28_shmoo_config_param_t *config_param)
4261{
4262 and28_shmoo_container_t *scPtr = NULL;
4263 uint32 dramType;
4264 uint32 ctlType;
4265 uint32 i;
4266 int ndx, ndxEnd;
4267 const uint32 *seqPtr;
4268 uint32 seqCount;
4269
4270 dramType = shmoo_dram_info_ptr->dram_type;
4271 ctlType = shmoo_dram_info_ptr->ctl_type;
4272
4273 if(!stat)
4274 {
4275 scPtr = &shmoo_container;
4276 if(scPtr == NULL)
4277 {
4278 return SOC_E_MEMORY;
4279 }
4280 sal_memset(scPtr, 0, sizeof(and28_shmoo_container_t));
4281
4282 if(phy_ndx != SHMOO_AND28_INTERFACE_RSVP)
4283 {
4284 ndx = phy_ndx;
4285 ndxEnd = phy_ndx + 1;
4286 }
4287 else
4288 {
4289 ndx = 0;
4290 ndxEnd = SHMOO_AND28_MAX_INTERFACES;
4291 }
4292
4293 for(; ndx < ndxEnd; ndx++)
4294 {
4295 if(!_shmoo_and28_check_dram(ndx)) {
4296 continue;
4297 }
4298
4299 if(action == SHMOO_AND28_ACTION_RESTORE)
4300 {
4301 switch(ctlType)
4302 {
4303 case SHMOO_AND28_CTL_TYPE_RSVP:
4304 break;
4305 case SHMOO_AND28_CTL_TYPE_1:
4306 _shmoo_and28_restore(unit, phy_ndx, config_param);
4307 break;
4308 default:
4309 if(scPtr != NULL)
4310 {
4311 /* sal_free(scPtr); */
4312 scPtr = NULL;
4313 }
4314
4315 printf("Unsupported controller type: %02u\n", ctlType);
4316 return SOC_E_FAIL;
4317 }
4318 }
4319 else if((action == SHMOO_AND28_ACTION_RUN) || (action == SHMOO_AND28_ACTION_RUN_AND_SAVE))
4320 {
4321 switch(ctlType)
4322 {
4323 case SHMOO_AND28_CTL_TYPE_RSVP:
4324 break;
4325 case SHMOO_AND28_CTL_TYPE_1:
4326 switch(dramType)
4327 {
4328#if (SHMOO_AND28_DRAM_TYPE == SHMOO_AND28_DRAM_TYPE_DDR3)
4329 case SHMOO_AND28_DRAM_TYPE_DDR3:
4330 seqPtr = &shmoo_order_and28_ddr3[0];
4331 seqCount = SHMOO_AND28_DDR3_SEQUENCE_COUNT;
4332 break;
4333#endif
4334#if (SHMOO_AND28_DRAM_TYPE == SHMOO_AND28_DRAM_TYPE_DDR3L)
4335 case SHMOO_AND28_DRAM_TYPE_DDR3L:
4336 seqPtr = &shmoo_order_and28_ddr3l[0];
4337 seqCount = SHMOO_AND28_DDR3L_SEQUENCE_COUNT;
4338 break;
4339#endif
4340 default:
4341 printf("Unsupported dram type: %02u\n", dramType);
4342 return SOC_E_FAIL;
4343 }
4344
4345 (*scPtr).dramType = dramType;
4346 (*scPtr).ctlType = ctlType;
4347
4348 if(shmoo_type != SHMOO_AND28_SHMOO_RSVP)
4349 {
4350 (*scPtr).shmooType = shmoo_type;
4351 _shmoo_and28_entry(unit, ndx, scPtr, SHMOO_AND28_SINGLE);
4352 _shmoo_and28_do(unit, ndx, scPtr);
4353 _shmoo_and28_calib_2D(unit, ndx, scPtr);
4354 _shmoo_and28_set_new_step(unit, ndx, scPtr);
4355#ifdef PLOT_SUPPORT
4356 if(plot)
4357 {
4358 _shmoo_and28_plot(unit, ndx, scPtr);
4359 }
4360#endif
4361 _shmoo_and28_exit(unit, ndx, scPtr, SHMOO_AND28_SINGLE);
4362 }
4363 else
4364 {
4365 for(i = 0; i < seqCount; i++)
4366 {
4367 (*scPtr).shmooType = seqPtr[i];
4368 _shmoo_and28_entry(unit, ndx, scPtr, SHMOO_AND28_SEQUENTIAL);
4369 _shmoo_and28_do(unit, ndx, scPtr);
4370 _shmoo_and28_calib_2D(unit, ndx, scPtr);
4371 _shmoo_and28_set_new_step(unit, ndx, scPtr);
4372#ifdef PLOT_SUPPORT
4373 if(plot)
4374 {
4375 _shmoo_and28_plot(unit, ndx, scPtr);
4376 }
4377#endif
4378 _shmoo_and28_exit(unit, ndx, scPtr, SHMOO_AND28_SEQUENTIAL);
4379 }
4380 }
4381
4382 break;
4383 default:
4384 if(scPtr != NULL)
4385 {
4386 /* sal_free(scPtr); */
4387 scPtr = NULL;
4388 }
4389
4390 printf("Unsupported controller type: %02u\n", ctlType);
4391 return SOC_E_FAIL;
4392 }
4393 }
4394
4395 if((action == SHMOO_AND28_ACTION_RUN_AND_SAVE) || (action == SHMOO_AND28_ACTION_SAVE))
4396 {
4397 _shmoo_and28_save(unit, phy_ndx, config_param);
4398 }
4399 }
4400
4401 if(scPtr != NULL)
4402 {
4403 /* sal_free(scPtr); */
4404 scPtr = NULL;
4405 }
4406
4407 printf("DDR Tuning Complete\n");
4408 }
4409 else
4410 {
4411 /* Report only */
4412 switch(ctlType)
4413 {
4414 case SHMOO_AND28_CTL_TYPE_RSVP:
4415 break;
4416 case SHMOO_AND28_CTL_TYPE_1:
4417 break;
4418 default:
4419 printf("Unsupported controller type: %02u\n", ctlType);
4420 return SOC_E_FAIL;
4421 }
4422 }
4423 return SOC_E_NONE;
4424}
4425
4426/* Set Dram Parameters/Info to Shmoo driver */
4427int
4428soc_and28_shmoo_dram_info_set(int unit, and28_shmoo_dram_info_t *sdi)
4429{
4430
4431#if(!SHMOO_AND28_PHY_CONSTANT_CONFIG)
4432 shmoo_dram_info_ptr = &shmoo_dram_info;
4433 shmoo_dram_info_ptr->ctl_type = (*sdi).ctl_type;
4434 shmoo_dram_info_ptr->dram_type = (*sdi).dram_type;
4435 shmoo_dram_info_ptr->dram_bitmap = (*sdi).dram_bitmap;
4436 shmoo_dram_info_ptr->interface_bitwidth = (*sdi).interface_bitwidth;
4437 shmoo_dram_info_ptr->num_columns = (*sdi).num_columns;
4438 shmoo_dram_info_ptr->num_rows = (*sdi).num_rows;
4439 shmoo_dram_info_ptr->num_banks = (*sdi).num_banks;
4440 shmoo_dram_info_ptr->data_rate_mbps = (*sdi).data_rate_mbps;
4441 shmoo_dram_info_ptr->ref_clk_mhz = (*sdi).ref_clk_mhz;
4442 shmoo_dram_info_ptr->refi = (*sdi).refi;
4443 shmoo_dram_info_ptr->command_parity_latency = (*sdi).command_parity_latency;
4444 shmoo_dram_info_ptr->sim_system_mode = (*sdi).sim_system_mode;
4445#endif
4446 return SOC_E_NONE;
4447}
4448
4449/* Configure PHY PLL and wait for lock */
4450int
4451_soc_and28_shmoo_phy_cfg_pll(int unit, int phy_ndx)
4452{
4453 int ndx, ndxEnd;
4454 uint32 data;
4455 uint32 timeout;
4456 uint32 pll_config;
4457 uint32 pll_control2;
4458 uint32 pll_dividers;
4459 uint32 pll_frac_divider;
4460
4461 if(shmoo_dram_info_ptr->ref_clk_mhz != 50)
4462 {
4463 printf(" Unsupported reference flock frequency: %4d MHz\n", shmoo_dram_info_ptr->ref_clk_mhz);
4464 return SOC_E_FAIL;
4465 }
4466
4467 switch(shmoo_dram_info_ptr->data_rate_mbps)
4468 {
4469 case 800:
4470 pll_config = 0x018D0012;
4471 pll_control2 = 0x94000000;
4472 pll_dividers = 0x004030C0;
4473 pll_frac_divider = 0x00000000;
4474 break;
4475 case 1066:
4476 pll_config = 0x018D0012;
4477 pll_control2 = 0x94000000;
4478 pll_dividers = 0x003030BF;
4479 pll_frac_divider = 0x000E147A;
4480 break;
4481 case 1333:
4482 pll_config = 0x018D0012;
4483 pll_control2 = 0x94000000;
4484 pll_dividers = 0x002030A0;
4485 pll_frac_divider = 0x000147AE;
4486 break;
4487 case 1600:
4488 pll_config = 0x018D0012;
4489 pll_control2 = 0x94000000;
4490 pll_dividers = 0x002030C0;
4491 pll_frac_divider = 0x00000000;
4492 break;
4493 default:
4494 printf(" Unsupported data rate: %4d Mbps\n", shmoo_dram_info_ptr->data_rate_mbps);
4495 return SOC_E_FAIL;
4496 }
4497
4498 printf(" PHY PLL Configuration\n");
4499 printf(" Fref.............: %4d MHz\n", shmoo_dram_info_ptr->ref_clk_mhz);
4500 printf(" Data rate........: %4d Mbps\n", shmoo_dram_info_ptr->data_rate_mbps);
4501
4502 if(phy_ndx != SHMOO_AND28_INTERFACE_RSVP)
4503 {
4504 ndx = phy_ndx;
4505 ndxEnd = phy_ndx + 1;
4506 }
4507 else
4508 {
4509 ndx = 0;
4510 ndxEnd = SHMOO_AND28_MAX_INTERFACES;
4511 }
4512
4513 for(; ndx < ndxEnd; ndx++)
4514 {
4515 if(!_shmoo_and28_check_dram(ndx))
4516 {
4517 continue;
4518 }
4519
4520 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG, pll_config);
4521 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2, pll_control2);
4522 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS, pll_dividers);
4523 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_PLL_FRAC_DIVIDER, pll_frac_divider);
4524
4525 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG, &data);
4526 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, PLL_CONFIG, RESET, 0);
4527 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG, data);
4528
4529 timeout = 2000;
4530 do
4531 {
4532 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS, &data);
4533
4534 if(DDR_PHY_GET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, PLL_STATUS, LOCK))
4535 {
4536 printf(" PLL locked.\n");
4537 break;
4538 }
4539
4540 if (timeout == 0)
4541 {
4542 printf(" PLL not locked!!! (Timeout)\n");
4543 return SOC_E_TIMEOUT;
4544 }
4545
4546 timeout--;
4547 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
4548 }
4549 while(TRUE);
4550
4551 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG, &data);
4552 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, PLL_CONFIG, RESET_POST_DIV, 0);
4553 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG, data);
4554 }
4555
4556 return SOC_E_NONE;
4557}
4558
4559int
4560soc_and28_shmoo_phy_init(int unit, int phy_ndx)
4561{
4562 int ndx, ndxEnd;
4563 uint32 data;
4564 uint32 dfi_ctrl;
4565 uint32 dram_config;
4566 uint32 dram_timing1;
4567 uint32 dram_timing2;
4568 uint32 dram_timing3;
4569 uint32 dram_timing4;
4570 uint32 size1000UI, sizeUI;
4571 and28_step_size_t ss;
4572
4573 if(phy_ndx != SHMOO_AND28_INTERFACE_RSVP)
4574 {
4575 ndx = phy_ndx;
4576 ndxEnd = phy_ndx + 1;
4577 }
4578 else
4579 {
4580 ndx = 0;
4581 ndxEnd = SHMOO_AND28_MAX_INTERFACES;
4582 }
4583
4584 for(; ndx < ndxEnd; ndx++)
4585 {
4586 if(!_shmoo_and28_check_dram(ndx))
4587 {
4588 continue;
4589 }
4590
4591 printf("A Series - PHY Initialization (PHY index: %02d)\n", ndx);
4592
4593/*A01*/ printf("A01. Turn off CKE\n");
4594 dfi_ctrl = 0;
4595 DDR_PHY_SET_FIELD(dfi_ctrl, DDR34_CORE_PHY_CONTROL_REGS, DFI_CNTRL, ASSERT_REQ, 1);
4596 DDR_PHY_SET_FIELD(dfi_ctrl, DDR34_CORE_PHY_CONTROL_REGS, DFI_CNTRL, DFI_CS0 , 1);
4597 DDR_PHY_SET_FIELD(dfi_ctrl, DDR34_CORE_PHY_CONTROL_REGS, DFI_CNTRL, DFI_CS1 , 1);
4598 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_F0))
4599 DDR_PHY_SET_FIELD(dfi_ctrl, DDR34_CORE_PHY_CONTROL_REGS, DFI_CNTRL, DFI_CKE , 0);
4600 #elif defined(PHY_AND28_E2)
4601 DDR_PHY_SET_FIELD(dfi_ctrl, DDR34_CORE_PHY_CONTROL_REGS, DFI_CNTRL, DFI_CKE0 , 0);
4602 DDR_PHY_SET_FIELD(dfi_ctrl, DDR34_CORE_PHY_CONTROL_REGS, DFI_CNTRL, DFI_CKE1 , 0);
4603 #endif
4604 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL, dfi_ctrl);
4605 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
4606
4607/*A02*/ printf("A02. Configure timing parameters\n");
4608 if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
4609 {
4610 switch(shmoo_dram_info_ptr->data_rate_mbps)
4611 {
4612 case 800:
4613 dram_timing1 = 0x0F040606;
4614 dram_timing2 = 0x04060506;
4615 dram_timing3 = 0x00044068;
4616 dram_timing4 = 0x00000000;
4617 break;
4618 case 1066:
4619 dram_timing1 = 0x14040707;
4620 dram_timing2 = 0x04080607;
4621 dram_timing3 = 0x0004408C;
4622 dram_timing4 = 0x00000000;
4623 break;
4624 case 1333:
4625 dram_timing1 = 0x18050909;
4626 dram_timing2 = 0x050A0709;
4627 dram_timing3 = 0x000450B0;
4628 dram_timing4 = 0x00000000;
4629 break;
4630 case 1600:
4631 dram_timing1 = 0x1C060B0B;
4632 dram_timing2 = 0x060C080B;
4633 dram_timing3 = 0x000460D0;
4634 dram_timing4 = 0x00000000;
4635 break;
4636 default:
4637 printf("Unsupported data rate: %4d Mbps\n", shmoo_dram_info_ptr->data_rate_mbps);
4638 return SOC_E_FAIL;
4639 }
4640 }
4641 else
4642 {
4643 switch(shmoo_dram_info_ptr->data_rate_mbps)
4644 {
4645 case 800:
4646 dram_timing1 = 0x0F040606;
4647 dram_timing2 = 0x04060506;
4648 dram_timing3 = 0x00044068;
4649 dram_timing4 = 0x00000000;
4650 break;
4651 case 1066:
4652 dram_timing1 = 0x14040707;
4653 dram_timing2 = 0x04080607;
4654 dram_timing3 = 0x0004408C;
4655 dram_timing4 = 0x00000000;
4656 break;
4657 case 1333:
4658 dram_timing1 = 0x18040909;
4659 dram_timing2 = 0x050A0709;
4660 dram_timing3 = 0x000450B0;
4661 dram_timing4 = 0x00000000;
4662 break;
4663 case 1600:
4664 dram_timing1 = 0x1C050B0B;
4665 dram_timing2 = 0x060C080B;
4666 dram_timing3 = 0x000460D0;
4667 dram_timing4 = 0x00000000;
4668 break;
4669 default:
4670 printf("Unsupported data rate: %4d Mbps\n", shmoo_dram_info_ptr->data_rate_mbps);
4671 return SOC_E_FAIL;
4672 }
4673 }
4674
4675 dram_config = 0x00001000;
4676 if (!SHMOO_AND28_PHY_BITWIDTH_IS_32)
4677 dram_config |= 0x02000000;
4678 switch(shmoo_dram_info_ptr->num_rows)
4679 {
4680 case 4096: dram_config |= 0x00000000; break;
4681 case 8192: dram_config |= 0x00000010; break;
4682 case 16384: dram_config |= 0x00000020; break;
4683 case 32768: dram_config |= 0x00000030; break;
4684 case 65536: dram_config |= 0x00000040; break;
4685 default:
4686 printf("Unsupported number of rows: %d\n", shmoo_dram_info_ptr->num_rows);
4687 return SOC_E_FAIL;
4688 }
4689 switch(shmoo_dram_info_ptr->num_columns)
4690 {
4691 case 512: dram_config |= 0x00000000; break;
4692 case 1024: dram_config |= 0x00000100; break;
4693 case 2048: dram_config |= 0x00000200; break;
4694 default:
4695 printf("Unsupported number of columns: %d\n", shmoo_dram_info_ptr->num_columns);
4696 return SOC_E_FAIL;
4697 }
4698 switch(shmoo_dram_info_ptr->num_banks)
4699 {
4700 case 4: dram_config |= 0x00000000; break;
4701 case 8: dram_config |= 0x00000400; break;
4702 default:
4703 printf("Unsupported number of banks: %d\n", shmoo_dram_info_ptr->num_banks);
4704 return SOC_E_FAIL;
4705 }
4706 printf("DRAM config: 0x%X\n", dram_config);
4707
4708 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG, dram_config);
4709 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING1, dram_timing1);
4710 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING2, dram_timing2);
4711 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3, dram_timing3);
4712 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING4, dram_timing4);
4713 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
4714
4715/*A03*/ printf("A03. Configure PHY PLL\n");
4716 _soc_and28_shmoo_phy_cfg_pll(unit, ndx);
4717 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
4718
4719/*A04*/ printf("A04. Configure reference voltage\n");
4720/*R04*/ DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL, &data);
4721 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VREF_DAC_CONTROL, DAC0, 32);
4722 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VREF_DAC_CONTROL, DAC1, 32);
4723 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL, data);
4724 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
4725
4726 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VREF_DAC_CONTROL, PDN0, 0);
4727 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VREF_DAC_CONTROL, PDN1, 0);
4728 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VREF_DAC_CONTROL, PDN2, 0);
4729 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VREF_DAC_CONTROL, PDN3, 0);
4730 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL, data);
4731 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
4732
4733/*A05*/ printf("A05. Compute VDL step size\n");
4734 _and28_calculate_step_size(unit, ndx, &ss);
4735
4736 size1000UI = ss.size1000UI;
4737 sizeUI = size1000UI / 1000;
4738 printf(" VDL calibration complete.\n");
4739 printf(" VDL step size....: %3u.%03u ps\n", (ss.step1000 / 1000), (ss.step1000 % 1000));
4740 printf(" UI size..........: %3u.%03u steps\n", sizeUI, (size1000UI % 1000));
4741
4742/*A06*/ printf("A06. Configure ADDR/CTRL VDLs\n");
4743 data = 0;
4744 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VDL_CONTROL_AD00, FORCE, 1);
4745 if(sizeUI > SHMOO_AND28_MAX_VDL_LENGTH)
4746 {
4747 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VDL_CONTROL_AD00, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
4748 }
4749 else
4750 {
4751 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VDL_CONTROL_AD00, VDL_STEP, sizeUI);
4752 }
4753 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00, data);
4754 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01, data);
4755 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02, data);
4756 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03, data);
4757 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04, data);
4758 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05, data);
4759 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06, data);
4760 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07, data);
4761 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08, data);
4762 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09, data);
4763 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10, data);
4764 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11, data);
4765 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12, data);
4766 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13, data);
4767 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14, data);
4768 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15, data);
4769 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0, data);
4770 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1, data);
4771 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2, data);
4772 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0, data);
4773 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1, data);
4774 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2, data);
4775 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0, data);
4776 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1, data);
4777 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR, data);
4778 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N, data);
4779 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N, data);
4780 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE, data);
4781 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N, data);
4782 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT, data);
4783 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N, data);
4784
4785/*A07*/ printf("A07. Disable Virtual VTT\n");
4786 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL, &data);
4787 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VIRTUAL_VTT_CONTROL, ENABLE_CTL_IDLE, 0);
4788 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VIRTUAL_VTT_CONTROL, ENABLE_CS_IDLE, 0);
4789 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VIRTUAL_VTT_CONTROL, ENABLE_CKE_IDLE, 0);
4790 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL, data);
4791
4792/*A08*/ printf("A08. ZQ calibration\n");
4793/*R08*/ if(shmoo_dram_info_ptr->sim_system_mode)
4794 {
4795 printf(" Skipped for emulation\n");
4796
4797 goto SHMOO_AND28_ZQ_CALIBRATION_END;
4798 }
4799
4800 _and28_zq_calibration(unit, ndx);
4801
4802 SHMOO_AND28_ZQ_CALIBRATION_END:
4803
4804/*A09*/ printf("A09. Configure Static Pad Control\n");
4805 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL, &data);
4806 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
4807 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, STATIC_PAD_CTL, IDDQ_CLK1, 1);
4808 #endif
4809 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, STATIC_PAD_CTL, AUTO_OEB, 1);
4810 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL, data);
4811 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
4812
4813/*A10*/ printf("A10. Configure ODT\n");
4814 data = 0;
4815 #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
4816 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, WRITE_ODT_CNTRL, ODT_FORCE, 1);
4817 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, WRITE_ODT_CNTRL, ODT_FORCE_VALUE, 1);
4818 #elif defined(PHY_AND28_F0)
4819 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, WRITE_ODT_CNTRL, ODT0_FORCE, 1);
4820 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, WRITE_ODT_CNTRL, ODT0_FORCE_VALUE, 1);
4821 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, WRITE_ODT_CNTRL, ODT1_FORCE, 1);
4822 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, WRITE_ODT_CNTRL, ODT1_FORCE_VALUE, 1);
4823 #endif
4824 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_WRITE_ODT_CNTRL, data);
4825
4826 data = 0;
4827 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, ODT_CONTROL, ODT_ENABLE, 1);
4828 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, ODT_CONTROL, ODT_DELAY, 0);
4829 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, ODT_CONTROL, ODT_POST_LENGTH, 2);
4830 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, ODT_CONTROL, ODT_PRE_LENGTH, 4);
4831 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_ODT_CONTROL, data);
4832 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_ODT_CONTROL, data);
4833 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
4834 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
4835 {
4836 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_ODT_CONTROL, data);
4837 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_ODT_CONTROL, data);
4838 }
4839 #endif
4840 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
4841
4842/*A11*/ printf("A11. Configure Write Pre-/Post-amble\n");
4843 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE, &data);
4844 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, WR_PREAMBLE_MODE, DQ_POSTAM_BITS, 1);
4845 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, WR_PREAMBLE_MODE, DQ_PREAM_BITS, 1);
4846 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, WR_PREAMBLE_MODE, DQS, 0xE);
4847 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, WR_PREAMBLE_MODE, DQS_POSTAM_BITS, 0);
4848 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, WR_PREAMBLE_MODE, DQS_PREAM_BITS, 2);
4849 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE, data);
4850 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE, data);
4851 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
4852 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
4853 {
4854 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE, data);
4855 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE, data);
4856 }
4857 #endif
4858 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
4859
4860/*A12*/ printf("A12. Configure Auto Idle\n");
4861 DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, &data);
4862 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, IDLE_PAD_CONTROL, AUTO_DQ_RXENB_MODE, 3);
4863 DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, IDLE_PAD_CONTROL, AUTO_DQ_IDDQ_MODE, 3);
4864 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, data);
4865 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, data);
4866 #if(SHMOO_AND28_PHY_BITWIDTH_IS_32)
4867 if(shmoo_dram_info_ptr->interface_bitwidth == 32)
4868 {
4869 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL, data);
4870 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL, data);
4871 }
4872 #endif
4873 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
4874
4875/*A13*/ printf("A13. Release PHY control\n");
4876 DDR_PHY_SET_FIELD(dfi_ctrl, DDR34_CORE_PHY_CONTROL_REGS, DFI_CNTRL, ASSERT_REQ, 0);
4877 DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL, data);
4878 sal_usleep(SHMOO_AND28_SHORT_SLEEP);
4879
4880 printf("A Series - PHY Initialization complete (PHY index: %02d)\n", ndx);
4881 }
4882
4883 return SOC_E_NONE;
4884}