Icarus Chau | d5f551a | 2015-02-13 15:16:37 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2015 Broadcom Corporation |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or |
| 5 | * modify it under the terms of the GNU General Public License as |
| 6 | * published by the Free Software Foundation version 2. |
| 7 | * |
| 8 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any |
| 9 | * kind, whether express or implied; without even the implied warranty |
| 10 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
| 14 | #include <delay.h> |
| 15 | #include <console/console.h> |
| 16 | #include <soc/config.h> |
| 17 | #include <soc/reg_utils.h> |
| 18 | |
| 19 | #define DDR_CTL_TYPE_1 1 |
| 20 | #define DDR_DRAM_TYPE_DDR3L 31 |
| 21 | |
| 22 | extern unsigned int ddr_init_tab[]; |
| 23 | #ifdef DDR2_SUPPORT |
| 24 | extern unsigned int ddr2_init_tab[]; |
| 25 | extern unsigned int ddr2_init_tab_400[]; |
| 26 | extern unsigned int ddr2_init_tab_667[]; |
| 27 | extern unsigned int ddr2_init_tab_800[]; |
| 28 | extern unsigned int ddr2_init_tab_1066[]; |
| 29 | extern unsigned int ddr2_mode_reg_tab[]; |
| 30 | #endif |
| 31 | |
| 32 | #ifdef CONFIG_DDR333 |
| 33 | #define CONFIG_DRAM_FREQ 333 |
| 34 | extern unsigned int ddr3_init_tab_667[]; |
| 35 | #endif |
| 36 | #ifdef CONFIG_DDR400 |
| 37 | #define CONFIG_DRAM_FREQ 400 |
| 38 | extern unsigned int ddr3_init_tab_800[]; |
| 39 | #endif |
| 40 | #ifdef CONFIG_DDR533 |
| 41 | #define CONFIG_DRAM_FREQ 533 |
| 42 | extern unsigned int ddr3_init_tab_1066[]; |
| 43 | #endif |
| 44 | #ifdef CONFIG_DDR667 |
| 45 | #define CONFIG_DRAM_FREQ 667 |
| 46 | extern unsigned int ddr3_init_tab_1333[]; |
| 47 | #endif |
Martin Roth | c4e49f6 | 2015-07-11 13:42:54 -0600 | [diff] [blame] | 48 | #if IS_ENABLED(CONFIG_CYGNUS_DDR800) |
Icarus Chau | d5f551a | 2015-02-13 15:16:37 -0800 | [diff] [blame] | 49 | #define CONFIG_DRAM_FREQ 800 |
| 50 | extern unsigned int ddr3_init_tab_1600[]; |
| 51 | #endif |
| 52 | |
| 53 | #define __udelay udelay |
| 54 | |
| 55 | /* Local function prototype */ |
| 56 | uint32_t change_ddr_clock(uint32_t clk); |
| 57 | void dump_phy_regs(void); |
| 58 | void ddr_init_regs(unsigned int * tblptr); |
| 59 | void ddr_phy_ctl_regs_ovrd(unsigned int * tblptr); |
| 60 | void ddr_phy_wl_regs_ovrd(unsigned int * tblptr); |
| 61 | int is_ddr_32bit(void); |
| 62 | uint32_t iproc_get_ddr3_clock_mhz(uint32_t unit); |
| 63 | int cygnus_phy_powerup(void); |
| 64 | void ddr_init2(void); |
| 65 | void PRE_SRX(void); |
| 66 | |
Martin Roth | c4e49f6 | 2015-07-11 13:42:54 -0600 | [diff] [blame] | 67 | #if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) |
Icarus Chau | d5f551a | 2015-02-13 15:16:37 -0800 | [diff] [blame] | 68 | void PRE_SRX(void) |
| 69 | { |
| 70 | uint32_t readvalue = 0; |
| 71 | |
| 72 | // Disable low power receivers: bit 0 of the byte lane STATIC_PAD_CTL register |
| 73 | readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL); |
| 74 | reg32_write ((volatile uint32_t *)DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL, ( readvalue & ~(1 << DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RX_MODE_R))); |
| 75 | |
| 76 | // Turn off ZQ_CAL drivers: bits 0,1, and 17 of the ZQ_CAL register (other bits 0 & 1 are set to 1) |
| 77 | readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_CONTROL_REGS_ZQ_CAL); |
| 78 | reg32_write ((volatile uint32_t *)DDR_PHY_CONTROL_REGS_ZQ_CAL, ( readvalue & ~(1 << DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_IDDQ))); |
| 79 | |
| 80 | // Byte lane 0 power up |
| 81 | readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); |
| 82 | reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, ( readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDLE))); |
| 83 | |
| 84 | readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); |
| 85 | reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, ( readvalue & 0xffff800f)); |
| 86 | |
| 87 | readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); |
| 88 | reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, ( readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDDQ))); |
| 89 | |
| 90 | // Byte lane 1 power up |
| 91 | readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); |
| 92 | reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, ( readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDLE))); |
| 93 | |
| 94 | readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); |
| 95 | reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, ( readvalue & 0xffff800f)); |
| 96 | |
| 97 | readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); |
| 98 | reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, ( readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDDQ))); |
| 99 | |
| 100 | // Turn on PHY_CONTROL AUTO_OEB ¨C not required |
| 101 | // Enable byte lane AUTO_DQ_RXENB_MODE: bits 18 and 19 of the byte lane IDLE_PAD_CONTROL ¨C already set 180114c8: 000f000a |
| 102 | |
| 103 | printk(BIOS_INFO, "\n....PLL power up.\n"); |
| 104 | reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG, (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & ~(1<<DDR_PHY_CONTROL_REGS_PLL_CONFIG__PWRDN))); |
| 105 | |
| 106 | // PLL out of reset |
| 107 | reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG, (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & ~(1<<DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESET))); |
| 108 | printk(BIOS_INFO, "\n....poll lock..\n"); |
| 109 | // Poll lock |
| 110 | readvalue = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_STATUS); |
| 111 | while ( ( readvalue & 0x1) == 0x0 ) |
| 112 | { |
| 113 | printk(BIOS_INFO, "\n....DDR_PHY_CONTROL_REGS_PLL_STATUS = %8x..\n",readvalue); |
| 114 | readvalue = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_STATUS); |
| 115 | } |
| 116 | printk(BIOS_INFO, "\n....after while..\n"); |
| 117 | |
| 118 | reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG, (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & ~(1<<DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESET_POST_DIV))); |
| 119 | |
| 120 | printk(BIOS_INFO, "\n....remove hold..\n"); |
| 121 | // Remove hold |
| 122 | reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG, (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & ~(1<<DDR_PHY_CONTROL_REGS_PLL_CONFIG__HOLD))); |
| 123 | printk(BIOS_INFO, "\n....restore dac..\n"); |
| 124 | |
| 125 | // Restore DAC |
| 126 | reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL, (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL) & 0xffff0fff)); |
| 127 | printk(BIOS_INFO, "\n....set iddq bit..\n"); |
| 128 | |
| 129 | // Set the iddq bit in the idle control register and select all outputs except cke and rst in the idee select registers. |
| 130 | // Do NOT assert any other bits in the idle control register. (This step can be done during init on power up.) |
| 131 | reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL, (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL) & ~(1 << DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__IDDQ))); |
| 132 | printk(BIOS_INFO, "\n....idle pad enable 0..\n"); |
| 133 | reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0, 0x0); |
| 134 | reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1, 0x0); |
| 135 | printk(BIOS_INFO, "\n....DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL..\n"); |
| 136 | reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL, (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL) & ~(1 << DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__IDLE))); |
| 137 | } |
| 138 | |
| 139 | #endif |
| 140 | |
| 141 | #if defined(CONFIG_IPROC_DDR_ECC) && !defined(CONFIG_IPROC_P7) |
| 142 | void iproc_ddr_ovrd_ecc_lane(void) |
| 143 | { |
| 144 | uint32_t val; |
| 145 | |
| 146 | #define SET_OVR_STEP(v) ( 0x30000 | ( (v) & 0x3F ) ) /* OVR_FORCE = OVR_EN = 1, OVR_STEP = v */ |
| 147 | |
| 148 | val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN); |
| 149 | val = SET_OVR_STEP(val & 0xff); |
| 150 | reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_RD_EN, val); |
| 151 | val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION); |
| 152 | |
| 153 | val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W); |
| 154 | val = SET_OVR_STEP(val & 0xff); |
| 155 | reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_W, val); |
| 156 | val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION); |
| 157 | |
| 158 | val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P); |
| 159 | val = SET_OVR_STEP(val & 0xff); |
| 160 | reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_R_P, val); |
| 161 | val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION); |
| 162 | |
| 163 | val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N); |
| 164 | val = SET_OVR_STEP(val & 0xff); |
| 165 | reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_R_N, val); |
| 166 | val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION); |
| 167 | |
| 168 | val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W); |
| 169 | val = SET_OVR_STEP(val & 0xff); |
| 170 | reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT0_W, val); |
| 171 | val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION); |
| 172 | |
| 173 | val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W); |
| 174 | val = SET_OVR_STEP(val & 0xff); |
| 175 | reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT1_W, val); |
| 176 | val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION); |
| 177 | |
| 178 | val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W); |
| 179 | val = SET_OVR_STEP(val & 0xff); |
| 180 | reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT2_W, val); |
| 181 | val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION); |
| 182 | |
| 183 | val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W); |
| 184 | val = SET_OVR_STEP(val & 0xff); |
| 185 | reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT3_W, val); |
| 186 | val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION); |
| 187 | |
| 188 | val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W); |
| 189 | val = SET_OVR_STEP(val & 0xff); |
| 190 | reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_DM_W, val); |
| 191 | val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION); |
| 192 | |
| 193 | val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P); |
| 194 | val = SET_OVR_STEP(val & 0xff); |
| 195 | reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT0_R_P, val); |
| 196 | val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION); |
| 197 | |
| 198 | val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N); |
| 199 | val = SET_OVR_STEP(val & 0xff); |
| 200 | reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT0_R_N, val); |
| 201 | val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION); |
| 202 | |
| 203 | val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P); |
| 204 | val = SET_OVR_STEP(val & 0xff); |
| 205 | reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT1_R_P, val); |
| 206 | val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION); |
| 207 | |
| 208 | val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N); |
| 209 | val = SET_OVR_STEP(val & 0xff); |
| 210 | reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT1_R_N, val); |
| 211 | val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION); |
| 212 | |
| 213 | val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P); |
| 214 | val = SET_OVR_STEP(val & 0xff); |
| 215 | reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT2_R_P, val); |
| 216 | val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION); |
| 217 | |
| 218 | val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N); |
| 219 | val = SET_OVR_STEP(val & 0xff); |
| 220 | reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT2_R_N, val); |
| 221 | val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION); |
| 222 | |
| 223 | val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P); |
| 224 | val = SET_OVR_STEP(val & 0xff); |
| 225 | reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT3_R_P, val); |
| 226 | val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION); |
| 227 | |
| 228 | val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N); |
| 229 | val = SET_OVR_STEP(val & 0xff); |
| 230 | reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT3_R_N, val); |
| 231 | val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION); |
| 232 | |
| 233 | |
| 234 | val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN); |
| 235 | val = SET_OVR_STEP(val & 0xff); |
| 236 | reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT_RD_EN, val); |
| 237 | val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION); |
| 238 | |
| 239 | val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_READ_DATA_DLY); |
| 240 | reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_READ_DATA_DLY, val); |
| 241 | val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION); |
| 242 | |
| 243 | val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_READ_CONTROL); |
| 244 | reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_READ_CONTROL, val); |
| 245 | val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION); |
| 246 | |
| 247 | val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_IDLE_PAD_CONTROL); |
| 248 | reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_IDLE_PAD_CONTROL, val); |
| 249 | val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION); |
| 250 | |
| 251 | val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_DRIVE_PAD_CTL); |
| 252 | reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_DRIVE_PAD_CTL, val); |
| 253 | val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION); |
| 254 | |
| 255 | val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_WR_PREAMBLE_MODE); |
| 256 | reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_WR_PREAMBLE_MODE, val); |
| 257 | val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION); |
| 258 | |
| 259 | __udelay(200); |
| 260 | reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_READ_FIFO_CLEAR, 0x1); |
| 261 | val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION); |
| 262 | __udelay(200); |
| 263 | } |
| 264 | |
| 265 | uint32_t iproc_read_ecc_syndrome(void) |
| 266 | { |
| 267 | volatile uint32_t syndrome = 0; |
| 268 | /* Place uncorrectible as bits 7:0, and correctible as 15:8 */ |
| 269 | syndrome = ((reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) >> 3) & 0x1) | |
| 270 | (((reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) >> 5) & 0x1)); |
| 271 | return(syndrome); |
| 272 | } |
| 273 | |
| 274 | void iproc_clear_ecc_syndrome(void) |
| 275 | { |
| 276 | uint32_t val; |
| 277 | |
| 278 | /* Clear the interrupts, bits 6:3 */ |
| 279 | reg32_write((volatile uint32_t *)DDR_DENALI_CTL_213, (1 << 5) | (1<< 3)); |
| 280 | __udelay(1000); |
| 281 | } |
| 282 | #endif |
| 283 | |
Martin Roth | c4e49f6 | 2015-07-11 13:42:54 -0600 | [diff] [blame] | 284 | #if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) |
Icarus Chau | d5f551a | 2015-02-13 15:16:37 -0800 | [diff] [blame] | 285 | uint32_t iproc_get_ddr3_clock_mhz(uint32_t unit) |
| 286 | { |
| 287 | uint32_t ndiv, mdiv, pdiv, ddrclk, data; |
| 288 | |
| 289 | data = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_DIVIDERS); |
| 290 | |
| 291 | ndiv = data >> DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__NDIV_INT_R; |
| 292 | ndiv &= (2^DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__NDIV_INT_WIDTH) - 1; |
| 293 | |
| 294 | pdiv = data >> DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__PDIV_R; |
| 295 | pdiv &= (2^DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__PDIV_WIDTH) - 1; |
| 296 | |
| 297 | mdiv = data >> DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__MDIV_R; |
| 298 | mdiv &= (2^DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__MDIV_WIDTH) - 1; |
| 299 | |
| 300 | /* read ndiv pdiv and mdiv */ |
| 301 | ddrclk = (25 * ndiv * 2 * pdiv) / mdiv; |
| 302 | printk(BIOS_INFO, "%s DDR PHY PLL divisor: ndiv(0x%x) mdiv(0x%x) ddrclk(0x%x)\n", __FUNCTION__, ndiv, mdiv, ddrclk); |
| 303 | |
| 304 | return(ddrclk); |
| 305 | } |
| 306 | |
| 307 | #endif |
| 308 | |
Martin Roth | c4e49f6 | 2015-07-11 13:42:54 -0600 | [diff] [blame] | 309 | #if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) |
Icarus Chau | d5f551a | 2015-02-13 15:16:37 -0800 | [diff] [blame] | 310 | |
| 311 | int cygnus_phy_powerup(void) |
| 312 | { |
| 313 | int data; |
| 314 | int count = 15; |
| 315 | |
| 316 | data = reg32_read((volatile uint32_t *)CRMU_DDR_PHY_AON_CTRL); |
| 317 | |
| 318 | if(reg32_read((volatile uint32_t *)CRMU_IHOST_POR_WAKEUP_FLAG)==0) |
| 319 | { |
| 320 | /* Step 1: POWRON */ |
| 321 | data = reg32_read((volatile uint32_t *)CRMU_DDR_PHY_AON_CTRL); |
| 322 | data |= 0x8;// assert power ON |
| 323 | reg32_write((volatile uint32_t *)CRMU_DDR_PHY_AON_CTRL, data); |
| 324 | |
| 325 | __udelay(2); |
| 326 | |
| 327 | /* Step 2: POWROK */ |
| 328 | data |= 0x10;// assert power OK |
| 329 | reg32_write((volatile uint32_t *)CRMU_DDR_PHY_AON_CTRL, data); |
| 330 | |
| 331 | while(count--) |
| 332 | __udelay(2); |
| 333 | |
| 334 | } |
| 335 | else |
| 336 | { |
| 337 | printk(BIOS_INFO, "DeepSleep wakeup: ddr phy init bypassed 1\n"); |
| 338 | } |
| 339 | |
| 340 | /* Step 3: DFI normal mode */ |
| 341 | data &= ~(0x04);// remove DFI isolation |
| 342 | reg32_write((volatile uint32_t *)CRMU_DDR_PHY_AON_CTRL, data); |
| 343 | |
| 344 | |
| 345 | /* Step 4: Enable register access */ |
| 346 | data &= ~(0x02);// remove PHY register isolation |
| 347 | reg32_write((volatile uint32_t *)CRMU_DDR_PHY_AON_CTRL, data); |
| 348 | |
| 349 | data &= ~(0x01);// remove PLL isolation |
| 350 | reg32_write((volatile uint32_t *)CRMU_DDR_PHY_AON_CTRL, data); |
| 351 | |
| 352 | count = 20; |
| 353 | while(count--) |
| 354 | __udelay(2); |
| 355 | |
| 356 | if(reg32_read((volatile uint32_t *)CRMU_IHOST_POR_WAKEUP_FLAG)==0) |
| 357 | { |
| 358 | /* Step 5: release reset */ |
| 359 | data |= 0x20;// de-assert reset |
| 360 | reg32_write((volatile uint32_t *)CRMU_DDR_PHY_AON_CTRL, data); |
| 361 | } |
| 362 | else |
| 363 | { |
| 364 | printk(BIOS_INFO, "DeepSleep wakeup: ddr phy init bypassed 2\n"); |
| 365 | } |
| 366 | while((reg32_read((volatile uint32_t *)DDR_S1_IDM_IO_STATUS) & 0x08) != 0x08) { |
| 367 | //poll DDR_S1_IDM_IO_STATUS__o_phy_pwrup_rsb |
| 368 | } |
| 369 | |
| 370 | return 0; |
| 371 | } |
| 372 | |
| 373 | #endif |
| 374 | |
| 375 | uint32_t change_ddr_clock(uint32_t clk) |
| 376 | { |
| 377 | return(0); |
| 378 | } |
| 379 | |
| 380 | void dump_phy_regs(void) |
| 381 | { |
| 382 | int i; |
| 383 | printk(BIOS_DEBUG, "\n PHY register dump: Control registers\n"); |
| 384 | for(i = 0; i <= 0x94; i+=4) |
| 385 | { |
| 386 | printk(BIOS_DEBUG, "0x%03x,\t0x%08x,\n", i, |
| 387 | *(volatile uint32_t *)(DDR_PHY_CONTROL_REGS_REVISION + i)); |
| 388 | } |
| 389 | |
| 390 | printk(BIOS_DEBUG, "\n PHY register dump: Wordlane0 registers\n"); |
| 391 | for(i = 0; i <= 0xc5; i+=4) |
| 392 | { |
| 393 | printk(BIOS_DEBUG, "0x%03x,\t0x%08x,\n", i, |
| 394 | *(volatile uint32_t *)(DDR_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P + i)); |
| 395 | } |
| 396 | |
| 397 | return; |
| 398 | } |
| 399 | |
| 400 | void ddr_init_regs(unsigned int * tblptr) |
| 401 | { |
| 402 | unsigned int offset = *tblptr; |
| 403 | unsigned int *addr = (unsigned int *)DDR_DENALI_CTL_00; |
| 404 | |
| 405 | while(offset != 0xffffffff) { |
| 406 | ++tblptr; |
| 407 | #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ |
| 408 | addr[offset] = *tblptr; |
| 409 | #else |
| 410 | addr[offset] = swap_u32(*tblptr); |
| 411 | #endif |
| 412 | ++tblptr; |
| 413 | offset = *tblptr; |
| 414 | } |
| 415 | } |
| 416 | |
| 417 | void ddr_phy_ctl_regs_ovrd(unsigned int * tblptr) |
| 418 | { |
| 419 | unsigned int offset = *tblptr; |
| 420 | unsigned int *addr = (unsigned int *)DDR_PHY_CONTROL_REGS_REVISION; |
| 421 | unsigned int val; |
| 422 | |
| 423 | while(offset != 0xffffffff) { |
| 424 | ++tblptr; |
| 425 | #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ |
| 426 | addr[offset/4] = *tblptr; |
| 427 | #else |
| 428 | addr[offset/4] = swap_u32(*tblptr); |
| 429 | #endif |
| 430 | val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION); |
| 431 | if (val) ; |
| 432 | ++tblptr; |
| 433 | offset = *tblptr; |
| 434 | } |
| 435 | } |
| 436 | |
| 437 | void ddr_phy_wl_regs_ovrd(unsigned int * tblptr) |
| 438 | { |
| 439 | } |
| 440 | |
| 441 | /*DDR_SHMOO_RELATED_CHANGE*/ |
| 442 | |
| 443 | #ifdef CONFIG_RUN_DDR_SHMOO |
| 444 | int ReWriteModeRegisters( void ) |
| 445 | { |
| 446 | int nRet = 0; |
| 447 | int j = 100; |
| 448 | |
| 449 | reg32_clear_bits( (volatile uint32_t *)DDR_DENALI_CTL_89 , 1 << 18 ); |
| 450 | |
| 451 | /* Set mode register for MR0, MR1, MR2 and MR3 write for all chip selects */ |
| 452 | reg32_write( (volatile uint32_t *)DDR_DENALI_CTL_43 , (1 << 17) | (1 << 24) | (1 << 25) ); |
| 453 | |
| 454 | /* Trigger Mode Register Write(MRW) sequence */ |
| 455 | reg32_set_bits( (volatile uint32_t *)DDR_DENALI_CTL_43 , 1 << 25 ); |
| 456 | |
| 457 | do { |
| 458 | if ( reg32_read( (volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18) ) { |
| 459 | break; |
| 460 | } |
| 461 | --j; |
| 462 | } while( j ); |
| 463 | |
| 464 | if ( j == 0 && (reg32_read( (volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18) ) == 0 ) { |
| 465 | printk(BIOS_ERR, "Error: DRAM mode registers write failed\n"); |
| 466 | nRet = 1; |
| 467 | }; |
| 468 | |
| 469 | return nRet; |
| 470 | } |
| 471 | #endif /* CONFIG_RUN_DDR_SHMOO */ |
| 472 | |
| 473 | |
| 474 | int is_ddr_32bit(void) |
| 475 | { |
| 476 | int ddr32 = 0; |
| 477 | |
| 478 | #if (CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT) |
| 479 | ddr32=1; |
| 480 | #endif /* (CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT) */ |
| 481 | |
| 482 | return ddr32; |
| 483 | } |
| 484 | |
| 485 | |
| 486 | static uint32_t get_ddr_clock(uint32_t sku_id, int ddr_type) |
| 487 | { |
| 488 | #ifdef CONFIG_DRAM_FREQ |
| 489 | return CONFIG_DRAM_FREQ; |
| 490 | #else |
| 491 | #error Please set DDR frequency (CONFIG_DRAM_FREQ must be set) |
| 492 | #endif |
| 493 | } |
| 494 | |
| 495 | #if defined(CONFIG_SHMOO_REUSE) || defined(CONFIG_SHMOO_AND28_REUSE) |
| 496 | |
| 497 | #define RAND_MAGIC_1 0x0000444BUL |
| 498 | #define RAND_MAGIC_2 0x88740000UL |
| 499 | #define RAND_MAGIC_3 69069UL |
| 500 | #define RAND_SEED 0x5301beef |
| 501 | #define RAND_SEED_2 ((RAND_SEED << 21) + (RAND_SEED << 14) + (RAND_SEED << 7)) |
| 502 | #define RAND_C_INIT (((RAND_SEED_2 + RAND_MAGIC_1) << 1) + 1) |
| 503 | #define RAND_T_INIT ((RAND_SEED_2 << (RAND_SEED_2 & 0xF)) + RAND_MAGIC_2) |
| 504 | |
| 505 | static int simple_memory_test(void *start, uint32_t len) |
| 506 | { |
| 507 | register uint32_t rand_c_value, rand_t_value, rand_value; |
| 508 | register uint32_t i; |
| 509 | register volatile uint32_t *paddr; |
| 510 | |
| 511 | len /= 4; |
| 512 | paddr = (volatile uint32_t *)start; |
| 513 | rand_c_value = RAND_C_INIT; |
| 514 | rand_t_value = RAND_T_INIT; |
| 515 | for(i=0; i<len; i++, paddr++) { |
| 516 | rand_c_value *= RAND_MAGIC_3; |
| 517 | rand_t_value ^= rand_t_value >> 15; |
| 518 | rand_t_value ^= rand_t_value << 17; |
| 519 | rand_value = rand_t_value ^ rand_c_value; |
| 520 | *paddr = rand_value; |
| 521 | } |
| 522 | |
| 523 | paddr = (volatile uint32_t *)start; |
| 524 | rand_c_value = RAND_C_INIT; |
| 525 | rand_t_value = RAND_T_INIT; |
| 526 | for(i=0; i<len; i++, paddr++) { |
| 527 | rand_c_value *= RAND_MAGIC_3; |
| 528 | rand_t_value ^= rand_t_value >> 15; |
| 529 | rand_t_value ^= rand_t_value << 17; |
| 530 | rand_value = rand_t_value ^ rand_c_value; |
| 531 | if (*paddr != rand_value) { |
| 532 | return -1; |
| 533 | } |
| 534 | } |
| 535 | |
| 536 | return 0; |
| 537 | } |
| 538 | |
| 539 | #endif /* CONFIG_SHMOO_REUSE || CONFIG_SHMOO_AND28_REUSE */ |
| 540 | |
| 541 | #if defined(CONFIG_RUN_DDR_SHMOO2) && defined(CONFIG_SHMOO_REUSE) |
| 542 | |
| 543 | #define SHMOO_HEADER_MAGIC "SHMO" |
| 544 | #define SHMOO_MIN_BLOCK_SIZE 0x10000 |
| 545 | |
| 546 | static const uint16_t ddr_phy_ctl_regs[] = { |
| 547 | 0x030, |
| 548 | 0x034, |
| 549 | 0x06c |
| 550 | }; |
| 551 | |
| 552 | static const uint16_t ddr_phy_wl_regs[] = { |
| 553 | 0x000, |
| 554 | 0x004, |
| 555 | 0x008, |
| 556 | 0x00c, |
| 557 | 0x010, |
| 558 | 0x014, |
| 559 | 0x018, |
| 560 | 0x01c, |
| 561 | 0x020, |
| 562 | 0x024, |
| 563 | 0x028, |
| 564 | 0x02c, |
| 565 | 0x030, |
| 566 | 0x034, |
| 567 | 0x038, |
| 568 | 0x03c, |
| 569 | 0x040, |
| 570 | 0x044, |
| 571 | 0x048, |
| 572 | 0x04c, |
| 573 | 0x050, |
| 574 | 0x054, |
| 575 | 0x058, |
| 576 | 0x05c, |
| 577 | 0x060, |
| 578 | 0x064, |
| 579 | 0x068, |
| 580 | 0x06c, |
| 581 | 0x070, |
| 582 | 0x074, |
| 583 | 0x0a4, |
| 584 | 0x0a8, |
| 585 | 0x0ac, |
| 586 | 0x0b0, |
| 587 | 0x0b4, |
| 588 | 0x0b8, |
| 589 | 0x0bc, |
| 590 | 0x0c0, |
| 591 | 0x0c4, |
| 592 | 0x0c8, |
| 593 | 0x0cc, |
| 594 | 0x0d0, |
| 595 | 0x0d4, |
| 596 | 0x0d8, |
| 597 | 0x0dc, |
| 598 | 0x0e0, |
| 599 | 0x0e4, |
| 600 | 0x0e8, |
| 601 | 0x0ec, |
| 602 | 0x0f0, |
| 603 | 0x0f4, |
| 604 | 0x0f8, |
| 605 | 0x0fc, |
| 606 | 0x100, |
| 607 | 0x104, |
| 608 | 0x108, |
| 609 | 0x10c, |
| 610 | 0x110, |
| 611 | 0x114, |
| 612 | 0x118, |
| 613 | 0x11c, |
| 614 | 0x120, |
| 615 | 0x124, |
| 616 | 0x128, |
| 617 | 0x12c, |
| 618 | 0x130, |
| 619 | 0x134, |
| 620 | 0x138, |
| 621 | 0x13c, |
| 622 | 0x140, |
| 623 | 0x144, |
| 624 | 0x148, |
| 625 | 0x14c, |
| 626 | 0x150, |
| 627 | 0x154, |
| 628 | 0x158, |
| 629 | 0x15c, |
| 630 | 0x160, |
| 631 | 0x164, |
| 632 | 0x168, |
| 633 | 0x16c, |
| 634 | 0x1a0, |
| 635 | 0x1a4, |
| 636 | 0x1a8, |
| 637 | 0x1ac, |
| 638 | 0x1b0 |
| 639 | }; |
| 640 | #if defined(CONFIG_IPROC_DDR_ECC) && !defined(CONFIG_IPROC_P7) |
| 641 | static const uint16_t ddr_phy_eccl_regs[] = { |
| 642 | DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_RD_EN_BASE, |
| 643 | DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_W_BASE, |
| 644 | DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_R_P_BASE, |
| 645 | DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_R_N_BASE, |
| 646 | DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT0_W_BASE, |
| 647 | DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT1_W_BASE, |
| 648 | DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT2_W_BASE, |
| 649 | DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT3_W_BASE, |
| 650 | DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_DM_W_BASE, |
| 651 | DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT0_R_P_BASE, |
| 652 | DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT0_R_N_BASE, |
| 653 | DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT1_R_P_BASE, |
| 654 | DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT1_R_N_BASE, |
| 655 | DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT2_R_P_BASE, |
| 656 | DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT2_R_N_BASE, |
| 657 | DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT3_R_P_BASE, |
| 658 | DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT3_R_N_BASE, |
| 659 | DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT_RD_EN_BASE, |
| 660 | DDR_PHY_ECC_LANE_READ_DATA_DLY_BASE, |
| 661 | DDR_PHY_ECC_LANE_READ_CONTROL_BASE, |
| 662 | DDR_PHY_ECC_LANE_IDLE_PAD_CONTROL_BASE, |
| 663 | DDR_PHY_ECC_LANE_DRIVE_PAD_CTL_BASE, |
| 664 | DDR_PHY_ECC_LANE_WR_PREAMBLE_MODE_BASE, |
| 665 | }; |
| 666 | #endif |
| 667 | #if defined(CONFIG_IPROC_NAND) && defined(CONFIG_ENV_IS_IN_NAND) && CONFIG_ENV_IS_IN_NAND |
| 668 | |
| 669 | static int write_shmoo_to_flash(void *buf, int length) |
| 670 | { |
| 671 | nand_info_t *nand; |
| 672 | int ret = 0; |
| 673 | uint32_t offset = CONFIG_SHMOO_REUSE_NAND_OFFSET; |
| 674 | uint32_t end = offset + CONFIG_SHMOO_REUSE_NAND_RANGE; |
| 675 | uint32_t blksize; |
| 676 | |
| 677 | /* Get flash handle */ |
| 678 | nand = &nand_info[0]; |
| 679 | if (nand->size < offset || nand->writesize == 0 || nand->erasesize == 0) { |
| 680 | printk(BIOS_ERR, "Failed to initialize NAND flash for saving Shmoo values!\n"); |
| 681 | return -1; |
| 682 | } |
| 683 | |
| 684 | /* For NAND with bad blocks, we always erase all blocks in the range */ |
| 685 | { |
| 686 | nand_erase_options_t opts; |
| 687 | memset(&opts, 0, sizeof(opts)); |
| 688 | opts.offset = offset / nand->erasesize * nand->erasesize; |
| 689 | opts.length = (CONFIG_SHMOO_REUSE_NAND_RANGE - 1) / nand->erasesize * nand->erasesize + 1; |
| 690 | opts.quiet = 1; |
| 691 | ret = nand_erase_opts(nand, &opts); |
| 692 | if (ret) { |
| 693 | printk(BIOS_ERR, "NAND flash erase failed, error=%d\n", ret); |
| 694 | return ret; |
| 695 | } |
| 696 | } |
| 697 | |
| 698 | /* Write data */ |
| 699 | blksize = nand->erasesize > SHMOO_MIN_BLOCK_SIZE? |
| 700 | nand->erasesize : SHMOO_MIN_BLOCK_SIZE; |
| 701 | while (offset < end) { |
| 702 | if (nand_block_isbad(nand, offset)) { |
| 703 | offset += blksize; |
| 704 | continue; |
| 705 | } |
| 706 | ret = nand_write(nand, offset, (size_t *)&length, (u_char *)buf); |
| 707 | if (ret) { |
| 708 | printk(BIOS_ERR, "NAND flash write failed, error=%d\n", ret); |
| 709 | } |
| 710 | break; |
| 711 | } |
| 712 | |
| 713 | return ret; |
| 714 | } |
| 715 | |
| 716 | #elif defined (CONFIG_SPI_FLASH) && defined(CONFIG_ENV_IS_IN_SPI_FLASH) && CONFIG_ENV_IS_IN_SPI_FLASH |
| 717 | |
| 718 | static int write_shmoo_to_flash(void *buf, int length) |
| 719 | { |
| 720 | struct spi_flash *flash; |
| 721 | int erase = 0; |
| 722 | volatile uint32_t *flptr; |
| 723 | int i, j, ret = 0; |
| 724 | uint32_t offset = CONFIG_SHMOO_REUSE_QSPI_OFFSET; |
| 725 | |
| 726 | /* Check if erasing is required */ |
| 727 | flptr = (volatile uint32_t *)(IPROC_QSPI_MEM_BASE + offset / 4 * 4); |
| 728 | j = (length - 1) / 4 + 1; |
| 729 | for(i=0; i<j; i++, flptr++) { |
| 730 | if (*flptr != 0xFFFFFFFF) { |
| 731 | erase = 1; |
| 732 | break; |
| 733 | } |
| 734 | } |
| 735 | |
| 736 | /* Probe flash */ |
| 737 | flash = spi_flash_probe( |
| 738 | CONFIG_ENV_SPI_BUS, |
| 739 | CONFIG_ENV_SPI_CS, |
| 740 | CONFIG_ENV_SPI_MAX_HZ, |
| 741 | CONFIG_ENV_SPI_MODE |
| 742 | ); |
| 743 | if (!flash) { |
| 744 | printk(BIOS_ERR, "Failed to initialize SPI flash for saving Shmoo values!\n"); |
| 745 | return -1; |
| 746 | } |
| 747 | |
| 748 | /* Erase if necessary */ |
| 749 | if (erase) { |
| 750 | ret = spi_flash_erase( |
| 751 | flash, |
| 752 | offset / flash->sector_size * flash->sector_size, |
| 753 | flash->sector_size |
| 754 | ); |
| 755 | if (ret) { |
| 756 | printk(BIOS_ERR, "SPI flash erase failed, error=%d\n", ret); |
| 757 | spi_flash_free(flash); |
| 758 | return ret; |
| 759 | } |
| 760 | } |
| 761 | |
| 762 | /* Write data */ |
| 763 | ret = spi_flash_write(flash, offset, length, buf); |
| 764 | if (ret) { |
| 765 | printk(BIOS_ERR, "SPI flash write failed, error=%d\n", ret); |
| 766 | } |
| 767 | |
| 768 | /* Free flash instance */ |
| 769 | spi_flash_free(flash); |
| 770 | |
| 771 | return ret; |
| 772 | } |
| 773 | |
| 774 | #elif defined (CONFIG_ENV_IS_IN_FLASH) |
| 775 | |
| 776 | static int write_shmoo_to_flash(void *buf, int length) |
| 777 | { |
| 778 | int erase = 0; |
| 779 | volatile uint32_t *flptr, shmoo_start; |
| 780 | int i, j, ret = 0; |
| 781 | uint32_t offset = CONFIG_SHMOO_REUSE_NOR_OFFSET; |
| 782 | int sect_len; |
| 783 | |
| 784 | /* Check if erasing is required */ |
| 785 | flptr = (volatile uint32_t *)(IPROC_NOR_MEM_BASE + offset / 4 * 4); |
| 786 | shmoo_start = flptr; |
| 787 | j = (length - 1) / 4 + 1; |
| 788 | for(i=0; i<j; i++, flptr++) { |
| 789 | if (*flptr != 0xFFFFFFFF) { |
| 790 | erase = 1; |
| 791 | break; |
| 792 | } |
| 793 | } |
| 794 | |
| 795 | sect_len = (((length / 0x20000) + 1)*0x20000 - 1); |
| 796 | /* Erase if necessary */ |
| 797 | if (erase) { |
| 798 | ret = flash_sect_erase((ulong)shmoo_start, (ulong)shmoo_start + sect_len); |
| 799 | if (ret) { |
| 800 | printk(BIOS_ERR, "NOR flash erase failed, error=%d, start addr: 0x%x, end addr: 0x%x\n", |
| 801 | ret, (ulong)shmoo_start, (ulong)shmoo_start + sect_len); |
| 802 | return ret; |
| 803 | } |
| 804 | } |
| 805 | |
| 806 | /* Write data */ |
| 807 | ret = flash_write((char *)buf, (ulong)shmoo_start, length); |
| 808 | |
| 809 | if (ret) { |
| 810 | printk(BIOS_ERR, "NOR flash write failed, error=%d\n", ret); |
| 811 | } |
| 812 | |
| 813 | |
| 814 | return ret; |
| 815 | |
| 816 | } |
| 817 | #else |
| 818 | #error Flash (SPI or NAND) must be enabled |
| 819 | #endif |
| 820 | |
| 821 | /* Return flash pointer; or NULL if validation failed */ |
| 822 | static volatile uint32_t *validate_flash_shmoo_values(struct shmoo_signature *psig, int *ppairs) |
| 823 | { |
| 824 | uint32_t dev_id, sku_id, ddr_type, ddr_clk; |
| 825 | volatile uint32_t *ptr; |
| 826 | volatile uint32_t *flptr; |
| 827 | struct shmoo_signature sig; |
| 828 | uint32_t checksum, pairs, length; |
| 829 | uint32_t chksum; |
| 830 | int offset; |
| 831 | int i; |
| 832 | int numpairs = 1; |
| 833 | |
| 834 | if (is_ddr_32bit()) { |
| 835 | numpairs = 2; |
| 836 | } |
| 837 | |
| 838 | /* Calculate required length (register/value pair) */ |
| 839 | pairs = |
| 840 | sizeof(ddr_phy_ctl_regs) / sizeof(ddr_phy_ctl_regs[0]) + |
| 841 | sizeof(ddr_phy_wl_regs) / sizeof(ddr_phy_wl_regs[0]) * numpairs; |
| 842 | #ifdef CONFIG_IPROC_DDR_ECC |
| 843 | pairs += sizeof(ddr_phy_eccl_regs) / sizeof(ddr_phy_eccl_regs[0]); |
| 844 | #endif |
| 845 | |
| 846 | if (ppairs != NULL) { |
| 847 | *ppairs = pairs; |
| 848 | } |
| 849 | |
| 850 | #if defined(CONFIG_ENV_IS_IN_NAND) && CONFIG_ENV_IS_IN_NAND |
| 851 | /* Read SHMOO data from NAND */ |
| 852 | flptr = (volatile uint32_t *)(IPROC_NAND_MEM_BASE + CONFIG_SHMOO_REUSE_NAND_OFFSET); |
| 853 | offset = (CONFIG_SHMOO_REUSE_NAND_RANGE - 1) / SHMOO_MIN_BLOCK_SIZE * SHMOO_MIN_BLOCK_SIZE; |
| 854 | #elif defined (CONFIG_ENV_IS_IN_FLASH) |
| 855 | /* Read SHMOO data from NOR */ |
| 856 | flptr = (volatile uint32_t *)(IPROC_NOR_MEM_BASE + CONFIG_SHMOO_REUSE_NOR_OFFSET); |
| 857 | offset = 0; |
| 858 | #else |
| 859 | /* Read SHMOO data from SPI */ |
| 860 | flptr = (volatile uint32_t *)(IPROC_QSPI_MEM_BASE + CONFIG_SHMOO_REUSE_QSPI_OFFSET); |
| 861 | offset = 0; |
| 862 | #endif |
| 863 | |
| 864 | /* Get chip type and DDR type/clock */ |
| 865 | dev_id = (reg32_read((volatile uint32_t *)ChipcommonA_ChipID)) & 0x0000ffff; |
| 866 | sku_id = (reg32_read((volatile uint32_t *)ROM_S0_IDM_IO_STATUS) >> 2) & 0x03; |
| 867 | ddr_type = reg32_read((volatile uint32_t *)DDR_S1_IDM_IO_STATUS) & 0x1; |
| 868 | ddr_clk = get_ddr_clock(sku_id, ddr_type); |
| 869 | |
| 870 | /* Construct signature */ |
| 871 | memcpy(sig.magic, SHMOO_HEADER_MAGIC, 4); |
| 872 | sig.dev_id = dev_id; |
| 873 | sig.sku_id = sku_id; |
| 874 | sig.ddr_type = ddr_type; |
| 875 | sig.ddr_clock = ddr_clk; |
| 876 | |
| 877 | /* Provide signature data to caller */ |
| 878 | if (psig) { |
| 879 | memcpy(psig, &sig, sizeof(sig)); |
| 880 | } |
| 881 | |
| 882 | /* Check signature (in min-blocks from bottom) */ |
| 883 | while (offset >= 0) { |
| 884 | ptr = flptr + offset; |
| 885 | if (!shmoo_sigmemcmp(&sig,(void *)ptr)) { |
| 886 | break; |
| 887 | } |
| 888 | offset -= SHMOO_MIN_BLOCK_SIZE; |
| 889 | } |
| 890 | if (offset < 0) { |
| 891 | printk(BIOS_ERR, " Signature mismatch "); |
| 892 | return NULL; |
| 893 | } |
| 894 | ptr += 3; |
| 895 | |
| 896 | /* Verify checksum */ |
| 897 | checksum = *ptr++; |
| 898 | length = *ptr++; |
| 899 | if (pairs != length) { |
| 900 | /* Pair count unmatched */ |
| 901 | printk(BIOS_ERR, " Pair count mismatch pairs %x length %x",pairs, length); |
| 902 | return NULL; |
| 903 | } |
| 904 | chksum = 0; |
| 905 | for(i=0; i<length * 2; i++, ptr++) { |
| 906 | chksum += *ptr; |
| 907 | } |
| 908 | if (chksum != checksum) { |
| 909 | printk(BIOS_ERR, " Checksum mismatch cksum: %x checksum:%x",chksum,checksum); |
| 910 | return NULL; |
| 911 | } |
| 912 | |
| 913 | return flptr + offset; |
| 914 | } |
| 915 | |
| 916 | static int try_restore_shmoo(void) |
| 917 | { |
| 918 | int invalid = 0; |
| 919 | struct shmoo_signature sig; |
| 920 | volatile uint32_t *flptr; |
| 921 | volatile uint32_t *reg; |
| 922 | uint32_t val; |
| 923 | int pairs, i; |
| 924 | |
| 925 | /* Validate values in flash */ |
| 926 | printk(BIOS_INFO, "Validate Shmoo parameters stored in flash ..... "); |
| 927 | flptr = validate_flash_shmoo_values(&sig, &pairs); |
| 928 | if (flptr == NULL) { |
| 929 | printk(BIOS_ERR, "failed\n"); |
| 930 | return 1; |
| 931 | } |
| 932 | printk(BIOS_INFO, "OK\n"); |
| 933 | |
| 934 | /* Check if user wants to skip restoring and run Shmoo */ |
| 935 | if (CONFIG_SHMOO_REUSE_DELAY_MSECS > 0) { |
| 936 | char c = 0; |
| 937 | unsigned long start; |
| 938 | printk(BIOS_INFO, "Press Ctrl-C to run Shmoo ..... "); |
| 939 | start = get_timer(0); |
| 940 | while(get_timer(start) <= CONFIG_SHMOO_REUSE_DELAY_MSECS) { |
| 941 | if (tstc()) { |
| 942 | c = getc(); |
| 943 | if (c == 0x03) { |
| 944 | printk(BIOS_INFO, "Pressed.\n"); |
| 945 | printk(BIOS_INFO, "Do you want to run the Shmoo? [y/N] "); |
| 946 | for(;;) { |
| 947 | c = getc(); |
| 948 | if (c == 'y' || c == 'Y') { |
| 949 | printk(BIOS_INFO, "Y\n"); |
| 950 | invalid = 1; |
| 951 | break; |
| 952 | } else if (c == '\r' || c == 'n' || c == 'N') { |
| 953 | if (c != '\r') |
| 954 | printk(BIOS_INFO, "N\n"); |
| 955 | break; |
| 956 | } |
| 957 | } |
| 958 | break; |
| 959 | } else { |
| 960 | c = 0; |
| 961 | } |
| 962 | } |
| 963 | } |
| 964 | if (c == 0) |
| 965 | printk(BIOS_INFO, "skipped\n"); |
| 966 | } |
| 967 | |
| 968 | if (invalid) { |
| 969 | return 1; |
| 970 | } |
| 971 | |
| 972 | /* Restore values from flash */ |
| 973 | printk(BIOS_INFO, "Restoring Shmoo parameters from flash ..... "); |
| 974 | flptr += 5; |
| 975 | for(i=0; i<pairs; i++) { |
| 976 | reg = (uint32_t *)(*flptr++); |
| 977 | val = (uint32_t *)(*flptr++); |
| 978 | if( (((uint32_t)reg >= DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN) && ((uint32_t)reg <= (DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN + 0x114))) |
| 979 | #if (CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT || defined(CONFIG_NS_PLUS)) |
| 980 | || (((uint32_t)reg >= DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN) && ((uint32_t)reg <= (DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN + 0x114))) |
| 981 | #endif |
| 982 | #ifdef CONFIG_IPROC_DDR_ECC |
| 983 | || (((uint32_t)reg >= (DDR_DENALI_CTL_00 + DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_RD_EN_BASE)) && ((uint32_t)reg <= (DDR_DENALI_CTL_00 + DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT_RD_EN_BASE))) |
| 984 | #endif |
| 985 | ) { |
| 986 | val |= (1 << 17); /* Force Override */ |
| 987 | } |
| 988 | // printk(BIOS_INFO, "Writing 0x%x to 0x%x\n",val,reg); |
| 989 | reg32_write(reg,val); |
| 990 | |
| 991 | reg32_read(reg); /* Dummy read back */ |
| 992 | } |
| 993 | printk(BIOS_INFO, "done\n"); |
| 994 | |
| 995 | /* Perform memory test to see if the parameters work */ |
| 996 | if (CONFIG_SHMOO_REUSE_MEMTEST_LENGTH > 0 ) { |
| 997 | printk(BIOS_INFO, "Running simple memory test ..... "); |
| 998 | i = simple_memory_test( |
| 999 | (void *)CONFIG_SHMOO_REUSE_MEMTEST_START, |
| 1000 | CONFIG_SHMOO_REUSE_MEMTEST_LENGTH); |
| 1001 | if (i) { |
| 1002 | printk(BIOS_ERR, "failed!\n"); |
| 1003 | return 1; |
| 1004 | } |
| 1005 | printk(BIOS_INFO, "OK\n"); |
| 1006 | } |
| 1007 | |
| 1008 | return 0; |
| 1009 | } |
| 1010 | |
| 1011 | #define SHMOO_REG_BUFFER_SIZE 100; |
| 1012 | static uint32_t shmoo_reg_buffer[SHMOO_REG_BUFFER_SIZE]; |
| 1013 | |
| 1014 | void iproc_save_shmoo_values(void) |
| 1015 | { |
| 1016 | uint32_t *buffer, *ptr; |
| 1017 | volatile uint32_t *flptr; |
| 1018 | uint32_t reg, val; |
| 1019 | struct shmoo_signature sig; |
| 1020 | int pairs, length; |
| 1021 | uint32_t chksum; |
| 1022 | int i; |
| 1023 | |
| 1024 | /* Check if flash already contains valid data */ |
| 1025 | flptr = validate_flash_shmoo_values(&sig, &pairs); |
| 1026 | if (flptr != NULL) { |
| 1027 | /* Check if the flash data are the same as current DDR PHY values */ |
| 1028 | flptr += 5; |
| 1029 | for(i=0; i<pairs; i++) { |
| 1030 | reg = *flptr++; |
| 1031 | val = *flptr++; |
| 1032 | if (val != reg32_read(reg)) { |
| 1033 | break; |
| 1034 | } |
| 1035 | |
| 1036 | } |
| 1037 | if (i == pairs) { |
| 1038 | /* No difference found; Saving skipped */ |
| 1039 | return; |
| 1040 | } |
| 1041 | } |
| 1042 | |
| 1043 | /* Calculate size of buffer */ |
| 1044 | length = 12 + |
| 1045 | sizeof(uint32_t) * 2 + |
| 1046 | sizeof(uint32_t) * pairs * 2; |
| 1047 | |
| 1048 | /* Allocate buffer */ |
| 1049 | if (length > size(uint32_t) * SHMOO_REG_BUFFER_SIZE) { |
| 1050 | printk(BIOS_INFO, "Error pre-allocated shmoo register buffer is not large enough!\n"); |
| 1051 | return; |
| 1052 | } |
| 1053 | |
| 1054 | buffer = shmoo_reg_buffer; |
| 1055 | ptr = buffer; |
| 1056 | |
| 1057 | /* Fill signature */ |
| 1058 | shmoo_sig2mem(&sig,ptr); |
| 1059 | ptr += 5; |
| 1060 | |
| 1061 | /* Copy registers and values to buffer */ |
| 1062 | chksum = 0; |
| 1063 | for(i=0; i<sizeof(ddr_phy_ctl_regs) / sizeof(ddr_phy_ctl_regs[0]); i++) { |
| 1064 | reg = (uint32_t)DDR_PHY_CONTROL_REGS_REVISION + ddr_phy_ctl_regs[i]; |
| 1065 | *ptr++ = reg; |
| 1066 | chksum += reg; |
| 1067 | // val = *(volatile uint32_t *)reg; |
| 1068 | val = reg32_read((volatile uint32_t *)reg); |
| 1069 | *ptr++ = val; |
| 1070 | chksum += val; |
| 1071 | } |
| 1072 | for(i=0; i<sizeof(ddr_phy_wl_regs) / sizeof(ddr_phy_wl_regs[0]); i++) { |
| 1073 | reg = (uint32_t)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN + ddr_phy_wl_regs[i]; |
| 1074 | *ptr++ = reg; |
| 1075 | chksum += reg; |
| 1076 | // val = *(volatile uint32_t *)reg; |
| 1077 | val = reg32_read((volatile uint32_t *)reg); |
| 1078 | *ptr++ = val; |
| 1079 | chksum += val; |
| 1080 | } |
| 1081 | #if (CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT || defined(CONFIG_NS_PLUS)) |
| 1082 | if (is_ddr_32bit()) { |
| 1083 | for(i=0; i<sizeof(ddr_phy_wl_regs) / sizeof(ddr_phy_wl_regs[0]); i++) { |
| 1084 | reg = (uint32_t)DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN + ddr_phy_wl_regs[i]; |
| 1085 | *ptr++ = reg; |
| 1086 | chksum += reg; |
| 1087 | // val = *(volatile uint32_t *)reg; |
| 1088 | val = reg32_read((volatile uint32_t *)reg); |
| 1089 | *ptr++ = val; |
| 1090 | chksum += val; |
| 1091 | } |
| 1092 | } |
| 1093 | #endif /* (CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT || defined(CONFIG_NS_PLUS)) */ |
| 1094 | #ifdef CONFIG_IPROC_DDR_ECC |
| 1095 | for(i=0; i<sizeof(ddr_phy_eccl_regs) / sizeof(ddr_phy_eccl_regs[0]); i++) { |
| 1096 | reg = (uint32_t)DDR_DENALI_CTL_00 + ddr_phy_eccl_regs[i]; |
| 1097 | *ptr++ = reg; |
| 1098 | chksum += reg; |
| 1099 | // val = *(volatile uint32_t *)reg; |
| 1100 | val = reg32_read((volatile uint32_t *)reg); |
| 1101 | *ptr++ = val; |
| 1102 | chksum += val; |
| 1103 | } |
| 1104 | #endif |
| 1105 | |
| 1106 | /* Fill checksum and length */ |
| 1107 | buffer[3] = chksum; |
| 1108 | buffer[4] = pairs; |
| 1109 | |
| 1110 | /* Write to flash */ |
| 1111 | printk(BIOS_INFO, "Writing Shmoo values into flash .....\n"); |
| 1112 | i = write_shmoo_to_flash(buffer, length); |
| 1113 | |
| 1114 | /* Free buffer */ |
| 1115 | // free(buffer); |
| 1116 | } |
| 1117 | |
| 1118 | #endif /* CONFIG_RUN_DDR_SHMOO2 && CONFIG_SHMOO_REUSE */ |
| 1119 | |
| 1120 | #include "soc/ddr_bist.h" |
| 1121 | #include "soc/shmoo_and28/shmoo_and28.h" |
| 1122 | |
| 1123 | #ifdef CONFIG_IPROC_DDR_ECC |
| 1124 | static int clear_ddr(uint32_t offset, uint32_t size) |
| 1125 | { |
| 1126 | unsigned long start; |
| 1127 | unsigned int i, val; |
| 1128 | |
| 1129 | reg32_write((uint32_t *)DDR_BistConfig,reg32_read((uint32_t *)DDR_BistConfig) & ~0x1); |
| 1130 | |
| 1131 | for( i = 0; i < 1000; i++); |
| 1132 | |
| 1133 | #if !defined(CONFIG_IPROC_P7) |
| 1134 | reg32_write((volatile uint32_t *)DDR_DENALI_CTL_213, 0x00FFFFFF); |
| 1135 | #endif |
| 1136 | |
| 1137 | reg32_write((volatile uint32_t *)DDR_BistConfig, 0x00000002); |
| 1138 | reg32_write((volatile uint32_t *)DDR_BistConfig, 0x00000003); |
| 1139 | reg32_write((volatile uint32_t *)DDR_BistConfig, 0x0000C003); |
| 1140 | reg32_write((volatile uint32_t *)DDR_BistGeneralConfigurations, 0x00000020); |
| 1141 | |
| 1142 | val = 255 << DDR_BistConfigurations__WriteWeight_R | |
| 1143 | 0 << DDR_BistConfigurations__ReadWeight_R | |
| 1144 | 1 << DDR_BistConfigurations__ConsAddr8Banks; |
| 1145 | |
| 1146 | reg32_write((volatile uint32_t *)DDR_BistConfigurations, val); |
| 1147 | |
| 1148 | |
| 1149 | reg32_write((volatile uint32_t *)DDR_BistStartAddress, offset); |
| 1150 | reg32_write((volatile uint32_t *)DDR_BistEndAddress, (1 << DDR_BistEndAddress__BistEndAddress_WIDTH) - 1); |
| 1151 | reg32_write((volatile uint32_t *)DDR_BistNumberOfActions, (size + 31) / 32); |
| 1152 | reg32_write((volatile uint32_t *)DDR_BistPatternWord0, 0); |
| 1153 | reg32_write((volatile uint32_t *)DDR_BistPatternWord1, 0); |
| 1154 | reg32_write((volatile uint32_t *)DDR_BistPatternWord2, 0); |
| 1155 | reg32_write((volatile uint32_t *)DDR_BistPatternWord3, 0); |
| 1156 | reg32_write((volatile uint32_t *)DDR_BistPatternWord4, 0); |
| 1157 | reg32_write((volatile uint32_t *)DDR_BistPatternWord5, 0); |
| 1158 | reg32_write((volatile uint32_t *)DDR_BistPatternWord6, 0); |
| 1159 | reg32_write((volatile uint32_t *)DDR_BistPatternWord7, 0); |
| 1160 | |
| 1161 | reg32_set_bits((volatile uint32_t *)DDR_BistConfigurations, 1 << DDR_BistConfigurations__IndWrRdAddrMode); |
| 1162 | |
| 1163 | reg32_set_bits((volatile uint32_t *)DDR_BistConfigurations, 1 << DDR_BistConfigurations__BistEn); |
| 1164 | |
| 1165 | start = get_timer(0); |
| 1166 | while(get_timer(start) <= 10000) { |
| 1167 | if(reg32_read((volatile uint32_t *)DDR_BistStatuses) & (1 << DDR_BistStatuses__BistFinished)) |
| 1168 | break; |
| 1169 | } |
| 1170 | /* Clear BIST_EN bit */ |
| 1171 | reg32_clear_bits((volatile uint32_t *)DDR_BistConfigurations, 1 << DDR_BistConfigurations__BistEn); |
| 1172 | |
| 1173 | if((get_timer(start) <= 10000) && |
| 1174 | (!reg32_read((volatile uint32_t *)DDR_BistErrorOccurred))) |
| 1175 | { |
| 1176 | printk(BIOS_INFO, "clear_ddr: OK\n"); |
| 1177 | return(0); |
| 1178 | } |
| 1179 | printk(BIOS_INFO, "clear_ddr: Failed: 0x%lx\n", get_timer(start)); |
| 1180 | if(reg32_read((volatile uint32_t *)DDR_BistErrorOccurred)) |
Martin Roth | 2ed0aa2 | 2016-01-05 20:58:58 -0700 | [diff] [blame] | 1181 | printk(BIOS_ERR, "clear_ddr: Error occurred\n"); |
Icarus Chau | d5f551a | 2015-02-13 15:16:37 -0800 | [diff] [blame] | 1182 | return(1); |
| 1183 | } |
| 1184 | #endif /* CONFIG_IPROC_DDR_ECC */ |
| 1185 | |
| 1186 | #if defined(CONFIG_SHMOO_AND28_REUSE) |
| 1187 | extern void restore_shmoo_config(and28_shmoo_config_param_t *shmoo_control_para); |
| 1188 | #endif |
| 1189 | |
Martin Roth | c4e49f6 | 2015-07-11 13:42:54 -0600 | [diff] [blame] | 1190 | #if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) |
Icarus Chau | d5f551a | 2015-02-13 15:16:37 -0800 | [diff] [blame] | 1191 | static int simple_ddr_crc32_check(void) |
| 1192 | { |
| 1193 | return 0; |
| 1194 | register uint32_t crc_mcu = 0; |
| 1195 | register uint32_t crc = 0, offset = 0; |
| 1196 | register volatile uint32_t *buf = (uint32_t *)0x60000000; |
| 1197 | register uint32_t len = 0x00100000;//in word |
| 1198 | |
| 1199 | printk(BIOS_INFO, "Checking simple DDR CRC, word start 0x%p, len 0x%08x...\n", buf, len); |
| 1200 | |
| 1201 | for(offset=0; offset<len; offset++) |
| 1202 | { |
| 1203 | crc ^= *buf++; |
| 1204 | } |
| 1205 | |
| 1206 | crc_mcu = reg32_read((volatile uint32_t *)0x03012A00); |
| 1207 | |
| 1208 | if(crc != crc_mcu) |
| 1209 | { |
| 1210 | printk(BIOS_ERR, "DDR CRC NOT match, old=0x%08x, new=0x%08x!\n", crc_mcu, crc); |
| 1211 | return -1; |
| 1212 | } |
| 1213 | else |
| 1214 | { |
| 1215 | printk(BIOS_INFO, "DDR CRC 0x%08x, match!\n", crc); |
| 1216 | return 0; |
| 1217 | } |
| 1218 | } |
| 1219 | #endif |
| 1220 | |
| 1221 | void ddr_init2(void) |
| 1222 | { |
| 1223 | int i; |
| 1224 | volatile unsigned int val; |
| 1225 | int ddr_type; |
| 1226 | uint32_t status, sku_id, ddr_clk, dev_id = 0; |
| 1227 | uint32_t unit = 0; |
| 1228 | uint32_t skip_shmoo = 0; |
Martin Roth | c4e49f6 | 2015-07-11 13:42:54 -0600 | [diff] [blame] | 1229 | #if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) |
Icarus Chau | d5f551a | 2015-02-13 15:16:37 -0800 | [diff] [blame] | 1230 | uint32_t pwrctli0 = reg32_read((volatile uint32_t *)IHOST_SCU_POWER_STATUS) & 0x3; |
| 1231 | skip_shmoo = reg32_read((volatile uint32_t *)CRMU_IHOST_POR_WAKEUP_FLAG) & 0x1; |
| 1232 | |
| 1233 | if(pwrctli0==2) |
| 1234 | { |
| 1235 | goto wakeup; |
| 1236 | } |
| 1237 | else if(pwrctli0==3) |
| 1238 | { |
| 1239 | skip_shmoo = 1; |
| 1240 | reg32_write((volatile uint32_t *)IHOST_GTIM_GLOB_CTRL, reg32_read((volatile uint32_t *)IHOST_GTIM_GLOB_CTRL)| 0x1); |
| 1241 | } |
Martin Roth | c4e49f6 | 2015-07-11 13:42:54 -0600 | [diff] [blame] | 1242 | #endif /* IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) */ |
Icarus Chau | d5f551a | 2015-02-13 15:16:37 -0800 | [diff] [blame] | 1243 | |
| 1244 | dev_id = dev_id; |
Martin Roth | c4e49f6 | 2015-07-11 13:42:54 -0600 | [diff] [blame] | 1245 | #if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) |
Icarus Chau | d5f551a | 2015-02-13 15:16:37 -0800 | [diff] [blame] | 1246 | and28_shmoo_dram_info_t sdi; |
| 1247 | and28_shmoo_config_param_t config_param; |
| 1248 | #endif |
| 1249 | |
Martin Roth | c4e49f6 | 2015-07-11 13:42:54 -0600 | [diff] [blame] | 1250 | #if !IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) |
Icarus Chau | d5f551a | 2015-02-13 15:16:37 -0800 | [diff] [blame] | 1251 | dev_id = (reg32_read((volatile uint32_t *)ChipcommonA_ChipID)) & 0x0000ffff; |
| 1252 | #else |
| 1253 | dev_id = 0x5800; |
| 1254 | cygnus_phy_powerup(); |
| 1255 | #endif |
| 1256 | |
Martin Roth | c4e49f6 | 2015-07-11 13:42:54 -0600 | [diff] [blame] | 1257 | #if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) |
Icarus Chau | d5f551a | 2015-02-13 15:16:37 -0800 | [diff] [blame] | 1258 | sku_id = (reg32_read((volatile uint32_t *)ROM_S0_IDM_IO_STATUS) >> 8) & 0x0f; |
| 1259 | #else |
| 1260 | sku_id = (reg32_read((volatile uint32_t *)ROM_S0_IDM_IO_STATUS) >> 2) & 0x03; |
| 1261 | #endif |
| 1262 | /* See if it is KATANA2, KATANA2 doesn't have right chip ID in ChipcommonA_ChipID */ |
| 1263 | if(((sku_id & 0xfff0) == 0xa450) || ((sku_id & 0xfff0) == 0xb450) || sku_id == 0xb248) { |
| 1264 | dev_id = 56450; /* KATANA2 */ |
| 1265 | } |
| 1266 | |
| 1267 | printk(BIOS_INFO, "DEV ID = 0x%x\n", dev_id); |
| 1268 | |
| 1269 | printk(BIOS_INFO, "SKU ID = 0x%x\n", sku_id); |
| 1270 | |
| 1271 | #if defined(CONFIG_IPROC_P7) |
| 1272 | val = reg32_read((volatile uint32_t *)DDR_S1_IDM_IO_STATUS) & 0x3; |
| 1273 | if (val == 0) { |
| 1274 | ddr_type = 1; |
| 1275 | } else if (val == 1) { |
| 1276 | ddr_type = 2; |
| 1277 | } else { |
| 1278 | printk(BIOS_ERR, "Unsupported DDR type: %d\n", val); |
| 1279 | goto done; |
| 1280 | } |
| 1281 | printk(BIOS_INFO, "DDR type: DDR%d\n", (ddr_type == 1)? 3 : 4); |
Martin Roth | c4e49f6 | 2015-07-11 13:42:54 -0600 | [diff] [blame] | 1282 | #elif IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) |
Icarus Chau | d5f551a | 2015-02-13 15:16:37 -0800 | [diff] [blame] | 1283 | ddr_type = 1; |
| 1284 | #else |
| 1285 | ddr_type = reg32_read((volatile uint32_t *)DDR_S1_IDM_IO_STATUS) & 0x1; |
| 1286 | printk(BIOS_INFO, "DDR type: DDR%d\n", (ddr_type) ? 3 : 2); |
| 1287 | #endif /* defined(CONFIG_IPROC_P7) */ |
| 1288 | |
| 1289 | ddr_clk = get_ddr_clock(sku_id, ddr_type); |
| 1290 | printk(BIOS_INFO, "MEMC 0 DDR speed = %dMHz\n", ddr_clk); |
| 1291 | |
| 1292 | status = change_ddr_clock(ddr_clk); |
| 1293 | if(status) { |
| 1294 | printk(BIOS_INFO, "CRU LCPLL configuratioin failed\n"); |
| 1295 | goto done; |
| 1296 | } |
| 1297 | |
| 1298 | #if defined(CONFIG_IPROC_P7) |
| 1299 | val = reg32_read((volatile uint32_t *)CRU_ddrphy_pwr_ctrl); |
| 1300 | |
| 1301 | /* assert power ON */ |
| 1302 | val |= 1 << CRU_ddrphy_pwr_ctrl__i_pwronin_phy; |
| 1303 | reg32_write((volatile uint32_t *)CRU_ddrphy_pwr_ctrl, val); |
| 1304 | |
| 1305 | /* assert power OK */ |
| 1306 | __udelay(10); |
| 1307 | val |= 1 << CRU_ddrphy_pwr_ctrl__i_pwrokin_phy; |
| 1308 | reg32_write((volatile uint32_t *)CRU_ddrphy_pwr_ctrl, val); |
| 1309 | |
| 1310 | /* remove DFI isolation */ |
| 1311 | __udelay(150); |
| 1312 | val &= ~(1 << CRU_ddrphy_pwr_ctrl__i_iso_phy_dfi); |
| 1313 | reg32_write((volatile uint32_t *)CRU_ddrphy_pwr_ctrl, val); |
| 1314 | |
| 1315 | /* remove PHY register isolation */ |
| 1316 | val &= ~(1 << CRU_ddrphy_pwr_ctrl__i_iso_phy_regs); |
| 1317 | reg32_write((volatile uint32_t *)CRU_ddrphy_pwr_ctrl, val); |
| 1318 | |
| 1319 | /* remove PLL isolation */ |
| 1320 | val &= ~(1 << CRU_ddrphy_pwr_ctrl__i_iso_phy_pll); |
| 1321 | reg32_write((volatile uint32_t *)CRU_ddrphy_pwr_ctrl, val); |
| 1322 | |
| 1323 | /* de-assert reset */ |
| 1324 | __udelay(200); |
| 1325 | val |= 1 << CRU_ddrphy_pwr_ctrl__i_hw_reset_n; |
| 1326 | reg32_write((volatile uint32_t *)CRU_ddrphy_pwr_ctrl, val); |
| 1327 | |
| 1328 | /* Wait for PHY power up */ |
| 1329 | for(i=0; i < 0x19000; i++) { |
| 1330 | val = reg32_read((volatile uint32_t *)DDR_S1_IDM_IO_STATUS); |
| 1331 | if((val & (1 << DDR_S1_IDM_IO_STATUS__o_phy_pwrup_rsb))) |
| 1332 | break; |
| 1333 | } |
| 1334 | if(i == 0x19000) { |
| 1335 | printk(BIOS_ERR, "DDR PHY not power up\n"); |
| 1336 | goto done; |
| 1337 | } |
| 1338 | #endif /* defined(CONFIG_IPROC_P7) */ |
| 1339 | |
Martin Roth | c4e49f6 | 2015-07-11 13:42:54 -0600 | [diff] [blame] | 1340 | #if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) || defined(CONFIG_IPROC_P7) |
Icarus Chau | d5f551a | 2015-02-13 15:16:37 -0800 | [diff] [blame] | 1341 | /* Get the DDR S1 and S2 out of reset */ |
| 1342 | reg32_write((volatile uint32_t *)DDR_S1_IDM_RESET_CONTROL, 0); |
| 1343 | reg32_write((volatile uint32_t *)DDR_S2_IDM_RESET_CONTROL, 0); |
| 1344 | |
| 1345 | __udelay(1000); |
| 1346 | reg32_write((volatile uint32_t *)DDR_S0_IDM_RESET_CONTROL, 0); |
| 1347 | /* Set the ddr_ck to 400 MHz, 2x memc clock */ |
| 1348 | reg32_write_masked((volatile uint32_t *)DDR_S1_IDM_IO_CONTROL_DIRECT, 0xfff << 16, /*ddr_clk*/ 0x190 << 16); |
| 1349 | |
| 1350 | if(pwrctli0==3) |
| 1351 | { |
| 1352 | printk(BIOS_INFO, "\n PRE_SRX call \n"); |
| 1353 | PRE_SRX(); |
| 1354 | } |
| 1355 | #else |
| 1356 | reg32_write((volatile uint32_t *)DDR_S1_IDM_RESET_CONTROL, 0); |
| 1357 | reg32_write((volatile uint32_t *)DDR_S2_IDM_RESET_CONTROL, 0); |
| 1358 | /* Set the ddr_ck to 400 MHz, 2x memc clock */ |
| 1359 | reg32_write_masked((volatile uint32_t *)DDR_S1_IDM_IO_CONTROL_DIRECT, 0xfff << 16, /*ddr_clk*/ 0x190 << 16); |
Martin Roth | c4e49f6 | 2015-07-11 13:42:54 -0600 | [diff] [blame] | 1360 | #endif /* IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) || defined(CONFIG_IPROC_P7) */ |
Icarus Chau | d5f551a | 2015-02-13 15:16:37 -0800 | [diff] [blame] | 1361 | |
| 1362 | #if defined(CONFIG_IPROC_P7) |
| 1363 | if (is_ddr_32bit()) { |
| 1364 | reg32_write_masked( |
| 1365 | (volatile uint32_t *)DDR_S2_IDM_IO_CONTROL_DIRECT, |
| 1366 | 1 << DDR_S2_IDM_IO_CONTROL_DIRECT__mode_32b, |
| 1367 | 1 << DDR_S2_IDM_IO_CONTROL_DIRECT__mode_32b |
| 1368 | ); |
| 1369 | } |
| 1370 | |
| 1371 | /* Wait for PHY ready */ |
| 1372 | for(i=0; i < 0x19000; i++) { |
| 1373 | val = reg32_read((volatile uint32_t *)DDR_S1_IDM_IO_STATUS); |
| 1374 | if((val & (1 << DDR_S1_IDM_IO_STATUS__o_phy_ready))) |
| 1375 | break; /* DDR PHY is up */ |
| 1376 | } |
| 1377 | |
| 1378 | if(i == 0x19000) { |
| 1379 | printk(BIOS_ERR, "DDR PLL not locked\n"); |
| 1380 | goto done; |
| 1381 | } |
| 1382 | |
| 1383 | /* Get the DDR S0 out of reset */ |
| 1384 | reg32_write((volatile uint32_t *)DDR_S0_IDM_RESET_CONTROL, 0); |
| 1385 | #endif /* defined(CONFIG_IPROC_P7) */ |
| 1386 | |
| 1387 | /* Wait for DDR PHY up */ |
| 1388 | for(i=0; i < 0x19000; i++) { |
| 1389 | val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION); |
| 1390 | if( val != 0) { |
| 1391 | printk(BIOS_INFO, "PHY revision version: 0x%08x\n", val); |
| 1392 | break; /* DDR PHY is up */ |
| 1393 | } |
| 1394 | } |
| 1395 | |
| 1396 | if(i == 0x19000) { |
| 1397 | printk(BIOS_ERR, "DDR PHY is not up\n"); |
| 1398 | return; |
| 1399 | } |
| 1400 | |
Martin Roth | c4e49f6 | 2015-07-11 13:42:54 -0600 | [diff] [blame] | 1401 | #if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) |
Icarus Chau | d5f551a | 2015-02-13 15:16:37 -0800 | [diff] [blame] | 1402 | if(!skip_shmoo) |
| 1403 | { |
| 1404 | printk(BIOS_INFO, "ddr_init2: Calling soc_and28_shmoo_dram_info_set\n"); |
| 1405 | /* Cygnus clock speed: |
| 1406 | * |
| 1407 | * clock rate |
| 1408 | * 400 800 |
| 1409 | * 533 1066 |
| 1410 | * 667 1333 |
| 1411 | * 800 1600 |
| 1412 | */ |
| 1413 | sdi.data_rate_mbps = (ddr_clk == 667) ? 1333 : ((ddr_clk == 333) ? 667 : (ddr_clk << 1)); |
| 1414 | sdi.ref_clk_mhz = 50; |
| 1415 | sdi.ctl_type = DDR_CTL_TYPE_1; |
| 1416 | sdi.dram_type = DDR_DRAM_TYPE_DDR3L; |
| 1417 | sdi.dram_bitmap = 0x00000001; |
| 1418 | sdi.interface_bitwidth = SDI_INTERFACE_BITWIDTH; |
| 1419 | sdi.num_columns = SDI_NUM_COLUMNS; |
| 1420 | sdi.num_rows = SDI_NUM_ROWS; |
| 1421 | sdi.num_banks = SDI_NUM_BANKS; |
| 1422 | sdi.refi = 7800; |
| 1423 | sdi.command_parity_latency = 0; |
| 1424 | sdi.sim_system_mode = 0; |
| 1425 | printk(BIOS_INFO, "ddr_init2: Calling soc_and28_shmoo_dram_info_set\n"); |
| 1426 | soc_and28_shmoo_dram_info_set(unit, &sdi); |
| 1427 | } |
| 1428 | else |
| 1429 | { |
| 1430 | printk(BIOS_INFO, "DeepSleep wakeup: ddr init bypassed 1\n"); |
| 1431 | } |
| 1432 | #else |
| 1433 | #error "DRAM config is not set" |
| 1434 | #endif |
| 1435 | |
Martin Roth | c4e49f6 | 2015-07-11 13:42:54 -0600 | [diff] [blame] | 1436 | #if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) |
Icarus Chau | d5f551a | 2015-02-13 15:16:37 -0800 | [diff] [blame] | 1437 | if(!skip_shmoo) |
| 1438 | { |
| 1439 | printk(BIOS_INFO, "ddr_init2: Calling soc_and28_shmoo_phy_init\n"); |
| 1440 | if(soc_and28_shmoo_phy_init(unit, 0) != SOC_E_NONE) { |
| 1441 | |
| 1442 | printk(BIOS_ERR, "DDR PHY initialization failed\n"); |
| 1443 | goto done; |
| 1444 | } |
| 1445 | } |
| 1446 | else |
| 1447 | { |
| 1448 | printk(BIOS_INFO, "DeepSleep wakeup: ddr init bypassed 2\n"); |
| 1449 | } |
| 1450 | #endif |
| 1451 | |
| 1452 | #ifdef CONFIG_RUN_DDR_SHMOO |
| 1453 | printk(BIOS_DEBUG, "PHY register dump after DDR PHY init\n"); |
| 1454 | dump_phy_regs(); |
| 1455 | #endif |
| 1456 | |
| 1457 | printk(BIOS_INFO, "Programming controller register\n"); |
| 1458 | ddr_init_regs(ddr_init_tab); |
| 1459 | |
| 1460 | ddr_type = 1; |
| 1461 | if(ddr_type) { |
| 1462 | /* DDR3 */ |
| 1463 | switch(ddr_clk) { |
| 1464 | #ifdef CONFIG_DDR333 |
| 1465 | case 333: |
| 1466 | ddr_init_regs(ddr3_init_tab_667); |
| 1467 | break; |
| 1468 | #endif |
| 1469 | #ifdef CONFIG_DDR400 |
| 1470 | case 400: |
| 1471 | ddr_init_regs(ddr3_init_tab_800); |
| 1472 | break; |
| 1473 | #endif |
| 1474 | #ifdef CONFIG_DDR533 |
| 1475 | case 533: |
| 1476 | ddr_init_regs(ddr3_init_tab_1066); |
| 1477 | break; |
| 1478 | #endif |
| 1479 | #ifdef CONFIG_DDR667 |
| 1480 | case 667: |
| 1481 | ddr_init_regs(ddr3_init_tab_1333); |
| 1482 | break; |
| 1483 | #endif |
Martin Roth | c4e49f6 | 2015-07-11 13:42:54 -0600 | [diff] [blame] | 1484 | #if (defined(CONFIG_DDR750) || IS_ENABLED(CONFIG_CYGNUS_DDR800)) |
Icarus Chau | d5f551a | 2015-02-13 15:16:37 -0800 | [diff] [blame] | 1485 | case 750: |
| 1486 | case 800: |
| 1487 | ddr_init_regs(ddr3_init_tab_1600); |
| 1488 | break; |
| 1489 | #endif |
| 1490 | } |
| 1491 | } |
| 1492 | |
Icarus Chau | be47636 | 2015-04-07 16:09:24 -0700 | [diff] [blame] | 1493 | #if CONFIG_CYGNUS_DDR_AUTO_SELF_REFRESH_ENABLE |
| 1494 | #if (DDR_AUTO_SELF_REFRESH_IDLE_COUNT > 0) & (DDR_AUTO_SELF_REFRESH_IDLE_COUNT <= 0xff) |
| 1495 | /* Enable auto self-refresh */ |
| 1496 | reg32_set_bits((unsigned int *)DDR_DENALI_CTL_57, |
| 1497 | 0x2 << DDR_DENALI_CTL_57__LP_AUTO_EXIT_EN_R | |
| 1498 | 0x2 << DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_R ); |
| 1499 | |
| 1500 | reg32_set_bits((unsigned int *)DDR_DENALI_CTL_58, |
| 1501 | DDR_AUTO_SELF_REFRESH_IDLE_COUNT << DDR_DENALI_CTL_58__LP_AUTO_SR_IDLE_R); |
| 1502 | #else |
| 1503 | #error DDR_AUTO_SELF_REFRESH_IDLE_COUNT out of range |
| 1504 | #endif |
| 1505 | #else |
| 1506 | /* Disable auto-self refresh */ |
| 1507 | reg32_clear_bits((unsigned int *)DDR_DENALI_CTL_57, |
| 1508 | 0x2 << DDR_DENALI_CTL_57__LP_AUTO_EXIT_EN_R | |
| 1509 | 0x2 << DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_R ); |
| 1510 | reg32_clear_bits((unsigned int *)DDR_DENALI_CTL_58, |
| 1511 | 0xff << DDR_DENALI_CTL_58__LP_AUTO_SR_IDLE_R ); |
| 1512 | #endif |
| 1513 | |
Icarus Chau | d5f551a | 2015-02-13 15:16:37 -0800 | [diff] [blame] | 1514 | /* Start the DDR */ |
| 1515 | reg32_set_bits((volatile uint32_t *)DDR_DENALI_CTL_00, 0x01); |
| 1516 | |
Martin Roth | c4e49f6 | 2015-07-11 13:42:54 -0600 | [diff] [blame] | 1517 | #if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) |
Icarus Chau | d5f551a | 2015-02-13 15:16:37 -0800 | [diff] [blame] | 1518 | if(!skip_shmoo) |
| 1519 | { |
| 1520 | while(!(reg32_read((volatile uint32_t *)DDR_DENALI_CTL_175) & 0x100)); |
| 1521 | printk(BIOS_INFO, "ddr_init2: MemC initialization complete\n"); |
| 1522 | |
| 1523 | reg32_set_bits((unsigned int *)DDR_DENALI_CTL_177, 0x00100); |
| 1524 | reg32_write((unsigned int *)DDR_BistConfig, 0x00000002); |
| 1525 | reg32_write((unsigned int *)DDR_BistConfig, 0x00000003); |
| 1526 | reg32_write((unsigned int *)DDR_BistConfig, 0x0000C003); |
| 1527 | reg32_write((unsigned int *)DDR_BistGeneralConfigurations, 0x00000020); |
| 1528 | |
| 1529 | printk(BIOS_INFO, "ddr_init2: Calling soc_and28_shmoo_ctl\n"); |
| 1530 | #if defined(CONFIG_SHMOO_AND28_REUSE) |
| 1531 | if (is_shmoo_data_valid()) { |
| 1532 | restore_shmoo_config(&config_param); |
| 1533 | soc_and28_shmoo_ctl(unit, 0, SHMOO_AND28_SHMOO_RSVP, 0, 1, SHMOO_AND28_ACTION_RESTORE, &config_param); |
| 1534 | |
| 1535 | #if defined(CONFIG_SHMOO_REUSE_MEMTEST_LENGTH) |
| 1536 | /* Perform memory test to see if the stored SHMMO values work */ |
| 1537 | if (CONFIG_SHMOO_REUSE_MEMTEST_LENGTH > 0) { |
| 1538 | /* Release DDR to AXI for memory testing */ |
| 1539 | reg32_clear_bits((volatile uint32_t *)DDR_BistConfig, 1 << DDR_BistConfig__axi_port_sel); |
| 1540 | |
| 1541 | printk(BIOS_INFO, "Running simple memory test ..... "); |
| 1542 | i = simple_memory_test( |
| 1543 | (void *)CONFIG_SHMOO_REUSE_MEMTEST_START, |
| 1544 | CONFIG_SHMOO_REUSE_MEMTEST_LENGTH); |
| 1545 | if (i) { |
| 1546 | printk(BIOS_ERR, "failed!\n"); |
| 1547 | |
| 1548 | /* Connect DDR controller to BIST for SHMOO */ |
| 1549 | reg32_set_bits((volatile uint32_t *)DDR_BistConfig, 1 << DDR_BistConfig__axi_port_sel); |
| 1550 | |
| 1551 | /* Perform full SHMOO since stored values don't work */ |
| 1552 | soc_and28_shmoo_ctl(unit, 0, SHMOO_AND28_SHMOO_RSVP, 0, 1, SHMOO_AND28_ACTION_RUN, &config_param); |
| 1553 | } else { |
| 1554 | printk(BIOS_INFO, "OK\n"); |
| 1555 | } |
| 1556 | } |
| 1557 | #endif /* defined(CONFIG_SHMOO_REUSE_MEMTEST_LENGTH) */ |
| 1558 | |
| 1559 | } else { |
| 1560 | soc_and28_shmoo_ctl(unit, 0, SHMOO_AND28_SHMOO_RSVP, 0, 1, SHMOO_AND28_ACTION_RUN, &config_param); |
| 1561 | } |
| 1562 | #else |
| 1563 | soc_and28_shmoo_ctl(unit, 0, SHMOO_AND28_SHMOO_RSVP, 0, 1, SHMOO_AND28_ACTION_RUN, &config_param); |
| 1564 | #endif /* CONFIG_SHMOO_AND28_REUSE */ |
| 1565 | } |
| 1566 | #endif |
| 1567 | else |
| 1568 | { |
| 1569 | printk(BIOS_INFO, "DeepSleep wakeup: ddr init bypassed 3\n"); |
| 1570 | } |
| 1571 | |
| 1572 | #if defined(CONFIG_IPROC_P7) && defined(CONFIG_IPROC_DDR_ECC) |
| 1573 | printk(BIOS_INFO, "Enabling DDR ECC correcting and reporting\n"); |
| 1574 | |
| 1575 | /* Clear DDR ECC interrupts if any */ |
| 1576 | reg32_set_bits((volatile uint32_t *)DDR_DENALI_CTL_177, |
| 1577 | DDR_DENALI_CTL_177_ECC_MASK); |
| 1578 | |
| 1579 | /* Disable auto corruption */ |
| 1580 | reg32_set_bits((volatile uint32_t *)DDR_DENALI_CTL_148, |
| 1581 | 1 << DDR_DENALI_CTL_148__ECC_DISABLE_W_UC_ERR); |
| 1582 | |
| 1583 | /* Enable ECC correction and reporting */ |
| 1584 | reg32_set_bits((volatile uint32_t *)DDR_DENALI_CTL_146, |
| 1585 | 1 << DDR_DENALI_CTL_146__ECC_EN); |
| 1586 | |
| 1587 | /* Initialize DDR so that uninitialized reads won't report ecc error */ |
| 1588 | clear_ddr(0, CONFIG_PHYS_SDRAM_1_SIZE); |
| 1589 | #elif defined(CONFIG_IPROC_DDR_ECC) |
| 1590 | printk(BIOS_INFO, "Enabling DDR ECC reporting\n"); |
| 1591 | /* Clear DDR interrupts if any */ |
| 1592 | *(unsigned int *)(DDR_DENALI_CTL_213) = 0x00FFFFFF; |
| 1593 | __udelay(1000); |
| 1594 | reg32_set_bits((volatile uint32_t *)DDR_DENALI_CTL_67, 0x01); //Disable auto correction |
| 1595 | reg32_set_bits((volatile uint32_t *)DDR_DENALI_CTL_66, 0x01); //Enable ECC |
| 1596 | |
| 1597 | clear_ddr(0, CONFIG_PHYS_SDRAM_1_SIZE); |
| 1598 | printk(BIOS_INFO, "Enabling DDR ECC correction\n"); |
| 1599 | reg32_set_bits((volatile uint32_t *)DDR_DENALI_CTL_66, 1 << 1); //Enable ECC correction |
| 1600 | #endif /* defined(CONFIG_IPROC_P7) && defined(CONFIG_IPROC_DDR_ECC) */ |
| 1601 | |
| 1602 | /* Release DDR slave port to AXI */ |
| 1603 | reg32_clear_bits((volatile uint32_t *)DDR_BistConfig, 1 << DDR_BistConfig__axi_port_sel); |
| 1604 | printk(BIOS_INFO, "DDR Interface Ready\n"); |
| 1605 | |
| 1606 | //dump_phy_regs(); |
| 1607 | |
Martin Roth | c4e49f6 | 2015-07-11 13:42:54 -0600 | [diff] [blame] | 1608 | #if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) |
Icarus Chau | d5f551a | 2015-02-13 15:16:37 -0800 | [diff] [blame] | 1609 | /* SRX */ |
| 1610 | if(skip_shmoo) |
| 1611 | { |
| 1612 | // Enter Self refresh (dummy) , to keep Denali happy |
| 1613 | reg32_write((unsigned int *)DDR_DENALI_CTL_56, 0x0a050505); |
| 1614 | |
| 1615 | __udelay(200); |
| 1616 | printk(BIOS_INFO, "\nDDR self refresh exit \n"); |
| 1617 | |
| 1618 | // Assert DFI request from PHY to mask any interaction with MEMC |
| 1619 | reg32_write((unsigned int *)DDR_PHY_CONTROL_REGS_DFI_CNTRL, 0xe0); |
| 1620 | reg32_write((unsigned int *)DDR_PHY_CONTROL_REGS_DFI_CNTRL, 0); |
| 1621 | |
| 1622 | // Exit Self refresh |
| 1623 | reg32_write((unsigned int *)DDR_DENALI_CTL_56, 0x09050505); |
| 1624 | } |
| 1625 | |
| 1626 | /* Clear iHOST flag */ |
| 1627 | reg32_write((unsigned int *)CRMU_IHOST_POR_WAKEUP_FLAG, 0x0); |
| 1628 | printk(BIOS_INFO, "IHOST POR WAKEUP FLAG cleared\n"); |
| 1629 | |
| 1630 | // iproc_dump_ddr_regs(); |
| 1631 | |
| 1632 | if(pwrctli0==0) |
| 1633 | goto done; |
| 1634 | |
| 1635 | wakeup: |
| 1636 | printk(BIOS_INFO, "Wakeup from %s\n", pwrctli0==2 ? "SLEEP":"DEEPSLEEP"); |
| 1637 | |
| 1638 | if(pwrctli0==3) |
| 1639 | { |
| 1640 | __udelay(10000); |
| 1641 | if(simple_ddr_crc32_check()<0) |
| 1642 | { |
| 1643 | printk(BIOS_INFO, "Die...\n"); |
| 1644 | while(1); |
| 1645 | } |
| 1646 | } |
| 1647 | |
| 1648 | /* CRMU_IHOST_SW_PERSISTENT_REG4 = 0x03024c64 */ |
| 1649 | asm( |
| 1650 | "movw r3, #0x4c64\n" |
| 1651 | "movt r3, #0x0302\n" |
| 1652 | "ldr r5, [r3]\n" |
| 1653 | "mov lr, #0\n" |
| 1654 | "mov pc, r5\n"); |
Martin Roth | c4e49f6 | 2015-07-11 13:42:54 -0600 | [diff] [blame] | 1655 | #endif /* IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) */ |
Icarus Chau | d5f551a | 2015-02-13 15:16:37 -0800 | [diff] [blame] | 1656 | |
| 1657 | done: |
| 1658 | /* Reclaim everything we have previously allocated for temporary usage. */ |
| 1659 | // free_heap(); |
| 1660 | return; |
| 1661 | } |