Michał Żygowski | 90989b3 | 2022-04-07 15:16:46 +0200 | [diff] [blame] | 1 | chip soc/intel/alderlake |
Michał Kopeć | 7592625 | 2022-04-08 14:41:23 +0200 | [diff] [blame] | 2 | # FSP configuration |
| 3 | |
| 4 | register "eist_enable" = "1" |
| 5 | |
| 6 | # Sagv Configuration |
| 7 | register "sagv" = "SaGv_Enabled" |
| 8 | register "RMT" = "0" |
| 9 | register "enable_c6dram" = "1" |
| 10 | |
| 11 | register "pmc_gpe0_dw0" = "GPP_J" |
| 12 | register "pmc_gpe0_dw1" = "GPP_VPGIO" |
| 13 | register "pmc_gpe0_dw2" = "GPD" |
| 14 | |
| 15 | # USB Configuration |
Michał Żygowski | eb9f1e1 | 2022-11-14 13:10:35 +0100 | [diff] [blame^] | 16 | register "usb2_ports[0]" = "USB2_PORT_SHORT(OC2)" # USB-C LAN_USB1 |
| 17 | register "usb2_ports[1]" = "USB2_PORT_SHORT(OC1)" # MSI MYSTIC LIGHT |
| 18 | register "usb2_ports[2]" = "USB2_PORT_SHORT(OC0)" # USB-A LAN_USB1 |
| 19 | register "usb2_ports[3]" = "USB2_PORT_LONG(OC0)" # JUSB5 |
| 20 | register "usb2_ports[4]" = "USB2_PORT_SHORT(OC3)" # HUB to rear USB 2.0 |
Michał Żygowski | 1c3b443 | 2022-05-12 15:21:08 +0200 | [diff] [blame] | 21 | register "usb2_ports[5]" = "USB2_PORT_LONG(OC3)" # empty? |
| 22 | register "usb2_ports[6]" = "USB2_PORT_LONG(OC7)" # JUSB4 |
| 23 | register "usb2_ports[7]" = "USB2_PORT_LONG(OC0)" # JUSB4 |
| 24 | register "usb2_ports[8]" = "USB2_PORT_LONG(OC2)" # JUSB3 |
| 25 | register "usb2_ports[9]" = "USB2_PORT_LONG(OC7)" # JUSB3 |
Michał Żygowski | eb9f1e1 | 2022-11-14 13:10:35 +0100 | [diff] [blame^] | 26 | register "usb2_ports[10]" = "USB2_PORT_SHORT(OC0)" # PS2_USB1 |
| 27 | register "usb2_ports[11]" = "USB2_PORT_SHORT(OC0)" # PS2_USB1 |
| 28 | register "usb2_ports[12]" = "USB2_PORT_SHORT(OC0)" # HUB to USB 2.0 headers |
| 29 | register "usb2_ports[13]" = "USB2_PORT_SHORT(OC6)" # CNVi BT |
| 30 | register "usb2_ports[14]" = "USB2_PORT_EMPTY" # USB Redirection port 1 |
| 31 | register "usb2_ports[15]" = "USB2_PORT_EMPTY" # USB Redirection port 2 |
Michał Kopeć | 7592625 | 2022-04-08 14:41:23 +0200 | [diff] [blame] | 32 | |
Michał Żygowski | 1c3b443 | 2022-05-12 15:21:08 +0200 | [diff] [blame] | 33 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # USB-C LAN_USB1 |
| 34 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB-A LAN_USB1 |
| 35 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # JUSB5 |
| 36 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" # USB-A USB2 |
| 37 | register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC7)" # USB-A USB2 |
| 38 | register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC7)" # JUSB4 |
| 39 | register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC2)" # JUSB4 |
| 40 | register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" # JUSB3 |
| 41 | register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC0)" # JUSB3 |
| 42 | register "usb3_ports[9]" = "USB3_PORT_EMPTY" |
Michał Kopeć | 7592625 | 2022-04-08 14:41:23 +0200 | [diff] [blame] | 43 | |
| 44 | # LPC generic I/O ranges |
| 45 | register "gen1_dec" = "0x00fc0201" |
| 46 | register "gen2_dec" = "0x003c0a01" |
| 47 | register "gen3_dec" = "0x000c03f1" |
| 48 | register "gen4_dec" = "0x000c0081" |
| 49 | |
| 50 | register "sata_salp_support" = "1" |
| 51 | |
| 52 | register "sata_ports_enable" = "{ |
| 53 | [0] = 1, |
| 54 | [1] = 1, |
| 55 | [2] = 1, |
| 56 | [3] = 1, |
| 57 | [4] = 1, |
| 58 | [5] = 1, |
| 59 | [6] = 1, |
| 60 | [7] = 1, |
| 61 | }" |
| 62 | |
| 63 | register "sata_ports_dev_slp" = "{ |
| 64 | [0] = 0, |
| 65 | [1] = 0, |
| 66 | [2] = 0, |
| 67 | [3] = 0, |
| 68 | [4] = 0, |
| 69 | [5] = 0, |
| 70 | [6] = 1, |
| 71 | [7] = 1, |
| 72 | }" |
| 73 | |
Michał Żygowski | 6cf9b8f | 2022-04-08 19:02:42 +0200 | [diff] [blame] | 74 | # HDMI on port B |
| 75 | register "ddi_portB_config" = "1" |
| 76 | register "ddi_ports_config" = "{ |
| 77 | [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, |
| 78 | [DDI_PORT_C] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, |
| 79 | [DDI_PORT_1] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, |
| 80 | [DDI_PORT_2] = DDI_ENABLE_HPD, |
| 81 | [DDI_PORT_3] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, |
| 82 | [DDI_PORT_4] = DDI_ENABLE_HPD, |
| 83 | }" |
| 84 | |
Michał Żygowski | c354f31 | 2022-04-15 18:19:19 +0200 | [diff] [blame] | 85 | register "hybrid_storage_mode" = "1" |
| 86 | register "dmi_power_optimize_disable" = "1" |
| 87 | |
Michał Żygowski | ffec028 | 2022-05-04 15:46:16 +0200 | [diff] [blame] | 88 | # FIVR configuration |
| 89 | register "fivr_rfi_frequency" = "1394" |
| 90 | register "fivr_spread_spectrum" = "FIVR_SS_1_5" |
| 91 | register "ext_fivr_settings" = "{ |
| 92 | .configure_ext_fivr = 1, |
| 93 | }" |
| 94 | |
Michał Żygowski | 90989b3 | 2022-04-07 15:16:46 +0200 | [diff] [blame] | 95 | device domain 0 on |
Michał Żygowski | c354f31 | 2022-04-15 18:19:19 +0200 | [diff] [blame] | 96 | subsystemid 0x1462 0x7d25 inherit |
| 97 | device ref pcie5_0 on |
| 98 | register "cpu_pcie_rp[CPU_RP(2)]" = "{ |
| 99 | .clk_src = 0, |
| 100 | .clk_req = 0, |
| 101 | .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_HOTPLUG, |
| 102 | .PcieRpL1Substates = L1_SS_L1_2, |
| 103 | .pcie_rp_aspm = ASPM_L0S_L1, |
| 104 | }" |
| 105 | smbios_slot_desc "SlotTypePciExpressGen5x16" "SlotLengthLong" |
| 106 | "PCI_E1" "SlotDataBusWidth16X" |
| 107 | end |
| 108 | device ref pcie5_1 off end |
Michał Żygowski | 90989b3 | 2022-04-07 15:16:46 +0200 | [diff] [blame] | 109 | device ref igpu on end |
Michał Żygowski | c354f31 | 2022-04-15 18:19:19 +0200 | [diff] [blame] | 110 | device ref pcie4_0 on |
| 111 | register "cpu_pcie_rp[CPU_RP(1)]" = "{ |
| 112 | .clk_src = 9, |
| 113 | .clk_req = 9, |
| 114 | .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT, |
| 115 | .PcieRpL1Substates = L1_SS_L1_2, |
| 116 | .pcie_rp_aspm = ASPM_L0S_L1, |
| 117 | }" |
| 118 | smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" |
| 119 | "M2_1" "SlotDataBusWidth4X" |
| 120 | end |
Michał Żygowski | 90989b3 | 2022-04-07 15:16:46 +0200 | [diff] [blame] | 121 | device ref crashlog off end |
| 122 | device ref xhci on end |
Michał Żygowski | c354f31 | 2022-04-15 18:19:19 +0200 | [diff] [blame] | 123 | device ref cnvi_wifi on |
| 124 | # Enable CNVi BT |
| 125 | register "cnvi_bt_core" = "true" |
| 126 | register "cnvi_bt_audio_offload" = "false" |
Michał Żygowski | 0feffd1 | 2022-04-25 12:10:52 +0200 | [diff] [blame] | 127 | chip drivers/wifi/generic |
| 128 | register "wake" = "GPE0_PME_B0" |
| 129 | register "enable_cnvi_ddr_rfim" = "true" |
| 130 | device generic 0 on end |
| 131 | end |
Michał Żygowski | c354f31 | 2022-04-15 18:19:19 +0200 | [diff] [blame] | 132 | end |
Michał Żygowski | 90989b3 | 2022-04-07 15:16:46 +0200 | [diff] [blame] | 133 | device ref heci1 on end |
| 134 | device ref heci2 off end |
| 135 | device ref ide_r off end |
| 136 | device ref kt off end |
| 137 | device ref heci3 off end |
| 138 | device ref heci4 off end |
| 139 | device ref sata on end |
Michał Żygowski | c354f31 | 2022-04-15 18:19:19 +0200 | [diff] [blame] | 140 | device ref pcie_rp1 on |
| 141 | register "pch_pcie_rp[PCH_RP(1)]" = "{ |
| 142 | .clk_src = 10, |
| 143 | .clk_req = 10, |
| 144 | .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_HOTPLUG | PCIE_RP_CLK_REQ_DETECT, |
| 145 | .PcieRpL1Substates = L1_SS_L1_2, |
| 146 | .pcie_rp_aspm = ASPM_L0S_L1, |
| 147 | }" |
| 148 | smbios_slot_desc "SlotTypePciExpressGen3X1" "SlotLengthShort" |
| 149 | "PCI_E2" "SlotDataBusWidth1X" |
| 150 | end |
| 151 | device ref pcie_rp2 on |
| 152 | register "pch_pcie_rp[PCH_RP(2)]" = "{ |
| 153 | .clk_src = 17, |
| 154 | .clk_req = 17, |
| 155 | .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_HOTPLUG | PCIE_RP_CLK_REQ_DETECT, |
| 156 | .PcieRpL1Substates = L1_SS_L1_2, |
| 157 | .pcie_rp_aspm = ASPM_L0S_L1, |
| 158 | }" |
| 159 | smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" |
| 160 | "PCI_E4" "SlotDataBusWidth1X" |
| 161 | end |
| 162 | device ref pcie_rp3 on |
| 163 | # i225 Ethernet, Clock PM unsupported, onboard device |
| 164 | register "pch_pcie_rp[PCH_RP(3)]" = "{ |
| 165 | .clk_src = 12, |
| 166 | .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN, |
| 167 | .PcieRpL1Substates = L1_SS_L1_2, |
| 168 | .pcie_rp_aspm = ASPM_L0S_L1, |
| 169 | }" |
| 170 | end |
| 171 | device ref pcie_rp4 off end |
| 172 | |
| 173 | device ref pcie_rp5 on |
| 174 | register "pch_pcie_rp[PCH_RP(5)]" = "{ |
| 175 | .clk_src = 15, |
| 176 | .clk_req = 15, |
| 177 | .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_HOTPLUG | PCIE_RP_CLK_REQ_DETECT, |
| 178 | .PcieRpL1Substates = L1_SS_L1_2, |
| 179 | .pcie_rp_aspm = ASPM_L0S_L1, |
| 180 | }" |
| 181 | smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" |
| 182 | "PCI_E3" "SlotDataBusWidth4X" |
| 183 | end |
| 184 | |
| 185 | device ref pcie_rp9 on |
| 186 | register "pch_pcie_rp[PCH_RP(9)]" = "{ |
| 187 | .clk_src = 13, |
| 188 | .clk_req = 13, |
| 189 | .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT, |
| 190 | .PcieRpL1Substates = L1_SS_L1_2, |
| 191 | .pcie_rp_aspm = ASPM_L0S_L1, |
| 192 | }" |
| 193 | smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" |
| 194 | "M2_3" "SlotDataBusWidth4X" |
| 195 | end |
| 196 | |
| 197 | # These are not enabled. The Flex I/O mode is SATA to cover all 8 SATA ports. |
| 198 | # There is an ASMedia switch on-board to mux the SATA ports 7, 8 and PCIe |
| 199 | # 9-12, 21-24 to M2_3 and M2_4 slots |
| 200 | device ref pcie_rp13 off end |
| 201 | device ref pcie_rp14 off end |
| 202 | device ref pcie_rp15 off end |
| 203 | device ref pcie_rp16 off end |
| 204 | device ref pcie_rp17 off end |
| 205 | device ref pcie_rp18 off end |
| 206 | device ref pcie_rp19 off end |
| 207 | device ref pcie_rp20 off end |
| 208 | |
| 209 | device ref pcie_rp21 on |
| 210 | register "pch_pcie_rp[PCH_RP(21)]" = "{ |
| 211 | .clk_src = 14, |
| 212 | .clk_req = 14, |
| 213 | .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT, |
| 214 | .PcieRpL1Substates = L1_SS_L1_2, |
| 215 | .pcie_rp_aspm = ASPM_L0S_L1, |
| 216 | }" |
| 217 | smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" |
| 218 | "M2_4" "SlotDataBusWidth4X" |
| 219 | end |
| 220 | |
| 221 | device ref pcie_rp25 on |
| 222 | register "pch_pcie_rp[PCH_RP(25)]" = "{ |
| 223 | .clk_src = 8, |
| 224 | .clk_req = 8, |
| 225 | .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT, |
| 226 | .PcieRpL1Substates = L1_SS_L1_2, |
| 227 | .pcie_rp_aspm = ASPM_L0S_L1, |
| 228 | }" |
| 229 | smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" |
| 230 | "M2_2" "SlotDataBusWidth4X" |
| 231 | end |
Michał Żygowski | ba9b2b7 | 2022-04-28 13:15:36 +0200 | [diff] [blame] | 232 | device ref pch_espi on |
| 233 | chip superio/nuvoton/nct6687d |
| 234 | device pnp 4e.1 off end # Parallel port |
| 235 | device pnp 4e.2 on # COM1 |
| 236 | io 0x60 = 0x3f8 |
| 237 | irq 0x70 = 4 |
| 238 | end |
| 239 | device pnp 4e.3 off end # COM2, IR |
| 240 | device pnp 4e.5 on # Keyboard |
| 241 | io 0x60 = 0x60 |
| 242 | io 0x62 = 0x64 |
| 243 | irq 0x70 = 1 |
| 244 | irq 0x72 = 12 |
| 245 | end |
| 246 | device pnp 4e.6 off end # CIR |
| 247 | device pnp 4e.7 off end # GPIO0-7 |
| 248 | device pnp 4e.8 off end # P80 UART |
| 249 | device pnp 4e.9 off end # GPIO8-9, GPIO1-8 AF |
| 250 | device pnp 4e.a on # ACPI |
| 251 | # Vendor firmware did not assign I/O and IRQ |
| 252 | end |
| 253 | device pnp 4e.b on # EC |
| 254 | io 0x60 = 0xa20 |
| 255 | # Vendor firmware did not assign IRQ |
| 256 | end |
| 257 | device pnp 4e.c off end # RTC |
| 258 | device pnp 4e.d off end # Deep Sleep |
| 259 | device pnp 4e.e off end # TACH/PWM assignment |
| 260 | device pnp 4e.f off end # Function register |
| 261 | end |
| 262 | end |
Michał Żygowski | 90989b3 | 2022-04-07 15:16:46 +0200 | [diff] [blame] | 263 | device ref p2sb on end |
Michał Żygowski | ed8216d | 2022-04-19 18:23:41 +0200 | [diff] [blame] | 264 | device ref hda on |
| 265 | subsystemid 0x1462 0x9d25 |
Sean Rhodes | 854bd49 | 2023-01-06 11:20:30 +0000 | [diff] [blame] | 266 | register "pch_hda_audio_link_hda_enable" = "1" |
Michał Żygowski | ed8216d | 2022-04-19 18:23:41 +0200 | [diff] [blame] | 267 | register "pch_hda_dsp_enable" = "0" |
| 268 | register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" |
| 269 | register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" |
| 270 | register "pch_hda_idisp_codec_enable" = "true" |
| 271 | end |
Michał Żygowski | 90989b3 | 2022-04-07 15:16:46 +0200 | [diff] [blame] | 272 | device ref smbus on end |
Michał Żygowski | f0f8a5f | 2022-04-23 00:22:20 +0200 | [diff] [blame] | 273 | |
| 274 | chip drivers/crb |
| 275 | device mmio 0xfed40000 on end |
| 276 | end |
Michał Żygowski | 90989b3 | 2022-04-07 15:16:46 +0200 | [diff] [blame] | 277 | end |
| 278 | end |