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review.coreboot.org / coreboot / eb8ee59f87d08868cdd9975d67f49da5a11181e4 / . / src / soc / amd / mendocino / chip.h
blob: 858bcbe07c8d444e1be5d4e86dd71078dba59c80 [file] [log] [blame]
Felix Held3c44c622022-01-10 20:57:29 +0100[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
2
Jon Murphy4f732422022-08-05 15:43:44 -0600[diff] [blame]3#ifndef MENDOCINO_CHIP_H
4#define MENDOCINO_CHIP_H
Felix Held3c44c622022-01-10 20:57:29 +0100[diff] [blame]5
6#include <amdblocks/chip.h>
Felix Held556d1cc2022-02-02 22:11:52 +0100[diff] [blame]7#include <amdblocks/i2c.h>
Robert Ziebab3b27f72022-10-03 14:50:55 -0600[diff] [blame]8#include <amdblocks/pci_clk_req.h>
Felix Held3c44c622022-01-10 20:57:29 +0100[diff] [blame]9#include <gpio.h>
10#include <soc/i2c.h>
11#include <soc/southbridge.h>
12#include <drivers/i2c/designware/dw_i2c.h>
13#include <types.h>
Jon Murphy4f732422022-08-05 15:43:44 -0600[diff] [blame]14#include <vendorcode/amd/fsp/mendocino/FspUsb.h>
Felix Held3c44c622022-01-10 20:57:29 +0100[diff] [blame]15
Jon Murphy4f732422022-08-05 15:43:44 -0600[diff] [blame]16struct soc_amd_mendocino_config {
Felix Held3c44c622022-01-10 20:57:29 +0100[diff] [blame]17 struct soc_amd_common_config common_config;
18 u8 i2c_scl_reset;
19 struct dw_i2c_bus_config i2c[I2C_CTRLR_COUNT];
Felix Held556d1cc2022-02-02 22:11:52 +0100[diff] [blame]20 struct i2c_pad_control i2c_pad[I2C_CTRLR_COUNT];
Felix Held3c44c622022-01-10 20:57:29 +0100[diff] [blame]21
22 /* Enable S0iX support */
23 bool s0ix_enable;
24
25 enum {
26 DOWNCORE_AUTO = 0,
27 DOWNCORE_1 = 1, /* Run with 1 physical core */
28 DOWNCORE_2 = 3, /* Run with 2 physical cores */
29 DOWNCORE_3 = 4, /* Run with 3 physical cores */
30 DOWNCORE_4 = 6, /* Run with 4 physical cores */
31 DOWNCORE_5 = 8, /* Run with 5 physical cores */
32 DOWNCORE_6 = 9, /* Run with 6 physical cores */
33 DOWNCORE_7 = 10, /* Run with 7 physical cores */
34 } downcore_mode;
35 bool disable_smt; /* disable second thread on all physical cores */
36
37 uint8_t stt_control;
38 uint8_t stt_pcb_sensor_count;
39 uint16_t stt_min_limit;
40 uint16_t stt_m1;
41 uint16_t stt_m2;
42 uint16_t stt_m3;
43 uint16_t stt_m4;
44 uint16_t stt_m5;
45 uint16_t stt_m6;
46 uint16_t stt_c_apu;
47 uint16_t stt_c_gpu;
48 uint16_t stt_c_hs2;
49 uint16_t stt_alpha_apu;
50 uint16_t stt_alpha_gpu;
51 uint16_t stt_alpha_hs2;
52 uint16_t stt_skin_temp_apu;
53 uint16_t stt_skin_temp_gpu;
54 uint16_t stt_skin_temp_hs2;
55 uint16_t stt_error_coeff;
56 uint16_t stt_error_rate_coefficient;
57
Tim Van Pattenb06873f2022-09-06 09:56:52 -0600[diff] [blame]58 /* Default */
Felix Held3c44c622022-01-10 20:57:29 +0100[diff] [blame]59 uint8_t stapm_boost;
60 uint32_t stapm_time_constant_s;
61 uint32_t apu_only_sppt_limit;
62 uint32_t sustained_power_limit_mW;
63 uint32_t fast_ppt_limit_mW;
64 uint32_t slow_ppt_limit_mW;
65 uint32_t slow_ppt_time_constant_s;
66 uint32_t thermctl_limit_degreeC;
Tim Van Pattenb06873f2022-09-06 09:56:52 -0600[diff] [blame]67 uint32_t vrm_current_limit_mA;
68 uint32_t vrm_maximum_current_limit_mA;
69 uint32_t vrm_soc_current_limit_mA;
Tim Van Patten1cf0acd2022-09-15 17:15:56 -0600[diff] [blame]70 /* Throttle (e.g., Low/No Battery) */
71 uint32_t vrm_current_limit_throttle_mA;
72 uint32_t vrm_maximum_current_limit_throttle_mA;
73 uint32_t vrm_soc_current_limit_throttle_mA;
Felix Held3c44c622022-01-10 20:57:29 +0100[diff] [blame]74
Chris.Wang9ac09842022-12-13 14:31:38 +0800[diff] [blame]75 /* tablet mode.*/
76 uint32_t sustained_power_limit_mW_tablet;
77
EricKY Chengf7a09272022-10-17 13:10:50 +0800[diff] [blame]78 /* Thermal profile B*/
79 uint32_t fast_ppt_limit_mW_B;
80 uint32_t slow_ppt_limit_mW_B;
81 uint32_t slow_ppt_time_constant_s_B;
82 uint32_t sustained_power_limit_mW_B;
83 uint16_t stt_min_limit_B;
84 uint16_t stt_m1_B;
85 uint16_t stt_m2_B;
86 uint16_t stt_c_apu_B;
87 uint16_t stt_skin_temp_apu_B;
88
89 /* Thermal profile C*/
90 uint32_t fast_ppt_limit_mW_C;
91 uint32_t slow_ppt_limit_mW_C;
92 uint32_t slow_ppt_time_constant_s_C;
93 uint32_t sustained_power_limit_mW_C;
94 uint16_t stt_min_limit_C;
95 uint16_t stt_m1_C;
96 uint16_t stt_m2_C;
97 uint16_t stt_c_apu_C;
98 uint16_t stt_skin_temp_apu_C;
99
100 /* Thermal profile D*/
101 uint32_t fast_ppt_limit_mW_D;
102 uint32_t slow_ppt_limit_mW_D;
103 uint32_t slow_ppt_time_constant_s_D;
104 uint32_t sustained_power_limit_mW_D;
105 uint16_t stt_min_limit_D;
106 uint16_t stt_m1_D;
107 uint16_t stt_m2_D;
108 uint16_t stt_c_apu_D;
109 uint16_t stt_skin_temp_apu_D;
110
111 /* Thermal profile E*/
112 uint32_t fast_ppt_limit_mW_E;
113 uint32_t slow_ppt_limit_mW_E;
114 uint32_t slow_ppt_time_constant_s_E;
115 uint32_t sustained_power_limit_mW_E;
116 uint16_t stt_min_limit_E;
117 uint16_t stt_m1_E;
118 uint16_t stt_m2_E;
119 uint16_t stt_c_apu_E;
120 uint16_t stt_skin_temp_apu_E;
121
122
123 /* Thermal profile F*/
124 uint32_t fast_ppt_limit_mW_F;
125 uint32_t slow_ppt_limit_mW_F;
126 uint32_t slow_ppt_time_constant_s_F;
127 uint32_t sustained_power_limit_mW_F;
128 uint16_t stt_min_limit_F;
129 uint16_t stt_m1_F;
130 uint16_t stt_m2_F;
131 uint16_t stt_c_apu_F;
132 uint16_t stt_skin_temp_apu_F;
133
Felix Held3c44c622022-01-10 20:57:29 +0100[diff] [blame]134 uint8_t smartshift_enable;
135
136 uint8_t system_configuration;
137
Felix Held665476d2022-08-03 22:18:18 +0200[diff] [blame]138 uint8_t cppc_ctrl;
139 uint8_t cppc_perf_limit_max_range;
140 uint8_t cppc_perf_limit_min_range;
141 uint8_t cppc_epp_max_range;
142 uint8_t cppc_epp_min_range;
143 uint8_t cppc_preferred_cores;
144
Felix Held3c44c622022-01-10 20:57:29 +0100[diff] [blame]145 /* telemetry settings */
146 uint32_t telemetry_vddcrvddfull_scale_current_mA;
147 uint32_t telemetry_vddcrvddoffset;
148 uint32_t telemetry_vddcrsocfull_scale_current_mA;
149 uint32_t telemetry_vddcrsocoffset;
150
Felix Held3c44c622022-01-10 20:57:29 +0100[diff] [blame]151 /* The array index is the general purpose PCIe clock output number. Values in here
152 aren't the values written to the register to have the default to be always on. */
Robert Ziebab3b27f72022-10-03 14:50:55 -0600[diff] [blame]153 enum gpp_clk_req gpp_clk_config[GPP_CLK_OUTPUT_AVAILABLE];
Felix Held3c44c622022-01-10 20:57:29 +0100[diff] [blame]154
155 /* performance policy for the PCIe links: power consumption vs. link speed */
156 enum {
157 DXIO_PSPP_DISABLED = 0,
158 DXIO_PSPP_PERFORMANCE,
159 DXIO_PSPP_BALANCED,
160 DXIO_PSPP_POWERSAVE,
161 } pspp_policy;
162
163 uint8_t usb_phy_custom;
164 struct usb_phy_config usb_phy;
Chris.Wangad12b4f2022-12-28 17:07:48 +0800[diff] [blame]165 /* Set for PCIe optimization w/a and a double confirming on the result of PCIe Signal
166 Integrity is highly recommended. */
167 uint8_t dxio_tx_vboost_enable;
Felix Held3c44c622022-01-10 20:57:29 +0100[diff] [blame]168};
169
Jon Murphy4f732422022-08-05 15:43:44 -0600[diff] [blame]170#endif /* MENDOCINO_CHIP_H */